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hubxb.h
资源名称：linux-2.4.20.tar.gz　[点击查看]
上传用户：jlfgdled
上传日期：2013-04-10
资源大小：33168k
文件大小：43k
源码类别：

Linux/Unix编程

开发平台：

Unix_Linux

hubxb.h：源码内容
  1. /* $Id$
  2.  *
  3.  * This file is subject to the terms and conditions of the GNU General Public
  4.  * License.  See the file "COPYING" in the main directory of this archive
  5.  * for more details.
  6.  *
  7.  * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  8.  */
  9. #ifndef _ASM_IA64_SN_SN1_HUBXB_H
  10. #define _ASM_IA64_SN_SN1_HUBXB_H
  12. /************************************************************************
  13.  *                                                                      *
  14.  *      WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!  WARNING!!!      *
  15.  *                                                                      *
  16.  * This file is created by an automated script. Any (minimal) changes   *
  17.  * made manually to this  file should be made with care.                *
  18.  *                                                                      *
  19.  *               MAKE ALL ADDITIONS TO THE END OF THIS FILE             *
  20.  *                                                                      *
  21.  ************************************************************************/
  24. #define    XB_PARMS                  0x00700000    /*
  25.                                                     * Controls
  26.                                                     * crossbar-wide
  27.                                                     * parameters.
  28.                                                     */
  32. #define    XB_SLOW_GNT               0x00700008    /*
  33.                                                     * Controls wavefront
  34.                                                     * arbiter grant
  35.                                                     * frequency, used to
  36.                                                     * slow XB grants
  37.                                                     */
  41. #define    XB_SPEW_CONTROL           0x00700010    /*
  42.                                                     * Controls spew
  43.                                                     * settings (debug
  44.                                                     * only).
  45.                                                     */
  49. #define    XB_IOQ_ARB_TRIGGER        0x00700018    /*
  50.                                                     * Controls IOQ
  51.                                                     * trigger level
  52.                                                     */
  56. #define    XB_FIRST_ERROR            0x00700090    /*
  57.                                                     * Records the first
  58.                                                     * crossbar error
  59.                                                     * seen.
  60.                                                     */
  64. #define    XB_POQ0_ERROR             0x00700020    /*
  65.                                                     * POQ0 error
  66.                                                     * register.
  67.                                                     */
  71. #define    XB_PIQ0_ERROR             0x00700028    /*
  72.                                                     * PIQ0 error
  73.                                                     * register.
  74.                                                     */
  78. #define    XB_POQ1_ERROR             0x00700030    /*
  79.                                                     * POQ1 error
  80.                                                     * register.
  81.                                                     */
  85. #define    XB_PIQ1_ERROR             0x00700038    /*
  86.                                                     * PIQ1 error
  87.                                                     * register.
  88.                                                     */
  92. #define    XB_MP0_ERROR              0x00700040    /*
  93.                                                     * MOQ for PI0 error
  94.                                                     * register.
  95.                                                     */
  99. #define    XB_MP1_ERROR              0x00700048    /*
  100.                                                     * MOQ for PI1 error
  101.                                                     * register.
  102.                                                     */
  106. #define    XB_MMQ_ERROR              0x00700050    /*
  107.                                                     * MOQ for misc. (LB,
  108.                                                     * NI, II) error
  109.                                                     * register.
  110.                                                     */
  114. #define    XB_MIQ_ERROR              0x00700058    /*
  115.                                                     * MIQ error register,
  116.                                                     * addtional MIQ
  117.                                                     * errors are logged
  118.                                                     * in MD "Input
  119.                                                     * Error
  120.                                                     * Registers".
  121.                                                     */
  125. #define    XB_NOQ_ERROR              0x00700060    /* NOQ error register.    */
  129. #define    XB_NIQ_ERROR              0x00700068    /* NIQ error register.    */
  133. #define    XB_IOQ_ERROR              0x00700070    /* IOQ error register.    */
  137. #define    XB_IIQ_ERROR              0x00700078    /* IIQ error register.    */
  141. #define    XB_LOQ_ERROR              0x00700080    /* LOQ error register.    */
  145. #define    XB_LIQ_ERROR              0x00700088    /* LIQ error register.    */
  149. #define    XB_DEBUG_DATA_CTL         0x00700098    /*
  150.                                                     * Debug Datapath
  151.                                                     * Select
  152.                                                     */
  156. #define    XB_DEBUG_ARB_CTL          0x007000A0    /*
  157.                                                     * XB master debug
  158.                                                     * control
  159.                                                     */
  163. #define    XB_POQ0_ERROR_CLEAR       0x00700120    /*
  164.                                                     * Clears
  165.                                                     * XB_POQ0_ERROR
  166.                                                     * register.
  167.                                                     */
  171. #define    XB_PIQ0_ERROR_CLEAR       0x00700128    /*
  172.                                                     * Clears
  173.                                                     * XB_PIQ0_ERROR
  174.                                                     * register.
  175.                                                     */
  179. #define    XB_POQ1_ERROR_CLEAR       0x00700130    /*
  180.                                                     * Clears
  181.                                                     * XB_POQ1_ERROR
  182.                                                     * register.
  183.                                                     */
  187. #define    XB_PIQ1_ERROR_CLEAR       0x00700138    /*
  188.                                                     * Clears
  189.                                                     * XB_PIQ1_ERROR
  190.                                                     * register.
  191.                                                     */
  195. #define    XB_MP0_ERROR_CLEAR        0x00700140    /*
  196.                                                     * Clears XB_MP0_ERROR
  197.                                                     * register.
  198.                                                     */
  202. #define    XB_MP1_ERROR_CLEAR        0x00700148    /*
  203.                                                     * Clears XB_MP1_ERROR
  204.                                                     * register.
  205.                                                     */
  209. #define    XB_MMQ_ERROR_CLEAR        0x00700150    /*
  210.                                                     * Clears XB_MMQ_ERROR
  211.                                                     * register.
  212.                                                     */
  216. #define    XB_XM_MIQ_ERROR_CLEAR     0x00700158    /*
  217.                                                     * Clears XB_MIQ_ERROR
  218.                                                     * register
  219.                                                     */
  223. #define    XB_NOQ_ERROR_CLEAR        0x00700160    /*
  224.                                                     * Clears XB_NOQ_ERROR
  225.                                                     * register.
  226.                                                     */
  230. #define    XB_NIQ_ERROR_CLEAR        0x00700168    /*
  231.                                                     * Clears XB_NIQ_ERROR
  232.                                                     * register.
  233.                                                     */
  237. #define    XB_IOQ_ERROR_CLEAR        0x00700170    /*
  238.                                                     * Clears XB_IOQ
  239.                                                     * _ERROR register.
  240.                                                     */
  244. #define    XB_IIQ_ERROR_CLEAR        0x00700178    /*
  245.                                                     * Clears XB_IIQ
  246.                                                     * _ERROR register.
  247.                                                     */
  251. #define    XB_LOQ_ERROR_CLEAR        0x00700180    /*
  252.                                                     * Clears XB_LOQ_ERROR
  253.                                                     * register.
  254.                                                     */
  258. #define    XB_LIQ_ERROR_CLEAR        0x00700188    /*
  259.                                                     * Clears XB_LIQ_ERROR
  260.                                                     * register.
  261.                                                     */
  265. #define    XB_FIRST_ERROR_CLEAR      0x00700190    /*
  266.                                                     * Clears
  267.                                                     * XB_FIRST_ERROR
  268.                                                     * register
  269.                                                     */
  275. #ifndef __ASSEMBLY__
  277. /************************************************************************
  278.  *                                                                      *
  279.  *  Access to parameters which control various aspects of the           *
  280.  * crossbar's operation.                                                *
  281.  *                                                                      *
  282.  ************************************************************************/
  287. #ifdef LITTLE_ENDIAN
  289. typedef union xb_parms_u {
  290. bdrkreg_t xb_parms_regval;
  291. struct  {
  292. bdrkreg_t p_byp_en                  :  1;
  293.                 bdrkreg_t       p_rsrvd_1                 :      3;
  294.                 bdrkreg_t       p_age_wrap                :      8;
  295.                 bdrkreg_t       p_deadlock_to_wrap        :     20;
  296.                 bdrkreg_t       p_tail_to_wrap            :     20;
  297.                 bdrkreg_t       p_rsrvd                   :     12;
  298. } xb_parms_fld_s;
  299. } xb_parms_u_t;
  301. #else
  303. typedef union xb_parms_u {
  304. bdrkreg_t xb_parms_regval;
  305. struct {
  306. bdrkreg_t p_rsrvd   : 12;
  307. bdrkreg_t p_tail_to_wrap   : 20;
  308. bdrkreg_t p_deadlock_to_wrap   : 20;
  309. bdrkreg_t p_age_wrap   :  8;
  310. bdrkreg_t p_rsrvd_1   :  3;
  311. bdrkreg_t p_byp_en   :  1;
  312. } xb_parms_fld_s;
  313. } xb_parms_u_t;
  315. #endif
  320. /************************************************************************
  321.  *                                                                      *
  322.  *  Sets the period of wavefront grants given to each unit. The         *
  323.  * register's value corresponds to the number of cycles between each    *
  324.  * wavefront grant opportunity given to the requesting unit. If set     *
  325.  * to 0xF, no grants are given to this unit. If set to 0xE, the unit    *
  326.  * is granted at the slowest rate (sometimes called "molasses mode").   *
  327.  * This feature can be used to apply backpressure to a unit's output    *
  328.  * queue(s). The setting does not affect bypass grants.                 *
  329.  *                                                                      *
  330.  ************************************************************************/
  335. #ifdef LITTLE_ENDIAN
  337. typedef union xb_slow_gnt_u {
  338. bdrkreg_t xb_slow_gnt_regval;
  339. struct  {
  340. bdrkreg_t sg_lb_slow_gnt            :  4;
  341.                 bdrkreg_t       sg_ii_slow_gnt            :      4;
  342.                 bdrkreg_t       sg_ni_slow_gnt            :      4;
  343.                 bdrkreg_t       sg_mmq_slow_gnt           :      4;
  344.                 bdrkreg_t       sg_mp1_slow_gnt           :      4;
  345.                 bdrkreg_t       sg_mp0_slow_gnt           :      4;
  346.                 bdrkreg_t       sg_pi1_slow_gnt           :      4;
  347.                 bdrkreg_t       sg_pi0_slow_gnt           :      4;
  348.                 bdrkreg_t       sg_rsrvd                  :     32;
  349. } xb_slow_gnt_fld_s;
  350. } xb_slow_gnt_u_t;
  352. #else
  354. typedef union xb_slow_gnt_u {
  355. bdrkreg_t xb_slow_gnt_regval;
  356. struct {
  357. bdrkreg_t sg_rsrvd   : 32;
  358. bdrkreg_t sg_pi0_slow_gnt   :  4;
  359. bdrkreg_t sg_pi1_slow_gnt   :  4;
  360. bdrkreg_t sg_mp0_slow_gnt   :  4;
  361. bdrkreg_t sg_mp1_slow_gnt   :  4;
  362. bdrkreg_t sg_mmq_slow_gnt   :  4;
  363. bdrkreg_t sg_ni_slow_gnt   :  4;
  364. bdrkreg_t sg_ii_slow_gnt   :  4;
  365. bdrkreg_t sg_lb_slow_gnt   :  4;
  366. } xb_slow_gnt_fld_s;
  367. } xb_slow_gnt_u_t;
  369. #endif
  374. /************************************************************************
  375.  *                                                                      *
  376.  *  Enables snooping of internal crossbar traffic by spewing all        *
  377.  * traffic across a selected crossbar point to the PI1 port. Only one   *
  378.  * bit should be set at any one time, and any bit set will preclude     *
  379.  * using the P1 for anything but a debug connection.                    *
  380.  *                                                                      *
  381.  ************************************************************************/
  386. #ifdef LITTLE_ENDIAN
  388. typedef union xb_spew_control_u {
  389. bdrkreg_t xb_spew_control_regval;
  390. struct  {
  391. bdrkreg_t sc_snoop_liq              :  1;
  392.                 bdrkreg_t       sc_snoop_iiq              :      1;
  393.                 bdrkreg_t       sc_snoop_niq              :      1;
  394.                 bdrkreg_t       sc_snoop_miq              :      1;
  395.                 bdrkreg_t       sc_snoop_piq0             :      1;
  396.                 bdrkreg_t       sc_snoop_loq              :      1;
  397.                 bdrkreg_t       sc_snoop_ioq              :      1;
  398.                 bdrkreg_t       sc_snoop_noq              :      1;
  399.                 bdrkreg_t       sc_snoop_mmq              :      1;
  400.                 bdrkreg_t       sc_snoop_mp0              :      1;
  401.                 bdrkreg_t       sc_snoop_poq0             :      1;
  402.                 bdrkreg_t       sc_rsrvd                  :     53;
  403. } xb_spew_control_fld_s;
  404. } xb_spew_control_u_t;
  406. #else
  408. typedef union xb_spew_control_u {
  409. bdrkreg_t xb_spew_control_regval;
  410. struct {
  411. bdrkreg_t sc_rsrvd   : 53;
  412. bdrkreg_t sc_snoop_poq0   :  1;
  413. bdrkreg_t sc_snoop_mp0   :  1;
  414. bdrkreg_t sc_snoop_mmq   :  1;
  415. bdrkreg_t sc_snoop_noq   :  1;
  416. bdrkreg_t sc_snoop_ioq   :  1;
  417. bdrkreg_t sc_snoop_loq   :  1;
  418. bdrkreg_t sc_snoop_piq0   :  1;
  419. bdrkreg_t sc_snoop_miq   :  1;
  420. bdrkreg_t sc_snoop_niq   :  1;
  421. bdrkreg_t sc_snoop_iiq   :  1;
  422. bdrkreg_t sc_snoop_liq   :  1;
  423. } xb_spew_control_fld_s;
  424. } xb_spew_control_u_t;
  426. #endif
  431. /************************************************************************
  432.  *                                                                      *
  433.  *  Number of clocks the IOQ will wait before beginning XB              *
  434.  * arbitration. This is set so that the slower IOQ data rate can        *
  435.  * catch up up with the XB data rate in the IOQ buffer.                 *
  436.  *                                                                      *
  437.  ************************************************************************/
  442. #ifdef LITTLE_ENDIAN
  444. typedef union xb_ioq_arb_trigger_u {
  445. bdrkreg_t xb_ioq_arb_trigger_regval;
  446. struct  {
  447. bdrkreg_t iat_ioq_arb_trigger       :  4;
  448.         bdrkreg_t       iat_rsrvd                 :     60;
  449. } xb_ioq_arb_trigger_fld_s;
  450. } xb_ioq_arb_trigger_u_t;
  452. #else
  454. typedef union xb_ioq_arb_trigger_u {
  455. bdrkreg_t xb_ioq_arb_trigger_regval;
  456. struct {
  457. bdrkreg_t iat_rsrvd   : 60;
  458. bdrkreg_t iat_ioq_arb_trigger   :  4;
  459. } xb_ioq_arb_trigger_fld_s;
  460. } xb_ioq_arb_trigger_u_t;
  462. #endif
  467. /************************************************************************
  468.  *                                                                      *
  469.  *  Records errors seen by POQ0.Can be written to test software, will   *
  470.  * cause an interrupt.                                                  *
  471.  *                                                                      *
  472.  ************************************************************************/
  477. #ifdef LITTLE_ENDIAN
  479. typedef union xb_poq0_error_u {
  480. bdrkreg_t xb_poq0_error_regval;
  481. struct  {
  482. bdrkreg_t pe_invalid_xsel           :  2;
  483.                 bdrkreg_t       pe_rsrvd_3                :      2;
  484.                 bdrkreg_t       pe_overflow               :      2;
  485.                 bdrkreg_t       pe_rsrvd_2                :      2;
  486.                 bdrkreg_t       pe_underflow              :      2;
  487.                 bdrkreg_t       pe_rsrvd_1                :      2;
  488.                 bdrkreg_t       pe_tail_timeout           :      2;
  489.                 bdrkreg_t       pe_unused                 :      6;
  490.                 bdrkreg_t       pe_rsrvd                  :     44;
  491. } xb_poq0_error_fld_s;
  492. } xb_poq0_error_u_t;
  494. #else
  496. typedef union xb_poq0_error_u {
  497. bdrkreg_t xb_poq0_error_regval;
  498. struct {
  499. bdrkreg_t pe_rsrvd   : 44;
  500. bdrkreg_t pe_unused   :  6;
  501. bdrkreg_t pe_tail_timeout   :  2;
  502. bdrkreg_t pe_rsrvd_1   :  2;
  503. bdrkreg_t pe_underflow   :  2;
  504. bdrkreg_t pe_rsrvd_2   :  2;
  505. bdrkreg_t pe_overflow   :  2;
  506. bdrkreg_t pe_rsrvd_3   :  2;
  507. bdrkreg_t pe_invalid_xsel   :  2;
  508. } xb_poq0_error_fld_s;
  509. } xb_poq0_error_u_t;
  511. #endif
  516. /************************************************************************
  517.  *                                                                      *
  518.  *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
  519.  * precludes PIQ underflow.                                             *
  520.  *                                                                      *
  521.  ************************************************************************/
  526. #ifdef LITTLE_ENDIAN
  528. typedef union xb_piq0_error_u {
  529. bdrkreg_t xb_piq0_error_regval;
  530. struct  {
  531. bdrkreg_t pe_overflow               :  2;
  532.                 bdrkreg_t       pe_rsrvd_1                :      2;
  533.                 bdrkreg_t       pe_deadlock_timeout       :      2;
  534.                 bdrkreg_t       pe_rsrvd                  :     58;
  535. } xb_piq0_error_fld_s;
  536. } xb_piq0_error_u_t;
  538. #else
  540. typedef union xb_piq0_error_u {
  541. bdrkreg_t xb_piq0_error_regval;
  542. struct {
  543. bdrkreg_t pe_rsrvd   : 58;
  544. bdrkreg_t pe_deadlock_timeout   :  2;
  545. bdrkreg_t pe_rsrvd_1   :  2;
  546. bdrkreg_t pe_overflow   :  2;
  547. } xb_piq0_error_fld_s;
  548. } xb_piq0_error_u_t;
  550. #endif
  555. /************************************************************************
  556.  *                                                                      *
  557.  *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
  558.  * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
  559.  * errors are possible.                                                 *
  560.  *                                                                      *
  561.  ************************************************************************/
  566. #ifdef LITTLE_ENDIAN
  568. typedef union xb_mp0_error_u {
  569. bdrkreg_t xb_mp0_error_regval;
  570. struct  {
  571. bdrkreg_t me_rsrvd_3                :  4;
  572.                 bdrkreg_t       me_overflow               :      2;
  573.                 bdrkreg_t       me_rsrvd_2                :      2;
  574.                 bdrkreg_t       me_underflow              :      2;
  575.                 bdrkreg_t       me_rsrvd_1                :      2;
  576.                 bdrkreg_t       me_tail_timeout           :      2;
  577.                 bdrkreg_t       me_rsrvd                  :     50;
  578. } xb_mp0_error_fld_s;
  579. } xb_mp0_error_u_t;
  581. #else
  583. typedef union xb_mp0_error_u {
  584. bdrkreg_t xb_mp0_error_regval;
  585. struct {
  586. bdrkreg_t me_rsrvd   : 50;
  587. bdrkreg_t me_tail_timeout   :  2;
  588. bdrkreg_t me_rsrvd_1   :  2;
  589. bdrkreg_t me_underflow   :  2;
  590. bdrkreg_t me_rsrvd_2   :  2;
  591. bdrkreg_t me_overflow   :  2;
  592. bdrkreg_t me_rsrvd_3   :  4;
  593. } xb_mp0_error_fld_s;
  594. } xb_mp0_error_u_t;
  596. #endif
  601. /************************************************************************
  602.  *                                                                      *
  603.  *  Records errors seen by MIQ.                                         *
  604.  *                                                                      *
  605.  ************************************************************************/
  609. #ifdef LITTLE_ENDIAN
  611. typedef union xb_miq_error_u {
  612. bdrkreg_t xb_miq_error_regval;
  613. struct  {
  614. bdrkreg_t me_rsrvd_1                :  4;
  615.                 bdrkreg_t       me_deadlock_timeout       :      4;
  616.                 bdrkreg_t       me_rsrvd                  :     56;
  617. } xb_miq_error_fld_s;
  618. } xb_miq_error_u_t;
  620. #else
  622. typedef union xb_miq_error_u {
  623. bdrkreg_t xb_miq_error_regval;
  624. struct {
  625. bdrkreg_t me_rsrvd   : 56;
  626. bdrkreg_t me_deadlock_timeout   :  4;
  627. bdrkreg_t me_rsrvd_1   :  4;
  628. } xb_miq_error_fld_s;
  629. } xb_miq_error_u_t;
  631. #endif
  636. /************************************************************************
  637.  *                                                                      *
  638.  *  Records errors seen by NOQ.                                         *
  639.  *                                                                      *
  640.  ************************************************************************/
  645. #ifdef LITTLE_ENDIAN
  647. typedef union xb_noq_error_u {
  648. bdrkreg_t xb_noq_error_regval;
  649. struct  {
  650. bdrkreg_t ne_rsvd                   :  4;
  651.                 bdrkreg_t       ne_overflow               :      4;
  652.                 bdrkreg_t       ne_underflow              :      4;
  653.                 bdrkreg_t       ne_tail_timeout           :      4;
  654.                 bdrkreg_t       ne_rsrvd                  :     48;
  655. } xb_noq_error_fld_s;
  656. } xb_noq_error_u_t;
  658. #else
  660. typedef union xb_noq_error_u {
  661. bdrkreg_t xb_noq_error_regval;
  662. struct {
  663. bdrkreg_t ne_rsrvd   : 48;
  664. bdrkreg_t ne_tail_timeout   :  4;
  665. bdrkreg_t ne_underflow   :  4;
  666. bdrkreg_t ne_overflow   :  4;
  667. bdrkreg_t ne_rsvd   :  4;
  668. } xb_noq_error_fld_s;
  669. } xb_noq_error_u_t;
  671. #endif
  676. /************************************************************************
  677.  *                                                                      *
  678.  *  Records errors seen by LOQ.                                         *
  679.  *                                                                      *
  680.  ************************************************************************/
  685. #ifdef LITTLE_ENDIAN
  687. typedef union xb_loq_error_u {
  688. bdrkreg_t xb_loq_error_regval;
  689. struct  {
  690. bdrkreg_t le_invalid_xsel           :  2;
  691.                 bdrkreg_t       le_rsrvd_1                :      6;
  692.                 bdrkreg_t       le_underflow              :      2;
  693.                 bdrkreg_t       le_rsvd                   :      2;
  694.                 bdrkreg_t       le_tail_timeout           :      2;
  695.                 bdrkreg_t       le_rsrvd                  :     50;
  696. } xb_loq_error_fld_s;
  697. } xb_loq_error_u_t;
  699. #else
  701. typedef union xb_loq_error_u {
  702. bdrkreg_t xb_loq_error_regval;
  703. struct {
  704. bdrkreg_t le_rsrvd   : 50;
  705. bdrkreg_t le_tail_timeout   :  2;
  706. bdrkreg_t le_rsvd   :  2;
  707. bdrkreg_t le_underflow   :  2;
  708. bdrkreg_t le_rsrvd_1   :  6;
  709. bdrkreg_t le_invalid_xsel   :  2;
  710. } xb_loq_error_fld_s;
  711. } xb_loq_error_u_t;
  713. #endif
  718. /************************************************************************
  719.  *                                                                      *
  720.  *  Records errors seen by LIQ. Note that the LIQ only records errors   *
  721.  * for the request channel. The reply channel can never deadlock or     *
  722.  * overflow because it does not have hardware flow control.             *
  723.  *                                                                      *
  724.  ************************************************************************/
  729. #ifdef LITTLE_ENDIAN
  731. typedef union xb_liq_error_u {
  732. bdrkreg_t xb_liq_error_regval;
  733. struct  {
  734. bdrkreg_t le_overflow               :  1;
  735.                 bdrkreg_t       le_rsrvd_1                :      3;
  736.                 bdrkreg_t       le_deadlock_timeout       :      1;
  737.                 bdrkreg_t       le_rsrvd                  :     59;
  738. } xb_liq_error_fld_s;
  739. } xb_liq_error_u_t;
  741. #else
  743. typedef union xb_liq_error_u {
  744. bdrkreg_t xb_liq_error_regval;
  745. struct {
  746. bdrkreg_t le_rsrvd   : 59;
  747. bdrkreg_t le_deadlock_timeout   :  1;
  748. bdrkreg_t le_rsrvd_1   :  3;
  749. bdrkreg_t le_overflow   :  1;
  750. } xb_liq_error_fld_s;
  751. } xb_liq_error_u_t;
  753. #endif
  758. /************************************************************************
  759.  *                                                                      *
  760.  *  First error is latched whenever the Valid bit is clear and an       *
  761.  * error occurs. Any valid bit on in this register causes an            *
  762.  * interrupt to PI0 and PI1. This interrupt bit will persist until      *
  763.  * the specific error register to capture the error is cleared, then    *
  764.  * the FIRST_ERROR register is cleared (in that oder.) The              *
  765.  * FIRST_ERROR register is not writable, but will be set when any of    *
  766.  * the corresponding error registers are written by software.           *
  767.  *                                                                      *
  768.  ************************************************************************/
  773. #ifdef LITTLE_ENDIAN
  775. typedef union xb_first_error_u {
  776. bdrkreg_t xb_first_error_regval;
  777. struct  {
  778. bdrkreg_t fe_type                   :  4;
  779.                 bdrkreg_t       fe_channel                :      4;
  780.                 bdrkreg_t       fe_source                 :      4;
  781.                 bdrkreg_t       fe_valid                  :      1;
  782.                 bdrkreg_t       fe_rsrvd                  :     51;
  783. } xb_first_error_fld_s;
  784. } xb_first_error_u_t;
  786. #else
  788. typedef union xb_first_error_u {
  789. bdrkreg_t xb_first_error_regval;
  790. struct {
  791. bdrkreg_t fe_rsrvd   : 51;
  792. bdrkreg_t fe_valid   :  1;
  793. bdrkreg_t fe_source   :  4;
  794. bdrkreg_t fe_channel   :  4;
  795. bdrkreg_t fe_type   :  4;
  796. } xb_first_error_fld_s;
  797. } xb_first_error_u_t;
  799. #endif
  804. /************************************************************************
  805.  *                                                                      *
  806.  *  Controls DEBUG_DATA mux setting. Allows user to watch the output    *
  807.  * of any OQ or input of any IQ on the DEBUG port. Note that bits       *
  808.  * 13:0 are one-hot. If more than one bit is set in [13:0], the debug   *
  809.  * output is undefined. Details on the debug output lines can be        *
  810.  * found in the XB chapter of the Bedrock Interface Specification.      *
  811.  *                                                                      *
  812.  ************************************************************************/
  817. #ifdef LITTLE_ENDIAN
  819. typedef union xb_debug_data_ctl_u {
  820. bdrkreg_t xb_debug_data_ctl_regval;
  821. struct  {
  822. bdrkreg_t ddc_observe_liq_traffic   :  1;
  823.                 bdrkreg_t       ddc_observe_iiq_traffic   :      1;
  824.                 bdrkreg_t       ddc_observe_niq_traffic   :      1;
  825.                 bdrkreg_t       ddc_observe_miq_traffic   :      1;
  826.                 bdrkreg_t       ddc_observe_piq1_traffic  :      1;
  827.                 bdrkreg_t       ddc_observe_piq0_traffic  :      1;
  828.                 bdrkreg_t       ddc_observe_loq_traffic   :      1;
  829.                 bdrkreg_t       ddc_observe_ioq_traffic   :      1;
  830.                 bdrkreg_t       ddc_observe_noq_traffic   :      1;
  831.                 bdrkreg_t       ddc_observe_mp1_traffic   :      1;
  832.                 bdrkreg_t       ddc_observe_mp0_traffic   :      1;
  833.                 bdrkreg_t       ddc_observe_mmq_traffic   :      1;
  834.                 bdrkreg_t       ddc_observe_poq1_traffic  :      1;
  835.                 bdrkreg_t       ddc_observe_poq0_traffic  :      1;
  836.                 bdrkreg_t       ddc_observe_source_field  :      1;
  837.                 bdrkreg_t       ddc_observe_lodata        :      1;
  838.                 bdrkreg_t       ddc_rsrvd                 :     48;
  839. } xb_debug_data_ctl_fld_s;
  840. } xb_debug_data_ctl_u_t;
  842. #else
  844. typedef union xb_debug_data_ctl_u {
  845. bdrkreg_t xb_debug_data_ctl_regval;
  846. struct {
  847. bdrkreg_t ddc_rsrvd   : 48;
  848. bdrkreg_t ddc_observe_lodata   :  1;
  849. bdrkreg_t ddc_observe_source_field  :  1;
  850. bdrkreg_t ddc_observe_poq0_traffic  :  1;
  851. bdrkreg_t ddc_observe_poq1_traffic  :  1;
  852. bdrkreg_t ddc_observe_mmq_traffic   :  1;
  853. bdrkreg_t ddc_observe_mp0_traffic   :  1;
  854. bdrkreg_t ddc_observe_mp1_traffic   :  1;
  855. bdrkreg_t ddc_observe_noq_traffic   :  1;
  856. bdrkreg_t ddc_observe_ioq_traffic   :  1;
  857. bdrkreg_t ddc_observe_loq_traffic   :  1;
  858. bdrkreg_t ddc_observe_piq0_traffic  :  1;
  859. bdrkreg_t ddc_observe_piq1_traffic  :  1;
  860. bdrkreg_t ddc_observe_miq_traffic   :  1;
  861. bdrkreg_t ddc_observe_niq_traffic   :  1;
  862. bdrkreg_t ddc_observe_iiq_traffic   :  1;
  863. bdrkreg_t ddc_observe_liq_traffic   :  1;
  864. } xb_debug_data_ctl_fld_s;
  865. } xb_debug_data_ctl_u_t;
  867. #endif
  872. /************************************************************************
  873.  *                                                                      *
  874.  *  Controls debug mux setting for XB Input/Output Queues and           *
  875.  * Arbiter. Can select one of the following values. Details on the      *
  876.  * debug output lines can be found in the XB chapter of the Bedrock     *
  877.  * Interface Specification.                                             *
  878.  *                                                                      *
  879.  ************************************************************************/
  884. #ifdef LITTLE_ENDIAN
  886. typedef union xb_debug_arb_ctl_u {
  887. bdrkreg_t xb_debug_arb_ctl_regval;
  888. struct  {
  889. bdrkreg_t dac_xb_debug_select       :  3;
  890. bdrkreg_t       dac_rsrvd                 :     61;
  891. } xb_debug_arb_ctl_fld_s;
  892. } xb_debug_arb_ctl_u_t;
  894. #else
  896. typedef union xb_debug_arb_ctl_u {
  897.         bdrkreg_t       xb_debug_arb_ctl_regval;
  898.         struct  {
  899.                 bdrkreg_t       dac_rsrvd                 :     61;
  900.                 bdrkreg_t       dac_xb_debug_select       :      3;
  901.         } xb_debug_arb_ctl_fld_s;
  902. } xb_debug_arb_ctl_u_t;
  904. #endif
  909. /************************************************************************
  910.  *                                                                      *
  911.  *  Records errors seen by POQ0.Can be written to test software, will   *
  912.  * cause an interrupt.                                                  *
  913.  *                                                                      *
  914.  ************************************************************************/
  919. #ifdef LITTLE_ENDIAN
  921. typedef union xb_poq0_error_clear_u {
  922. bdrkreg_t xb_poq0_error_clear_regval;
  923. struct  {
  924. bdrkreg_t pec_invalid_xsel          :  2;
  925.                 bdrkreg_t       pec_rsrvd_3               :      2;
  926.                 bdrkreg_t       pec_overflow              :      2;
  927.                 bdrkreg_t       pec_rsrvd_2               :      2;
  928.                 bdrkreg_t       pec_underflow             :      2;
  929.                 bdrkreg_t       pec_rsrvd_1               :      2;
  930.                 bdrkreg_t       pec_tail_timeout          :      2;
  931.                 bdrkreg_t       pec_unused                :      6;
  932.                 bdrkreg_t       pec_rsrvd                 :     44;
  933. } xb_poq0_error_clear_fld_s;
  934. } xb_poq0_error_clear_u_t;
  936. #else
  938. typedef union xb_poq0_error_clear_u {
  939. bdrkreg_t xb_poq0_error_clear_regval;
  940. struct {
  941. bdrkreg_t pec_rsrvd   : 44;
  942. bdrkreg_t pec_unused   :  6;
  943. bdrkreg_t pec_tail_timeout   :  2;
  944. bdrkreg_t pec_rsrvd_1   :  2;
  945. bdrkreg_t pec_underflow   :  2;
  946. bdrkreg_t pec_rsrvd_2   :  2;
  947. bdrkreg_t pec_overflow   :  2;
  948. bdrkreg_t pec_rsrvd_3   :  2;
  949. bdrkreg_t pec_invalid_xsel   :  2;
  950. } xb_poq0_error_clear_fld_s;
  951. } xb_poq0_error_clear_u_t;
  953. #endif
  958. /************************************************************************
  959.  *                                                                      *
  960.  *  Records errors seen by PIQ0. Note that the PIQ/PI interface         *
  961.  * precludes PIQ underflow.                                             *
  962.  *                                                                      *
  963.  ************************************************************************/
  968. #ifdef LITTLE_ENDIAN
  970. typedef union xb_piq0_error_clear_u {
  971. bdrkreg_t xb_piq0_error_clear_regval;
  972. struct  {
  973. bdrkreg_t pec_overflow              :  2;
  974.                 bdrkreg_t       pec_rsrvd_1               :      2;
  975.                 bdrkreg_t       pec_deadlock_timeout      :      2;
  976.                 bdrkreg_t       pec_rsrvd                 :     58;
  977. } xb_piq0_error_clear_fld_s;
  978. } xb_piq0_error_clear_u_t;
  980. #else
  982. typedef union xb_piq0_error_clear_u {
  983. bdrkreg_t xb_piq0_error_clear_regval;
  984. struct {
  985. bdrkreg_t pec_rsrvd   : 58;
  986. bdrkreg_t pec_deadlock_timeout   :  2;
  987. bdrkreg_t pec_rsrvd_1   :  2;
  988. bdrkreg_t pec_overflow   :  2;
  989. } xb_piq0_error_clear_fld_s;
  990. } xb_piq0_error_clear_u_t;
  992. #endif
  997. /************************************************************************
  998.  *                                                                      *
  999.  *  Records errors seen by MP0 queue (the MOQ for processor 0). Since   *
  1000.  * the xselect is decoded on the MD/MOQ interface, no invalid xselect   *
  1001.  * errors are possible.                                                 *
  1002.  *                                                                      *
  1003.  ************************************************************************/
  1008. #ifdef LITTLE_ENDIAN
  1010. typedef union xb_mp0_error_clear_u {
  1011. bdrkreg_t xb_mp0_error_clear_regval;
  1012. struct  {
  1013. bdrkreg_t mec_rsrvd_3               :  4;
  1014.                 bdrkreg_t       mec_overflow              :      2;
  1015.                 bdrkreg_t       mec_rsrvd_2               :      2;
  1016.                 bdrkreg_t       mec_underflow             :      2;
  1017.                 bdrkreg_t       mec_rsrvd_1               :      2;
  1018.                 bdrkreg_t       mec_tail_timeout          :      2;
  1019.                 bdrkreg_t       mec_rsrvd                 :     50;
  1020. } xb_mp0_error_clear_fld_s;
  1021. } xb_mp0_error_clear_u_t;
  1023. #else
  1025. typedef union xb_mp0_error_clear_u {
  1026. bdrkreg_t xb_mp0_error_clear_regval;
  1027. struct {
  1028. bdrkreg_t mec_rsrvd   : 50;
  1029. bdrkreg_t mec_tail_timeout   :  2;
  1030. bdrkreg_t mec_rsrvd_1   :  2;
  1031. bdrkreg_t mec_underflow   :  2;
  1032. bdrkreg_t mec_rsrvd_2   :  2;
  1033. bdrkreg_t mec_overflow   :  2;
  1034. bdrkreg_t mec_rsrvd_3   :  4;
  1035. } xb_mp0_error_clear_fld_s;
  1036. } xb_mp0_error_clear_u_t;
  1038. #endif
  1043. /************************************************************************
  1044.  *                                                                      *
  1045.  *  Records errors seen by MIQ.                                         *
  1046.  *                                                                      *
  1047.  ************************************************************************/
  1052. #ifdef LITTLE_ENDIAN
  1054. typedef union xb_xm_miq_error_clear_u {
  1055. bdrkreg_t xb_xm_miq_error_clear_regval;
  1056. struct  {
  1057. bdrkreg_t xmec_rsrvd_1              :  4;
  1058.                 bdrkreg_t       xmec_deadlock_timeout     :      4;
  1059.                 bdrkreg_t       xmec_rsrvd                :     56;
  1060. } xb_xm_miq_error_clear_fld_s;
  1061. } xb_xm_miq_error_clear_u_t;
  1063. #else
  1065. typedef union xb_xm_miq_error_clear_u {
  1066. bdrkreg_t xb_xm_miq_error_clear_regval;
  1067. struct {
  1068. bdrkreg_t xmec_rsrvd   : 56;
  1069. bdrkreg_t xmec_deadlock_timeout   :  4;
  1070. bdrkreg_t xmec_rsrvd_1   :  4;
  1071. } xb_xm_miq_error_clear_fld_s;
  1072. } xb_xm_miq_error_clear_u_t;
  1074. #endif
  1079. /************************************************************************
  1080.  *                                                                      *
  1081.  *  Records errors seen by NOQ.                                         *
  1082.  *                                                                      *
  1083.  ************************************************************************/
  1088. #ifdef LITTLE_ENDIAN
  1090. typedef union xb_noq_error_clear_u {
  1091. bdrkreg_t xb_noq_error_clear_regval;
  1092. struct  {
  1093. bdrkreg_t nec_rsvd                  :  4;
  1094.                 bdrkreg_t       nec_overflow              :      4;
  1095.                 bdrkreg_t       nec_underflow             :      4;
  1096.                 bdrkreg_t       nec_tail_timeout          :      4;
  1097.                 bdrkreg_t       nec_rsrvd                 :     48;
  1098. } xb_noq_error_clear_fld_s;
  1099. } xb_noq_error_clear_u_t;
  1101. #else
  1103. typedef union xb_noq_error_clear_u {
  1104. bdrkreg_t xb_noq_error_clear_regval;
  1105. struct {
  1106. bdrkreg_t nec_rsrvd   : 48;
  1107. bdrkreg_t nec_tail_timeout   :  4;
  1108. bdrkreg_t nec_underflow   :  4;
  1109. bdrkreg_t nec_overflow   :  4;
  1110. bdrkreg_t nec_rsvd   :  4;
  1111. } xb_noq_error_clear_fld_s;
  1112. } xb_noq_error_clear_u_t;
  1114. #endif
  1119. /************************************************************************
  1120.  *                                                                      *
  1121.  *  Records errors seen by LOQ.                                         *
  1122.  *                                                                      *
  1123.  ************************************************************************/
  1128. #ifdef LITTLE_ENDIAN
  1130. typedef union xb_loq_error_clear_u {
  1131. bdrkreg_t xb_loq_error_clear_regval;
  1132. struct  {
  1133. bdrkreg_t lec_invalid_xsel          :  2;
  1134.                 bdrkreg_t       lec_rsrvd_1               :      6;
  1135.                 bdrkreg_t       lec_underflow             :      2;
  1136.                 bdrkreg_t       lec_rsvd                  :      2;
  1137.                 bdrkreg_t       lec_tail_timeout          :      2;
  1138.                 bdrkreg_t       lec_rsrvd                 :     50;
  1139. } xb_loq_error_clear_fld_s;
  1140. } xb_loq_error_clear_u_t;
  1142. #else
  1144. typedef union xb_loq_error_clear_u {
  1145. bdrkreg_t xb_loq_error_clear_regval;
  1146. struct {
  1147. bdrkreg_t lec_rsrvd   : 50;
  1148. bdrkreg_t lec_tail_timeout   :  2;
  1149. bdrkreg_t lec_rsvd   :  2;
  1150. bdrkreg_t lec_underflow   :  2;
  1151. bdrkreg_t lec_rsrvd_1   :  6;
  1152. bdrkreg_t lec_invalid_xsel   :  2;
  1153. } xb_loq_error_clear_fld_s;
  1154. } xb_loq_error_clear_u_t;
  1156. #endif
  1161. /************************************************************************
  1162.  *                                                                      *
  1163.  *  Records errors seen by LIQ. Note that the LIQ only records errors   *
  1164.  * for the request channel. The reply channel can never deadlock or     *
  1165.  * overflow because it does not have hardware flow control.             *
  1166.  *                                                                      *
  1167.  ************************************************************************/
  1172. #ifdef LITTLE_ENDIAN
  1174. typedef union xb_liq_error_clear_u {
  1175. bdrkreg_t xb_liq_error_clear_regval;
  1176. struct  {
  1177. bdrkreg_t lec_overflow              :  1;
  1178.                 bdrkreg_t       lec_rsrvd_1               :      3;
  1179.                 bdrkreg_t       lec_deadlock_timeout      :      1;
  1180.                 bdrkreg_t       lec_rsrvd                 :     59;
  1181. } xb_liq_error_clear_fld_s;
  1182. } xb_liq_error_clear_u_t;
  1184. #else
  1186. typedef union xb_liq_error_clear_u {
  1187.         bdrkreg_t       xb_liq_error_clear_regval;
  1188.         struct  {
  1189.                 bdrkreg_t       lec_rsrvd                 :     59;
  1190.                 bdrkreg_t       lec_deadlock_timeout      :      1;
  1191.                 bdrkreg_t       lec_rsrvd_1               :      3;
  1192.                 bdrkreg_t       lec_overflow              :      1;
  1193.         } xb_liq_error_clear_fld_s;
  1194. } xb_liq_error_clear_u_t;
  1196. #endif
  1201. /************************************************************************
  1202.  *                                                                      *
  1203.  *  First error is latched whenever the Valid bit is clear and an       *
  1204.  * error occurs. Any valid bit on in this register causes an            *
  1205.  * interrupt to PI0 and PI1. This interrupt bit will persist until      *
  1206.  * the specific error register to capture the error is cleared, then    *
  1207.  * the FIRST_ERROR register is cleared (in that oder.) The              *
  1208.  * FIRST_ERROR register is not writable, but will be set when any of    *
  1209.  * the corresponding error registers are written by software.           *
  1210.  *                                                                      *
  1211.  ************************************************************************/
  1216. #ifdef LITTLE_ENDIAN
  1218. typedef union xb_first_error_clear_u {
  1219. bdrkreg_t xb_first_error_clear_regval;
  1220. struct  {
  1221. bdrkreg_t fec_type                  :  4;
  1222.                 bdrkreg_t       fec_channel               :      4;
  1223.                 bdrkreg_t       fec_source                :      4;
  1224.                 bdrkreg_t       fec_valid                 :      1;
  1225.                 bdrkreg_t       fec_rsrvd                 :     51;
  1226. } xb_first_error_clear_fld_s;
  1227. } xb_first_error_clear_u_t;
  1229. #else
  1231. typedef union xb_first_error_clear_u {
  1232. bdrkreg_t xb_first_error_clear_regval;
  1233. struct {
  1234. bdrkreg_t fec_rsrvd   : 51;
  1235. bdrkreg_t fec_valid   :  1;
  1236. bdrkreg_t fec_source   :  4;
  1237. bdrkreg_t fec_channel   :  4;
  1238. bdrkreg_t fec_type   :  4;
  1239. } xb_first_error_clear_fld_s;
  1240. } xb_first_error_clear_u_t;
  1242. #endif
  1249. #endif /* __ASSEMBLY__ */
  1251. /************************************************************************
  1252.  *                                                                      *
  1253.  * The following defines were not formed into structures                *
  1254.  *                                                                      *
  1255.  * This could be because the document did not contain details of the    *
  1256.  * register, or because the automated script did not recognize the      *
  1257.  * register details in the documentation. If these register need        *
  1258.  * structure definition, please create them manually                    *
  1259.  *                                                                      *
  1260.  *           XB_POQ1_ERROR            0x700030                          *
  1261.  *           XB_PIQ1_ERROR            0x700038                          *
  1262.  *           XB_MP1_ERROR             0x700048                          *
  1263.  *           XB_MMQ_ERROR             0x700050                          *
  1264.  *           XB_NIQ_ERROR             0x700068                          *
  1265.  *           XB_IOQ_ERROR             0x700070                          *
  1266.  *           XB_IIQ_ERROR             0x700078                          *
  1267.  *           XB_POQ1_ERROR_CLEAR      0x700130                          *
  1268.  *           XB_PIQ1_ERROR_CLEAR      0x700138                          *
  1269.  *           XB_MP1_ERROR_CLEAR       0x700148                          *
  1270.  *           XB_MMQ_ERROR_CLEAR       0x700150                          *
  1271.  *           XB_NIQ_ERROR_CLEAR       0x700168                          *
  1272.  *           XB_IOQ_ERROR_CLEAR       0x700170                          *
  1273.  *           XB_IIQ_ERROR_CLEAR       0x700178                          *
  1274.  *                                                                      *
  1275.  ************************************************************************/
  1278. /************************************************************************
  1279.  *                                                                      *
  1280.  *               MAKE ALL ADDITIONS AFTER THIS LINE                     *
  1281.  *                                                                      *
  1282.  ************************************************************************/
  1288. #endif /* _ASM_IA64_SN_SN1_HUBXB_H */