irq.c
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上传日期:2013-04-10
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Linux/Unix编程

开发平台:

Unix_Linux

  1. /*
  2.  * FILE NAME
  3.  * arch/mips/vr41xx/nec-eagle/irq.c
  4.  *
  5.  * BRIEF MODULE DESCRIPTION
  6.  * Interrupt routines for the NEC Eagle/Hawk board.
  7.  *
  8.  * Author: Yoichi Yuasa
  9.  *         yyuasa@mvista.com or source@mvista.com
  10.  *
  11.  * Copyright 2002 MontaVista Software Inc.
  12.  *
  13.  *  This program is free software; you can redistribute it and/or modify it
  14.  *  under the terms of the GNU General Public License as published by the
  15.  *  Free Software Foundation; either version 2 of the License, or (at your
  16.  *  option) any later version.
  17.  *
  18.  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19.  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20.  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  21.  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22.  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  23.  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  24.  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  25.  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  26.  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  27.  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28.  *
  29.  *  You should have received a copy of the GNU General Public License along
  30.  *  with this program; if not, write to the Free Software Foundation, Inc.,
  31.  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32.  */
  33. /*
  34.  * Changes:
  35.  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  36.  *  - Added support for NEC Hawk.
  37.  *
  38.  *  MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
  39.  *  - New creation, NEC Eagle is supported.
  40.  */
  41. #include <linux/init.h>
  42. #include <linux/interrupt.h>
  43. #include <asm/io.h>
  44. #include <asm/vr41xx/eagle.h>
  45. static void enable_pciint_irq(unsigned int irq)
  46. {
  47. u8 val;
  48. val = readb(NEC_EAGLE_PCIINTMSKREG);
  49. val |= (u8)1 << (irq - PCIINT_IRQ_BASE);
  50. writeb(val, NEC_EAGLE_PCIINTMSKREG);
  51. }
  52. static void disable_pciint_irq(unsigned int irq)
  53. {
  54. u8 val;
  55. val = readb(NEC_EAGLE_PCIINTMSKREG);
  56. val &= ~((u8)1 << (irq - PCIINT_IRQ_BASE));
  57. writeb(val, NEC_EAGLE_PCIINTMSKREG);
  58. }
  59. static unsigned int startup_pciint_irq(unsigned int irq)
  60. {
  61. enable_pciint_irq(irq);
  62. return 0; /* never anything pending */
  63. }
  64. #define shutdown_pciint_irq disable_pciint_irq
  65. #define ack_pciint_irq disable_pciint_irq
  66. static void end_pciint_irq(unsigned int irq)
  67. {
  68. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  69. enable_pciint_irq(irq);
  70. }
  71. static struct hw_interrupt_type pciint_irq_type = {
  72. "PCIINT",
  73. startup_pciint_irq,
  74. shutdown_pciint_irq,
  75.         enable_pciint_irq,
  76. disable_pciint_irq,
  77. ack_pciint_irq,
  78. end_pciint_irq,
  79. NULL
  80. };
  81. static void enable_sdbint_irq(unsigned int irq)
  82. {
  83. u8 val;
  84. val = readb(NEC_EAGLE_SDBINTMSK);
  85. val |= (u8)1 << (irq - SDBINT_IRQ_BASE);
  86. writeb(val, NEC_EAGLE_SDBINTMSK);
  87. }
  88. static void disable_sdbint_irq(unsigned int irq)
  89. {
  90. u8 val;
  91. val = readb(NEC_EAGLE_SDBINTMSK);
  92. val &= ~((u8)1 << (irq - SDBINT_IRQ_BASE));
  93. writeb(val, NEC_EAGLE_SDBINTMSK);
  94. }
  95. static unsigned int startup_sdbint_irq(unsigned int irq)
  96. {
  97. enable_sdbint_irq(irq);
  98. return 0; /* never anything pending */
  99. }
  100. #define shutdown_sdbint_irq disable_sdbint_irq
  101. #define ack_sdbint_irq disable_sdbint_irq
  102. static void end_sdbint_irq(unsigned int irq)
  103. {
  104. if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
  105. enable_sdbint_irq(irq);
  106. }
  107. static struct hw_interrupt_type sdbint_irq_type = {
  108. "SDBINT",
  109. startup_sdbint_irq,
  110. shutdown_sdbint_irq,
  111.         enable_sdbint_irq,
  112. disable_sdbint_irq,
  113. ack_sdbint_irq,
  114. end_sdbint_irq,
  115. NULL
  116. };
  117. static int eagle_get_irq_number(int irq)
  118. {
  119. u8 sdbint, pciint;
  120. int i;
  121. sdbint = readb(NEC_EAGLE_SDBINT);
  122. sdbint &= (NEC_EAGLE_SDBINT_DEG | NEC_EAGLE_SDBINT_ENUM |
  123.            NEC_EAGLE_SDBINT_SIO1INT | NEC_EAGLE_SDBINT_SIO2INT |
  124.            NEC_EAGLE_SDBINT_PARINT);
  125. pciint = readb(NEC_EAGLE_PCIINTREG);
  126. pciint &= (NEC_EAGLE_PCIINT_CP_INTA | NEC_EAGLE_PCIINT_CP_INTB |
  127.            NEC_EAGLE_PCIINT_CP_INTC | NEC_EAGLE_PCIINT_CP_INTD |
  128.            NEC_EAGLE_PCIINT_LANINT);
  129. for (i = 1; i < 6; i++)
  130. if (sdbint & (0x01 << i))
  131. return SDBINT_IRQ_BASE + i;
  132. for (i = 0; i < 5; i++)
  133. if (pciint & (0x01 << i))
  134. return PCIINT_IRQ_BASE + i;
  135. return -EINVAL;
  136. }
  137. void __init eagle_irq_init(void)
  138. {
  139. int i;
  140. writeb(0, NEC_EAGLE_SDBINTMSK);
  141. writeb(0, NEC_EAGLE_PCIINTMSKREG);
  142. vr41xx_set_irq_trigger(VRC4173_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
  143. vr41xx_set_irq_level(VRC4173_PIN, LEVEL_LOW);
  144. vr41xx_set_irq_trigger(PCISLOT_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
  145. vr41xx_set_irq_level(PCISLOT_PIN, LEVEL_HIGH);
  146. vr41xx_set_irq_trigger(FPGA_PIN, TRIGGER_LEVEL, SIGNAL_THROUGH);
  147. vr41xx_set_irq_level(FPGA_PIN, LEVEL_HIGH);
  148. vr41xx_set_irq_trigger(DCD_PIN, TRIGGER_EDGE, SIGNAL_HOLD);
  149. vr41xx_set_irq_level(DCD_PIN, LEVEL_LOW);
  150. for (i = SDBINT_IRQ_BASE; i <= SDBINT_IRQ_LAST; i++)
  151. irq_desc[i].handler = &sdbint_irq_type;
  152. for (i = PCIINT_IRQ_BASE; i <= PCIINT_IRQ_LAST; i++)
  153. irq_desc[i].handler = &pciint_irq_type;
  154. vr41xx_cascade_irq(FPGA_CASCADE_IRQ, eagle_get_irq_number);
  155. }