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FlashPoint.c：源码内容

/*
FlashPoint.c -- FlashPoint SCCB Manager for Linux
This file contains the FlashPoint SCCB Manager from BusLogic's FlashPoint
Driver Developer's Kit, with minor modifications by Leonard N. Zubkoff for
Linux compatibility. It was provided by BusLogic in the form of 16 separate
source files, which would have unnecessarily cluttered the scsi directory, so
the individual files have been combined into this single file.
This file is available under both the GNU General Public License
and a BSD-style copyright; see LICENSE.FlashPoint for details.
*/
#include <linux/config.h>
#ifndef CONFIG_SCSI_OMIT_FLASHPOINT
#define UNIX
#define FW_TYPE _SCCB_MGR_
#define MAX_CARDS 8
#undef BUSTYPE_PCI
#define OS_InPortByte(port) inb(port)
#define OS_InPortWord(port) inw(port)
#define OS_InPortLong(port) inl(port)
#define OS_OutPortByte(port, value) outb(value, port)
#define OS_OutPortWord(port, value) outw(value, port)
#define OS_OutPortLong(port, value) outl(value, port)
#define OS_Lock(x)
#define OS_UnLock(x)
/*
Define name replacements for compatibility with the Linux BusLogic Driver.
*/
#define SccbMgr_sense_adapter FlashPoint_ProbeHostAdapter
#define SccbMgr_config_adapter FlashPoint_HardwareResetHostAdapter
#define SccbMgr_unload_card FlashPoint_ReleaseHostAdapter
#define SccbMgr_start_sccb FlashPoint_StartCCB
#define SccbMgr_abort_sccb FlashPoint_AbortCCB
#define SccbMgr_my_int FlashPoint_InterruptPending
#define SccbMgr_isr FlashPoint_HandleInterrupt
/*
Define name replacements to avoid kernel namespace pollution.
*/
#define BL_Card FPT_BL_Card
#define BusMasterInit FPT_BusMasterInit
#define CalcCrc16 FPT_CalcCrc16
#define CalcLrc FPT_CalcLrc
#define ChkIfChipInitialized FPT_ChkIfChipInitialized
#define DiagBusMaster FPT_DiagBusMaster
#define DiagEEPROM FPT_DiagEEPROM
#define DiagXbow FPT_DiagXbow
#define GetTarLun FPT_GetTarLun
#define RNVRamData FPT_RNVRamData
#define RdStack FPT_RdStack
#define SccbMgrTableInitAll FPT_SccbMgrTableInitAll
#define SccbMgrTableInitCard FPT_SccbMgrTableInitCard
#define SccbMgrTableInitTarget FPT_SccbMgrTableInitTarget
#define SccbMgr_bad_isr FPT_SccbMgr_bad_isr
#define SccbMgr_scsi_reset FPT_SccbMgr_scsi_reset
#define SccbMgr_timer_expired FPT_SccbMgr_timer_expired
#define SendMsg FPT_SendMsg
#define Wait FPT_Wait
#define Wait1Second FPT_Wait1Second
#define WrStack FPT_WrStack
#define XbowInit FPT_XbowInit
#define autoCmdCmplt FPT_autoCmdCmplt
#define autoLoadDefaultMap FPT_autoLoadDefaultMap
#define busMstrDataXferStart FPT_busMstrDataXferStart
#define busMstrSGDataXferStart FPT_busMstrSGDataXferStart
#define busMstrTimeOut FPT_busMstrTimeOut
#define dataXferProcessor FPT_dataXferProcessor
#define default_intena FPT_default_intena
#define hostDataXferAbort FPT_hostDataXferAbort
#define hostDataXferRestart FPT_hostDataXferRestart
#define inisci FPT_inisci
#define mbCards FPT_mbCards
#define nvRamInfo FPT_nvRamInfo
#define phaseBusFree FPT_phaseBusFree
#define phaseChkFifo FPT_phaseChkFifo
#define phaseCommand FPT_phaseCommand
#define phaseDataIn FPT_phaseDataIn
#define phaseDataOut FPT_phaseDataOut
#define phaseDecode FPT_phaseDecode
#define phaseIllegal FPT_phaseIllegal
#define phaseMsgIn FPT_phaseMsgIn
#define phaseMsgOut FPT_phaseMsgOut
#define phaseStatus FPT_phaseStatus
#define queueAddSccb FPT_queueAddSccb
#define queueCmdComplete FPT_queueCmdComplete
#define queueDisconnect FPT_queueDisconnect
#define queueFindSccb FPT_queueFindSccb
#define queueFlushSccb FPT_queueFlushSccb
#define queueFlushTargSccb FPT_queueFlushTargSccb
#define queueSearchSelect FPT_queueSearchSelect
#define queueSelectFail FPT_queueSelectFail
#define s_PhaseTbl FPT_s_PhaseTbl
#define scamHAString FPT_scamHAString
#define scamInfo FPT_scamInfo
#define scarb FPT_scarb
#define scasid FPT_scasid
#define scbusf FPT_scbusf
#define sccbMgrTbl FPT_sccbMgrTbl
#define schkdd FPT_schkdd
#define scini FPT_scini
#define sciso FPT_sciso
#define scmachid FPT_scmachid
#define scsavdi FPT_scsavdi
#define scsel FPT_scsel
#define scsell FPT_scsell
#define scsendi FPT_scsendi
#define scvalq FPT_scvalq
#define scwirod FPT_scwirod
#define scwiros FPT_scwiros
#define scwtsel FPT_scwtsel
#define scxferc FPT_scxferc
#define sdecm FPT_sdecm
#define sfm FPT_sfm
#define shandem FPT_shandem
#define sinits FPT_sinits
#define sisyncn FPT_sisyncn
#define sisyncr FPT_sisyncr
#define siwidn FPT_siwidn
#define siwidr FPT_siwidr
#define sres FPT_sres
#define sresb FPT_sresb
#define ssel FPT_ssel
#define ssenss FPT_ssenss
#define sssyncv FPT_sssyncv
#define stsyncn FPT_stsyncn
#define stwidn FPT_stwidn
#define sxfrp FPT_sxfrp
#define utilEERead FPT_utilEERead
#define utilEEReadOrg FPT_utilEEReadOrg
#define utilEESendCmdAddr FPT_utilEESendCmdAddr
#define utilEEWrite FPT_utilEEWrite
#define utilEEWriteOnOff FPT_utilEEWriteOnOff
#define utilUpdateResidual FPT_utilUpdateResidual
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: globals.h $
*
* Description: Common shared global defines.
*
* $Date: 1996/09/04 01:26:13 $
*
* $Revision: 1.11 $
*
*----------------------------------------------------------------------*/
#ifndef __GLOBALS_H__
#define __GLOBALS_H__
#define _UCB_MGR_ 1
#define _SCCB_MGR_ 2
/*#include <osflags.h>*/
#define MAX_CDBLEN 12
#define SCAM_LEV_2 1
#define CRCMASK 0xA001
/* In your osflags.h file, please ENSURE that only ONE OS FLAG
is on at a time !!! Also, please make sure you turn set the
variable FW_TYPE to either _UCB_MGR_ or _SCCB_MGR_ !!! */
#if defined(DOS) || defined(WIN95_16) || defined(OS2) || defined(OTHER_16)
#define COMPILER_16_BIT 1
#elif defined(NETWARE) || defined(NT) || defined(WIN95_32) || defined(UNIX) || defined(OTHER_32) || defined(SOLARIS_REAL_MODE)
#define COMPILER_32_BIT 1
#endif
#define BL_VENDOR_ID 0x104B
#define FP_DEVICE_ID 0x8130
#define MM_DEVICE_ID 0x1040
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!(FALSE))
#endif
#ifndef NULL
#define NULL 0
#endif
#define FAILURE 0xFFFFFFFFL
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned int UINT;
typedef unsigned long ULONG;
typedef unsigned char * PUCHAR;
typedef unsigned short* PUSHORT;
typedef unsigned long * PULONG;
typedef void * PVOID;
#if defined(COMPILER_16_BIT)
typedef unsigned char far * uchar_ptr;
typedef unsigned short far * ushort_ptr;
typedef unsigned long far * ulong_ptr;
#endif /* 16_BIT_COMPILER */
#if defined(COMPILER_32_BIT)
typedef unsigned char * uchar_ptr;
typedef unsigned short * ushort_ptr;
typedef unsigned long * ulong_ptr;
#endif /* 32_BIT_COMPILER */
/* NEW TYPE DEFINITIONS (shared with Mylex North)
** Use following type defines to avoid confusion in 16 and 32-bit
** environments. Avoid using 'int' as it denotes 16 bits in 16-bit
** environment and 32 in 32-bit environments.
*/
#define s08bits char
#define s16bits short
#define s32bits long
#define u08bits unsigned s08bits
#define u16bits unsigned s16bits
#define u32bits unsigned s32bits
#if defined(COMPILER_16_BIT)
typedef u08bits far * pu08bits;
typedef u16bits far * pu16bits;
typedef u32bits far * pu32bits;
#endif /* COMPILER_16_BIT */
#if defined(COMPILER_32_BIT)
typedef u08bits * pu08bits;
typedef u16bits * pu16bits;
typedef u32bits * pu32bits;
#endif /* COMPILER_32_BIT */
#define BIT(x) ((UCHAR)(1<<(x))) /* single-bit mask in bit position x */
#define BITW(x) ((USHORT)(1<<(x))) /* single-bit mask in bit position x */
#if defined(DOS)
/*#include <dos.h>*/
#undef inportb /* undefine for Borland Lib */
#undef inport /* they may have define I/O function in LIB */
#undef outportb
#undef outport
#define OS_InPortByte(ioport) inportb(ioport)
#define OS_InPortWord(ioport) inport(ioport)
#define OS_InPortLong(ioport) inportq(ioport, val)
#define OS_OutPortByte(ioport, val) outportb(ioport, val)
#define OS_OutPortWord(ioport, val) outport(ioport, val)
#define OS_OutPortLong(ioport) outportq(ioport, val)
#endif /* DOS */
#if defined(NETWARE) || defined(OTHER_32) || defined(OTHER_16)
extern u08bits OS_InPortByte(u32bits ioport);
extern u16bits OS_InPortWord(u32bits ioport);
extern u32bits OS_InPortLong(u32bits ioport);
extern OS_InPortByteBuffer(u32bits ioport, pu08bits buffer, u32bits count);
extern OS_InPortWordBuffer(u32bits ioport, pu16bits buffer, u32bits count);
extern OS_OutPortByte(u32bits ioport, u08bits val);
extern OS_OutPortWord(u32bits ioport, u16bits val);
extern OS_OutPortLong(u32bits ioport, u32bits val);
extern OS_OutPortByteBuffer(u32bits ioport, pu08bits buffer, u32bits count);
extern OS_OutPortWordBuffer(u32bits ioport, pu16bits buffer, u32bits count);
#endif /* NETWARE || OTHER_32 || OTHER_16 */
#if defined (NT) || defined(WIN95_32) || defined(WIN95_16)
#if defined(NT)
extern __declspec(dllimport) u08bits ScsiPortReadPortUchar(pu08bits ioport);
extern __declspec(dllimport) u16bits ScsiPortReadPortUshort(pu16bits ioport);
extern __declspec(dllimport) u32bits ScsiPortReadPortUlong(pu32bits ioport);
extern __declspec(dllimport) void ScsiPortWritePortUchar(pu08bits ioport, u08bits val);
extern __declspec(dllimport) void ScsiPortWritePortUshort(pu16bits port, u16bits val);
extern __declspec(dllimport) void ScsiPortWritePortUlong(pu32bits port, u32bits val);
#else
extern u08bits ScsiPortReadPortUchar(pu08bits ioport);
extern u16bits ScsiPortReadPortUshort(pu16bits ioport);
extern u32bits ScsiPortReadPortUlong(pu32bits ioport);
extern void ScsiPortWritePortUchar(pu08bits ioport, u08bits val);
extern void ScsiPortWritePortUshort(pu16bits port, u16bits val);
extern void ScsiPortWritePortUlong(pu32bits port, u32bits val);
#endif
#define OS_InPortByte(ioport) ScsiPortReadPortUchar((pu08bits) ioport)
#define OS_InPortWord(ioport) ScsiPortReadPortUshort((pu16bits) ioport)
#define OS_InPortLong(ioport) ScsiPortReadPortUlong((pu32bits) ioport)
#define OS_OutPortByte(ioport, val) ScsiPortWritePortUchar((pu08bits) ioport, (u08bits) val)
#define OS_OutPortWord(ioport, val) ScsiPortWritePortUshort((pu16bits) ioport, (u16bits) val)
#define OS_OutPortLong(ioport, val) ScsiPortWritePortUlong((pu32bits) ioport, (u32bits) val)
#define OS_OutPortByteBuffer(ioport, buffer, count)
ScsiPortWritePortBufferUchar((pu08bits)&port, (pu08bits) buffer, (u32bits) count)
#define OS_OutPortWordBuffer(ioport, buffer, count)
ScsiPortWritePortBufferUshort((pu16bits)&port, (pu16bits) buffer, (u32bits) count)
#define OS_Lock(x)
#define OS_UnLock(x)
#endif /* NT || WIN95_32 || WIN95_16 */
#if defined (UNIX) && !defined(OS_InPortByte)
#define OS_InPortByte(ioport) inb((u16bits)ioport)
#define OS_InPortWord(ioport) inw((u16bits)ioport)
#define OS_InPortLong(ioport) inl((u16bits)ioport)
#define OS_OutPortByte(ioport,val) outb((u16bits)ioport, (u08bits)val)
#define OS_OutPortWord(ioport,val) outw((u16bits)ioport, (u16bits)val)
#define OS_OutPortLong(ioport,val) outl((u16bits)ioport, (u32bits)val)
#define OS_Lock(x)
#define OS_UnLock(x)
#endif /* UNIX */
#if defined(OS2)
extern u08bits inb(u32bits ioport);
extern u16bits inw(u32bits ioport);
extern void outb(u32bits ioport, u08bits val);
extern void outw(u32bits ioport, u16bits val);
#define OS_InPortByte(ioport) inb(ioport)
#define OS_InPortWord(ioport) inw(ioport)
#define OS_OutPortByte(ioport, val) outb(ioport, val)
#define OS_OutPortWord(ioport, val) outw(ioport, val)
extern u32bits OS_InPortLong(u32bits ioport);
extern void OS_OutPortLong(u32bits ioport, u32bits val);
#define OS_Lock(x)
#define OS_UnLock(x)
#endif /* OS2 */
#if defined(SOLARIS_REAL_MODE)
extern unsigned char inb(unsigned long ioport);
extern unsigned short inw(unsigned long ioport);
#define OS_InPortByte(ioport) inb(ioport)
#define OS_InPortWord(ioport) inw(ioport)
extern void OS_OutPortByte(unsigned long ioport, unsigned char val);
extern void OS_OutPortWord(unsigned long ioport, unsigned short val);
extern unsigned long OS_InPortLong(unsigned long ioport);
extern void OS_OutPortLong(unsigned long ioport, unsigned long val);
#define OS_Lock(x)
#define OS_UnLock(x)
#endif /* SOLARIS_REAL_MODE */
#endif /* __GLOBALS_H__ */
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: sccbmgr.h $
*
* Description: Common shared SCCB Interface defines and SCCB
* Manager specifics defines.
*
* $Date: 1996/10/24 23:09:33 $
*
* $Revision: 1.14 $
*
*----------------------------------------------------------------------*/
#ifndef __SCCB_H__
#define __SCCB_H__
/*#include <osflags.h>*/
/*#include <globals.h>*/
#if defined(BUGBUG)
#define debug_size 32
#endif
#if defined(DOS)
typedef struct _SCCB near *PSCCB;
#if (FW_TYPE == _SCCB_MGR_)
typedef void (*CALL_BK_FN)(PSCCB);
#endif
#elif defined(OS2)
typedef struct _SCCB far *PSCCB;
#if (FW_TYPE == _SCCB_MGR_)
typedef void (far *CALL_BK_FN)(PSCCB);
#endif
#else
typedef struct _SCCB *PSCCB;
#if (FW_TYPE == _SCCB_MGR_)
typedef void (*CALL_BK_FN)(PSCCB);
#endif
#endif
typedef struct SCCBMgr_info {
ULONG si_baseaddr;
UCHAR si_present;
UCHAR si_intvect;
UCHAR si_id;
UCHAR si_lun;
USHORT si_fw_revision;
USHORT si_per_targ_init_sync;
USHORT si_per_targ_fast_nego;
USHORT si_per_targ_ultra_nego;
USHORT si_per_targ_no_disc;
USHORT si_per_targ_wide_nego;
USHORT si_flags;
UCHAR si_card_family;
UCHAR si_bustype;
UCHAR si_card_model[3];
UCHAR si_relative_cardnum;
UCHAR si_reserved[4];
ULONG si_OS_reserved;
UCHAR si_XlatInfo[4];
ULONG si_reserved2[5];
ULONG si_secondary_range;
} SCCBMGR_INFO;
#if defined(DOS)
typedef SCCBMGR_INFO * PSCCBMGR_INFO;
#else
#if defined (COMPILER_16_BIT)
typedef SCCBMGR_INFO far * PSCCBMGR_INFO;
#else
typedef SCCBMGR_INFO * PSCCBMGR_INFO;
#endif
#endif // defined(DOS)
#if (FW_TYPE==_SCCB_MGR_)
#define SCSI_PARITY_ENA 0x0001
#define LOW_BYTE_TERM 0x0010
#define HIGH_BYTE_TERM 0x0020
#define BUSTYPE_PCI 0x3
#endif
#define SUPPORT_16TAR_32LUN 0x0002
#define SOFT_RESET 0x0004
#define EXTENDED_TRANSLATION 0x0008
#define POST_ALL_UNDERRRUNS 0x0040
#define FLAG_SCAM_ENABLED 0x0080
#define FLAG_SCAM_LEVEL2 0x0100
#define HARPOON_FAMILY 0x02
#define ISA_BUS_CARD 0x01
#define EISA_BUS_CARD 0x02
#define PCI_BUS_CARD 0x03
#define VESA_BUS_CARD 0x04
/* SCCB struc used for both SCCB and UCB manager compiles!
* The UCB Manager treats the SCCB as it's 'native hardware structure'
*/
#pragma pack(1)
typedef struct _SCCB {
UCHAR OperationCode;
UCHAR ControlByte;
UCHAR CdbLength;
UCHAR RequestSenseLength;
ULONG DataLength;
ULONG DataPointer;
UCHAR CcbRes[2];
UCHAR HostStatus;
UCHAR TargetStatus;
UCHAR TargID;
UCHAR Lun;
UCHAR Cdb[12];
UCHAR CcbRes1;
UCHAR Reserved1;
ULONG Reserved2;
ULONG SensePointer;
CALL_BK_FN SccbCallback; /* VOID (*SccbCallback)(); */
ULONG SccbIOPort; /* Identifies board base port */
UCHAR SccbStatus;
UCHAR SCCBRes2;
USHORT SccbOSFlags;
ULONG Sccb_XferCnt; /* actual transfer count */
ULONG Sccb_ATC;
ULONG SccbVirtDataPtr; /* virtual addr for OS/2 */
ULONG Sccb_res1;
USHORT Sccb_MGRFlags;
USHORT Sccb_sgseg;
UCHAR Sccb_scsimsg; /* identify msg for selection */
UCHAR Sccb_tag;
UCHAR Sccb_scsistat;
UCHAR Sccb_idmsg; /* image of last msg in */
PSCCB Sccb_forwardlink;
PSCCB Sccb_backlink;
ULONG Sccb_savedATC;
UCHAR Save_Cdb[6];
UCHAR Save_CdbLen;
UCHAR Sccb_XferState;
ULONG Sccb_SGoffset;
#if (FW_TYPE == _UCB_MGR_)
PUCB Sccb_ucb_ptr;
#endif
} SCCB;
#define SCCB_SIZE sizeof(SCCB)
#pragma pack()
#define SCSI_INITIATOR_COMMAND 0x00
#define TARGET_MODE_COMMAND 0x01
#define SCATTER_GATHER_COMMAND 0x02
#define RESIDUAL_COMMAND 0x03
#define RESIDUAL_SG_COMMAND 0x04
#define RESET_COMMAND 0x81
#define F_USE_CMD_Q 0x20 /*Inidcates TAGGED command. */
#define TAG_TYPE_MASK 0xC0 /*Type of tag msg to send. */
#define TAG_Q_MASK 0xE0
#define SCCB_DATA_XFER_OUT 0x10 /* Write */
#define SCCB_DATA_XFER_IN 0x08 /* Read */
#define FOURTEEN_BYTES 0x00 /* Request Sense Buffer size */
#define NO_AUTO_REQUEST_SENSE 0x01 /* No Request Sense Buffer */
#define BUS_FREE_ST 0
#define SELECT_ST 1
#define SELECT_BDR_ST 2 /* Select w Bus Device Reset */
#define SELECT_SN_ST 3 /* Select w Sync Nego */
#define SELECT_WN_ST 4 /* Select w Wide Data Nego */
#define SELECT_Q_ST 5 /* Select w Tagged Q'ing */
#define COMMAND_ST 6
#define DATA_OUT_ST 7
#define DATA_IN_ST 8
#define DISCONNECT_ST 9
#define STATUS_ST 10
#define ABORT_ST 11
#define MESSAGE_ST 12
#define F_HOST_XFER_DIR 0x01
#define F_ALL_XFERRED 0x02
#define F_SG_XFER 0x04
#define F_AUTO_SENSE 0x08
#define F_ODD_BALL_CNT 0x10
#define F_NO_DATA_YET 0x80
#define F_STATUSLOADED 0x01
#define F_MSGLOADED 0x02
#define F_DEV_SELECTED 0x04
#define SCCB_COMPLETE 0x00 /* SCCB completed without error */
#define SCCB_DATA_UNDER_RUN 0x0C
#define SCCB_SELECTION_TIMEOUT 0x11 /* Set SCSI selection timed out */
#define SCCB_DATA_OVER_RUN 0x12
#define SCCB_UNEXPECTED_BUS_FREE 0x13 /* Target dropped SCSI BSY */
#define SCCB_PHASE_SEQUENCE_FAIL 0x14 /* Target bus phase sequence failure */
#define SCCB_INVALID_OP_CODE 0x16 /* SCCB invalid operation code */
#define SCCB_INVALID_SCCB 0x1A /* Invalid SCCB - bad parameter */
#define SCCB_GROSS_FW_ERR 0x27 /* Major problem! */
#define SCCB_BM_ERR 0x30 /* BusMaster error. */
#define SCCB_PARITY_ERR 0x34 /* SCSI parity error */
#if (FW_TYPE==_UCB_MGR_)
#define HBA_AUTO_SENSE_FAIL 0x1B
#define HBA_TQ_REJECTED 0x1C
#define HBA_UNSUPPORTED_MSG 0x1D
#define HBA_HW_ERROR 0x20
#define HBA_ATN_NOT_RESPONDED 0x21
#define HBA_SCSI_RESET_BY_ADAPTER 0x22
#define HBA_SCSI_RESET_BY_TARGET 0x23
#define HBA_WRONG_CONNECTION 0x24
#define HBA_BUS_DEVICE_RESET 0x25
#define HBA_ABORT_QUEUE 0x26
#else // these are not defined in BUDI/UCB
#define SCCB_INVALID_DIRECTION 0x18 /* Invalid target direction */
#define SCCB_DUPLICATE_SCCB 0x19 /* Duplicate SCCB */
#define SCCB_SCSI_RST 0x35 /* SCSI RESET detected. */
#endif // (FW_TYPE==_UCB_MGR_)
#define SCCB_IN_PROCESS 0x00
#define SCCB_SUCCESS 0x01
#define SCCB_ABORT 0x02
#define SCCB_NOT_FOUND 0x03
#define SCCB_ERROR 0x04
#define SCCB_INVALID 0x05
#define SCCB_SIZE sizeof(SCCB)
#if (FW_TYPE == _UCB_MGR_)
void SccbMgr_start_sccb(CARD_HANDLE pCurrCard, PUCB p_ucb);
s32bits SccbMgr_abort_sccb(CARD_HANDLE pCurrCard, PUCB p_ucb);
u08bits SccbMgr_my_int(CARD_HANDLE pCurrCard);
s32bits SccbMgr_isr(CARD_HANDLE pCurrCard);
void SccbMgr_scsi_reset(CARD_HANDLE pCurrCard);
void SccbMgr_timer_expired(CARD_HANDLE pCurrCard);
void SccbMgr_unload_card(CARD_HANDLE pCurrCard);
void SccbMgr_restore_foreign_state(CARD_HANDLE pCurrCard);
void SccbMgr_restore_native_state(CARD_HANDLE pCurrCard);
void SccbMgr_save_foreign_state(PADAPTER_INFO pAdapterInfo);
#endif
#if (FW_TYPE == _SCCB_MGR_)
#if defined (DOS)
int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo);
USHORT SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo);
void SccbMgr_start_sccb(USHORT pCurrCard, PSCCB p_SCCB);
int SccbMgr_abort_sccb(USHORT pCurrCard, PSCCB p_SCCB);
UCHAR SccbMgr_my_int(USHORT pCurrCard);
int SccbMgr_isr(USHORT pCurrCard);
void SccbMgr_scsi_reset(USHORT pCurrCard);
void SccbMgr_timer_expired(USHORT pCurrCard);
USHORT SccbMgr_status(USHORT pCurrCard);
void SccbMgr_unload_card(USHORT pCurrCard);
#else //non-DOS
int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo);
ULONG SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo);
void SccbMgr_start_sccb(ULONG pCurrCard, PSCCB p_SCCB);
int SccbMgr_abort_sccb(ULONG pCurrCard, PSCCB p_SCCB);
UCHAR SccbMgr_my_int(ULONG pCurrCard);
int SccbMgr_isr(ULONG pCurrCard);
void SccbMgr_scsi_reset(ULONG pCurrCard);
void SccbMgr_enable_int(ULONG pCurrCard);
void SccbMgr_disable_int(ULONG pCurrCard);
void SccbMgr_timer_expired(ULONG pCurrCard);
void SccbMgr_unload_card(ULONG pCurrCard);
#endif
#endif // (FW_TYPE == _SCCB_MGR_)
#endif /* __SCCB_H__ */
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: blx30.h $
*
* Description: This module contains SCCB/UCB Manager implementation
* specific stuff.
*
* $Date: 1996/11/13 18:34:22 $
*
* $Revision: 1.10 $
*
*----------------------------------------------------------------------*/
#ifndef __blx30_H__
#define __blx30_H__
/*#include <globals.h>*/
#define ORION_FW_REV 3110
#define HARP_REVD 1
#if defined(DOS)
#define QUEUE_DEPTH 8+1 /*1 for Normal disconnect 0 for Q'ing. */
#else
#define QUEUE_DEPTH 254+1 /*1 for Normal disconnect 32 for Q'ing. */
#endif // defined(DOS)
#define MAX_MB_CARDS 4 /* Max. no of cards suppoerted on Mother Board */
#define WIDE_SCSI 1
#if defined(WIDE_SCSI)
#if defined(DOS)
#define MAX_SCSI_TAR 16
#define MAX_LUN 8
#define LUN_MASK 0x07
#else
#define MAX_SCSI_TAR 16
#define MAX_LUN 32
#define LUN_MASK 0x1f
#endif
#else
#define MAX_SCSI_TAR 8
#define MAX_LUN 8
#define LUN_MASK 0x07
#endif
#if defined(HARP_REVA)
#define SG_BUF_CNT 15 /*Number of prefetched elements. */
#else
#define SG_BUF_CNT 16 /*Number of prefetched elements. */
#endif
#define SG_ELEMENT_SIZE 8 /*Eight byte per element. */
#define SG_LOCAL_MASK 0x00000000L
#define SG_ELEMENT_MASK 0xFFFFFFFFL
#if (FW_TYPE == _UCB_MGR_)
#define OPC_DECODE_NORMAL 0x0f7f
#endif // _UCB_MGR_
#if defined(DOS)
/*#include <dos.h>*/
#define RD_HARPOON(ioport) (OS_InPortByte(ioport))
#define RDW_HARPOON(ioport) (OS_InPortWord(ioport))
#define WR_HARPOON(ioport,val) (OS_OutPortByte(ioport,val))
#define WRW_HARPOON(ioport,val) (OS_OutPortWord(ioport,val))
#define RD_HARP32(port,offset,data) asm{db 66h;
push ax;
mov dx,port;
add dx, offset;
db 66h;
in ax,dx;
db 66h;
mov word ptr data,ax;
db 66h;
pop ax}
#define WR_HARP32(port,offset,data) asm{db 66h;
push ax;
mov dx,port;
add dx, offset;
db 66h;
mov ax,word ptr data;
db 66h;
out dx,ax;
db 66h;
pop ax}
#endif /* DOS */
#if defined(NETWARE) || defined(OTHER_32) || defined(OTHER_16)
#define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
#define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong(ioport + offset))
#define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
#define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
#define WR_HARP32(ioport,offset,data) OS_OutPortLong((ioport + offset), data)
#endif /* NETWARE || OTHER_32 || OTHER_16 */
#if defined(NT) || defined(WIN95_32) || defined(WIN95_16)
#define RD_HARPOON(ioport) OS_InPortByte((ULONG)ioport)
#define RDW_HARPOON(ioport) OS_InPortWord((ULONG)ioport)
#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
#define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
#define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
#define WR_HARP32(ioport,offset,data) OS_OutPortLong((ULONG)(ioport + offset), data)
#endif /* NT || WIN95_32 || WIN95_16 */
#if defined (UNIX)
#define RD_HARPOON(ioport) OS_InPortByte((u32bits)ioport)
#define RDW_HARPOON(ioport) OS_InPortWord((u32bits)ioport)
#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((u32bits)(ioport + offset)))
#define WR_HARPOON(ioport,val) OS_OutPortByte((u32bits)ioport,(u08bits) val)
#define WRW_HARPOON(ioport,val) OS_OutPortWord((u32bits)ioport,(u16bits)val)
#define WR_HARP32(ioport,offset,data) OS_OutPortLong((u32bits)(ioport + offset), data)
#endif /* UNIX */
#if defined(OS2)
#define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
#define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
#define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
#define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
#define WR_HARP32(ioport,offset,data) OS_OutPortLong(((ULONG)(ioport + offset)), data)
#endif /* OS2 */
#if defined(SOLARIS_REAL_MODE)
#define RD_HARPOON(ioport) OS_InPortByte((unsigned long)ioport)
#define RDW_HARPOON(ioport) OS_InPortWord((unsigned long)ioport)
#define RD_HARP32(ioport,offset,data) (data = OS_InPortLong((ULONG)(ioport + offset)))
#define WR_HARPOON(ioport,val) OS_OutPortByte((ULONG)ioport,(UCHAR) val)
#define WRW_HARPOON(ioport,val) OS_OutPortWord((ULONG)ioport,(USHORT)val)
#define WR_HARP32(ioport,offset,data) OS_OutPortLong((ULONG)(ioport + offset), (ULONG)data)
#endif /* SOLARIS_REAL_MODE */
#endif /* __BLX30_H__ */
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: target.h $
*
* Description: Definitions for Target related structures
*
* $Date: 1996/12/11 22:06:20 $
*
* $Revision: 1.9 $
*
*----------------------------------------------------------------------*/
#ifndef __TARGET__
#define __TARGET__
/*#include <globals.h>*/
/*#include <blx30.h>*/
#define TAR_SYNC_MASK (BIT(7)+BIT(6))
#define SYNC_UNKNOWN 0x00
#define SYNC_TRYING BIT(6)
#define SYNC_SUPPORTED (BIT(7)+BIT(6))
#define TAR_WIDE_MASK (BIT(5)+BIT(4))
#define WIDE_DISABLED 0x00
#define WIDE_ENABLED BIT(4)
#define WIDE_NEGOCIATED BIT(5)
#define TAR_TAG_Q_MASK (BIT(3)+BIT(2))
#define TAG_Q_UNKNOWN 0x00
#define TAG_Q_TRYING BIT(2)
#define TAG_Q_REJECT BIT(3)
#define TAG_Q_SUPPORTED (BIT(3)+BIT(2))
#define TAR_ALLOW_DISC BIT(0)
#define EE_SYNC_MASK (BIT(0)+BIT(1))
#define EE_SYNC_ASYNC 0x00
#define EE_SYNC_5MB BIT(0)
#define EE_SYNC_10MB BIT(1)
#define EE_SYNC_20MB (BIT(0)+BIT(1))
#define EE_ALLOW_DISC BIT(6)
#define EE_WIDE_SCSI BIT(7)
#if defined(DOS)
typedef struct SCCBMgr_tar_info near *PSCCBMgr_tar_info;
#elif defined(OS2)
typedef struct SCCBMgr_tar_info far *PSCCBMgr_tar_info;
#else
typedef struct SCCBMgr_tar_info *PSCCBMgr_tar_info;
#endif
typedef struct SCCBMgr_tar_info {
PSCCB TarSelQ_Head;
PSCCB TarSelQ_Tail;
UCHAR TarLUN_CA; /*Contingent Allgiance */
UCHAR TarTagQ_Cnt;
UCHAR TarSelQ_Cnt;
UCHAR TarStatus;
UCHAR TarEEValue;
UCHAR TarSyncCtrl;
UCHAR TarReserved[2]; /* for alignment */
UCHAR LunDiscQ_Idx[MAX_LUN];
UCHAR TarLUNBusy[MAX_LUN];
} SCCBMGR_TAR_INFO;
typedef struct NVRAMInfo {
UCHAR niModel; /* Model No. of card */
UCHAR niCardNo; /* Card no. */
#if defined(DOS)
USHORT niBaseAddr; /* Port Address of card */
#else
ULONG niBaseAddr; /* Port Address of card */
#endif
UCHAR niSysConf; /* Adapter Configuration byte - Byte 16 of eeprom map */
UCHAR niScsiConf; /* SCSI Configuration byte - Byte 17 of eeprom map */
UCHAR niScamConf; /* SCAM Configuration byte - Byte 20 of eeprom map */
UCHAR niAdapId; /* Host Adapter ID - Byte 24 of eerpom map */
UCHAR niSyncTbl[MAX_SCSI_TAR / 2]; /* Sync/Wide byte of targets */
UCHAR niScamTbl[MAX_SCSI_TAR][4]; /* Compressed Scam name string of Targets */
}NVRAMINFO;
#if defined(DOS)
typedef NVRAMINFO near *PNVRamInfo;
#elif defined (OS2)
typedef NVRAMINFO far *PNVRamInfo;
#else
typedef NVRAMINFO *PNVRamInfo;
#endif
#define MODEL_LT 1
#define MODEL_DL 2
#define MODEL_LW 3
#define MODEL_DW 4
typedef struct SCCBcard {
PSCCB currentSCCB;
#if (FW_TYPE==_SCCB_MGR_)
PSCCBMGR_INFO cardInfo;
#else
PADAPTER_INFO cardInfo;
#endif
#if defined(DOS)
USHORT ioPort;
#else
ULONG ioPort;
#endif
USHORT cmdCounter;
UCHAR discQCount;
UCHAR tagQ_Lst;
UCHAR cardIndex;
UCHAR scanIndex;
UCHAR globalFlags;
UCHAR ourId;
PNVRamInfo pNvRamInfo;
PSCCB discQ_Tbl[QUEUE_DEPTH];
}SCCBCARD;
#if defined(DOS)
typedef struct SCCBcard near *PSCCBcard;
#elif defined (OS2)
typedef struct SCCBcard far *PSCCBcard;
#else
typedef struct SCCBcard *PSCCBcard;
#endif
#define F_TAG_STARTED 0x01
#define F_CONLUN_IO 0x02
#define F_DO_RENEGO 0x04
#define F_NO_FILTER 0x08
#define F_GREEN_PC 0x10
#define F_HOST_XFER_ACT 0x20
#define F_NEW_SCCB_CMD 0x40
#define F_UPDATE_EEPROM 0x80
#define ID_STRING_LENGTH 32
#define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
#define TYPE_CODE1 00 /*No ID yet */
#define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
#define ASSIGN_ID 0x00
#define SET_P_FLAG 0x01
#define CFG_CMPLT 0x03
#define DOM_MSTR 0x0F
#define SYNC_PTRN 0x1F
#define ID_0_7 0x18
#define ID_8_F 0x11
#define ID_10_17 0x12
#define ID_18_1F 0x0B
#define MISC_CODE 0x14
#define CLR_P_FLAG 0x18
#define LOCATE_ON 0x12
#define LOCATE_OFF 0x0B
#define LVL_1_MST 0x00
#define LVL_2_MST 0x40
#define DOM_LVL_2 0xC0
#define INIT_SELTD 0x01
#define LEVEL2_TAR 0x02
enum scam_id_st { ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,
ID13,ID14,ID15,ID_UNUSED,ID_UNASSIGNED,ID_ASSIGNED,LEGACY,
CLR_PRIORITY,NO_ID_AVAIL };
typedef struct SCCBscam_info {
UCHAR id_string[ID_STRING_LENGTH];
enum scam_id_st state;
} SCCBSCAM_INFO, *PSCCBSCAM_INFO;
#endif
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: scsi2.h $
*
* Description: Register definitions for HARPOON ASIC.
*
* $Date: 1996/11/13 18:32:57 $
*
* $Revision: 1.4 $
*
*----------------------------------------------------------------------*/
#ifndef __SCSI_H__
#define __SCSI_H__
#define SCSI_TEST_UNIT_READY 0x00
#define SCSI_REZERO_UNIT 0x01
#define SCSI_REQUEST_SENSE 0x03
#define SCSI_FORMAT_UNIT 0x04
#define SCSI_REASSIGN 0x07
#define SCSI_READ 0x08
#define SCSI_WRITE 0x0A
#define SCSI_SEEK 0x0B
#define SCSI_INQUIRY 0x12
#define SCSI_MODE_SELECT 0x15
#define SCSI_RESERVE_UNIT 0x16
#define SCSI_RELEASE_UNIT 0x17
#define SCSI_MODE_SENSE 0x1A
#define SCSI_START_STOP_UNIT 0x1B
#define SCSI_SEND_DIAGNOSTIC 0x1D
#define SCSI_READ_CAPACITY 0x25
#define SCSI_READ_EXTENDED 0x28
#define SCSI_WRITE_EXTENDED 0x2A
#define SCSI_SEEK_EXTENDED 0x2B
#define SCSI_WRITE_AND_VERIFY 0x2E
#define SCSI_VERIFY 0x2F
#define SCSI_READ_DEFECT_DATA 0x37
#define SCSI_WRITE_BUFFER 0x3B
#define SCSI_READ_BUFFER 0x3C
#define SCSI_RECV_DIAGNOSTIC 0x1C
#define SCSI_READ_LONG 0x3E
#define SCSI_WRITE_LONG 0x3F
#define SCSI_LAST_SCSI_CMND SCSI_WRITE_LONG
#define SCSI_INVALID_CMND 0xFF
#define SSGOOD 0x00
#define SSCHECK 0x02
#define SSCOND_MET 0x04
#define SSBUSY 0x08
#define SSRESERVATION_CONFLICT 0x18
#define SSCMD_TERM 0x22
#define SSQ_FULL 0x28
#define SKNO_SEN 0x00
#define SKRECOV_ERR 0x01
#define SKNOT_RDY 0x02
#define SKMED_ERR 0x03
#define SKHW_ERR 0x04
#define SKILL_REQ 0x05
#define SKUNIT_ATTN 0x06
#define SKDATA_PROTECT 0x07
#define SKBLNK_CHK 0x08
#define SKCPY_ABORT 0x0A
#define SKABORT_CMD 0x0B
#define SKEQUAL 0x0C
#define SKVOL_OVF 0x0D
#define SKMIS_CMP 0x0E
#define SMCMD_COMP 0x00
#define SMEXT 0x01
#define SMSAVE_DATA_PTR 0x02
#define SMREST_DATA_PTR 0x03
#define SMDISC 0x04
#define SMINIT_DETEC_ERR 0x05
#define SMABORT 0x06
#define SMREJECT 0x07
#define SMNO_OP 0x08
#define SMPARITY 0x09
#define SMDEV_RESET 0x0C
#define SMABORT_TAG 0x0D
#define SMINIT_RECOVERY 0x0F
#define SMREL_RECOVERY 0x10
#define SMIDENT 0x80
#define DISC_PRIV 0x40
#define SMSYNC 0x01
#define SM10MBS 0x19 /* 100ns */
#define SM5MBS 0x32 /* 200ns */
#define SMOFFSET 0x0F /* Maxoffset value */
#define SMWDTR 0x03
#define SM8BIT 0x00
#define SM16BIT 0x01
#define SM32BIT 0x02
#define SMIGNORWR 0x23 /* Ignore Wide Residue */
#define ARBITRATION_DELAY 0x01 /* 2.4us using a 40Mhz clock */
#define BUS_SETTLE_DELAY 0x01 /* 400ns */
#define BUS_CLEAR_DELAY 0x01 /* 800ns */
#define SPHASE_TO 0x0A /* 10 second timeout waiting for */
#define SCMD_TO 0x0F /* Overall command timeout */
#define SIX_BYTE_CMD 0x06
#define TEN_BYTE_CMD 0x0A
#define TWELVE_BYTE_CMD 0x0C
#define ASYNC 0x00
#define PERI25NS 0x06 /* 25/4ns to next clock for xbow. */
#define SYNC10MBS 0x19
#define SYNC5MBS 0x32
#define MAX_OFFSET 0x0F /* Maxbyteoffset for Sync Xfers */
#endif
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: eeprom.h $
*
* Description: Definitions for EEPROM related structures
*
* $Date: 1996/11/13 18:28:39 $
*
* $Revision: 1.4 $
*
*----------------------------------------------------------------------*/
#ifndef __EEPROM__
#define __EEPROM__
/*#include <globals.h>*/
#define EEPROM_WD_CNT 256
#define EEPROM_CHECK_SUM 0
#define FW_SIGNATURE 2
#define MODEL_NUMB_0 4
#define MODEL_NUMB_1 5
#define MODEL_NUMB_2 6
#define MODEL_NUMB_3 7
#define MODEL_NUMB_4 8
#define MODEL_NUMB_5 9
#define IO_BASE_ADDR 10
#define IRQ_NUMBER 12
#define PCI_INT_PIN 13
#define BUS_DELAY 14 /*On time in byte 14 off delay in 15 */
#define SYSTEM_CONFIG 16
#define SCSI_CONFIG 17
#define BIOS_CONFIG 18
#define SPIN_UP_DELAY 19
#define SCAM_CONFIG 20
#define ADAPTER_SCSI_ID 24
#define IGNORE_B_SCAN 32
#define SEND_START_ENA 34
#define DEVICE_ENABLE 36
#define SYNC_RATE_TBL 38
#define SYNC_RATE_TBL01 38
#define SYNC_RATE_TBL23 40
#define SYNC_RATE_TBL45 42
#define SYNC_RATE_TBL67 44
#define SYNC_RATE_TBL89 46
#define SYNC_RATE_TBLab 48
#define SYNC_RATE_TBLcd 50
#define SYNC_RATE_TBLef 52
#define EE_SCAMBASE 256
#define DOM_MASTER (BIT(0) + BIT(1))
#define SCAM_ENABLED BIT(2)
#define SCAM_LEVEL2 BIT(3)
#define RENEGO_ENA BITW(10)
#define CONNIO_ENA BITW(11)
#define GREEN_PC_ENA BITW(12)
#define AUTO_RATE_00 00
#define AUTO_RATE_05 01
#define AUTO_RATE_10 02
#define AUTO_RATE_20 03
#define WIDE_NEGO_BIT BIT(7)
#define DISC_ENABLE_BIT BIT(6)
#endif
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: harpoon.h $
*
* Description: Register definitions for HARPOON ASIC.
*
* $Date: 1997/07/09 21:44:36 $
*
* $Revision: 1.9 $
*
*----------------------------------------------------------------------*/
/*#include <globals.h>*/
#ifndef __HARPOON__
#define __HARPOON__
#define hp_vendor_id_0 0x00 /* LSB */
#define ORION_VEND_0 0x4B
#define hp_vendor_id_1 0x01 /* MSB */
#define ORION_VEND_1 0x10
#define hp_device_id_0 0x02 /* LSB */
#define ORION_DEV_0 0x30
#define hp_device_id_1 0x03 /* MSB */
#define ORION_DEV_1 0x81
/* Sub Vendor ID and Sub Device ID only available in
Harpoon Version 2 and higher */
#define hp_sub_vendor_id_0 0x04 /* LSB */
#define hp_sub_vendor_id_1 0x05 /* MSB */
#define hp_sub_device_id_0 0x06 /* LSB */
#define hp_sub_device_id_1 0x07 /* MSB */
#define hp_dual_addr_lo 0x08
#define hp_dual_addr_lmi 0x09
#define hp_dual_addr_hmi 0x0A
#define hp_dual_addr_hi 0x0B
#define hp_semaphore 0x0C
#define SCCB_MGR_ACTIVE BIT(0)
#define TICKLE_ME BIT(1)
#define SCCB_MGR_PRESENT BIT(3)
#define BIOS_IN_USE BIT(4)
#define hp_user_defined_D 0x0D
#define hp_reserved_E 0x0E
#define hp_sys_ctrl 0x0F
#define STOP_CLK BIT(0) /*Turn off BusMaster Clock */
#define DRVR_RST BIT(1) /*Firmware Reset to 80C15 chip */
#define HALT_MACH BIT(3) /*Halt State Machine */
#define HARD_ABORT BIT(4) /*Hard Abort */
#define DIAG_MODE BIT(5) /*Diagnostic Mode */
#define BM_ABORT_TMOUT 0x50 /*Halt State machine time out */
#define hp_sys_cfg 0x10
#define DONT_RST_FIFO BIT(7) /*Don't reset FIFO */
#define hp_host_ctrl0 0x11
#define DUAL_ADDR_MODE BIT(0) /*Enable 64-bit addresses */
#define IO_MEM_SPACE BIT(1) /*I/O Memory Space */
#define RESOURCE_LOCK BIT(2) /*Enable Resource Lock */
#define IGNOR_ACCESS_ERR BIT(3) /*Ignore Access Error */
#define HOST_INT_EDGE BIT(4) /*Host interrupt level/edge mode sel */
#define SIX_CLOCKS BIT(5) /*6 Clocks between Strobe */
#define DMA_EVEN_PARITY BIT(6) /*Enable DMA Enen Parity */
/*
#define BURST_MODE BIT(0)
*/
#define hp_reserved_12 0x12
#define hp_host_blk_cnt 0x13
#define XFER_BLK1 0x00 /* 0 0 0 1 byte per block*/
#define XFER_BLK2 0x01 /* 0 0 1 2 byte per block*/
#define XFER_BLK4 0x02 /* 0 1 0 4 byte per block*/
#define XFER_BLK8 0x03 /* 0 1 1 8 byte per block*/
#define XFER_BLK16 0x04 /* 1 0 0 16 byte per block*/
#define XFER_BLK32 0x05 /* 1 0 1 32 byte per block*/
#define XFER_BLK64 0x06 /* 1 1 0 64 byte per block*/
#define BM_THRESHOLD 0x40 /* PCI mode can only xfer 16 bytes*/
#define hp_reserved_14 0x14
#define hp_reserved_15 0x15
#define hp_reserved_16 0x16
#define hp_int_mask 0x17
#define INT_CMD_COMPL BIT(0) /* DMA command complete */
#define INT_EXT_STATUS BIT(1) /* Extended Status Set */
#define INT_SCSI BIT(2) /* Scsi block interrupt */
#define INT_FIFO_RDY BIT(4) /* FIFO data ready */
#define hp_xfer_cnt_lo 0x18
#define hp_xfer_cnt_mi 0x19
#define hp_xfer_cnt_hi 0x1A
#define hp_xfer_cmd 0x1B
#define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
#define XFER_DMA_HOST 0x01 /* 0 0 1 Transfer DMA -> Host */
#define XFER_HOST_MPU 0x02 /* 0 1 0 Transfer Host -> MPU */
#define XFER_MPU_HOST 0x03 /* 0 1 1 Transfer MPU -> Host */
#define XFER_DMA_MPU 0x04 /* 1 0 0 Transfer DMA -> MPU */
#define XFER_MPU_DMA 0x05 /* 1 0 1 Transfer MPU -> DMA */
#define SET_SEMAPHORE 0x06 /* 1 1 0 Set Semaphore */
#define XFER_NOP 0x07 /* 1 1 1 Transfer NOP */
#define XFER_MB_MPU 0x06 /* 1 1 0 Transfer MB -> MPU */
#define XFER_MB_DMA 0x07 /* 1 1 1 Transfer MB -> DMA */
#define XFER_HOST_AUTO 0x00 /* 0 0 Auto Transfer Size */
#define XFER_HOST_8BIT 0x08 /* 0 1 8 BIT Transfer Size */
#define XFER_HOST_16BIT 0x10 /* 1 0 16 BIT Transfer Size */
#define XFER_HOST_32BIT 0x18 /* 1 1 32 BIT Transfer Size */
#define XFER_DMA_8BIT 0x20 /* 0 1 8 BIT Transfer Size */
#define XFER_DMA_16BIT 0x40 /* 1 0 16 BIT Transfer Size */
#define DISABLE_INT BIT(7) /*Do not interrupt at end of cmd. */
#define HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_8BIT))
#define HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_8BIT))
#define WIDE_HOST_WRT_CMD ((DISABLE_INT + XFER_HOST_DMA + XFER_HOST_AUTO + XFER_DMA_16BIT))
#define WIDE_HOST_RD_CMD ((DISABLE_INT + XFER_DMA_HOST + XFER_HOST_AUTO + XFER_DMA_16BIT))
#define hp_host_addr_lo 0x1C
#define hp_host_addr_lmi 0x1D
#define hp_host_addr_hmi 0x1E
#define hp_host_addr_hi 0x1F
#define hp_pio_data 0x20
#define hp_reserved_21 0x21
#define hp_ee_ctrl 0x22
#define EXT_ARB_ACK BIT(7)
#define SCSI_TERM_ENA_H BIT(6) /* SCSI high byte terminator */
#define SEE_MS BIT(5)
#define SEE_CS BIT(3)
#define SEE_CLK BIT(2)
#define SEE_DO BIT(1)
#define SEE_DI BIT(0)
#define EE_READ 0x06
#define EE_WRITE 0x05
#define EWEN 0x04
#define EWEN_ADDR 0x03C0
#define EWDS 0x04
#define EWDS_ADDR 0x0000
#define hp_brdctl 0x23
#define DAT_7 BIT(7)
#define DAT_6 BIT(6)
#define DAT_5 BIT(5)
#define BRD_STB BIT(4)
#define BRD_CS BIT(3)
#define BRD_WR BIT(2)
#define hp_reserved_24 0x24
#define hp_reserved_25 0x25
#define hp_bm_ctrl 0x26
#define SCSI_TERM_ENA_L BIT(0) /*Enable/Disable external terminators */
#define FLUSH_XFER_CNTR BIT(1) /*Flush transfer counter */
#define BM_XFER_MIN_8 BIT(2) /*Enable bus master transfer of 9 */
#define BIOS_ENA BIT(3) /*Enable BIOS/FLASH Enable */
#define FORCE1_XFER BIT(5) /*Always xfer one byte in byte mode */
#define FAST_SINGLE BIT(6) /*?? */
#define BMCTRL_DEFAULT (FORCE1_XFER|FAST_SINGLE|SCSI_TERM_ENA_L)
#define hp_reserved_27 0x27
#define hp_sg_addr 0x28
#define hp_page_ctrl 0x29
#define SCATTER_EN BIT(0)
#define SGRAM_ARAM BIT(1)
#define BIOS_SHADOW BIT(2)
#define G_INT_DISABLE BIT(3) /* Enable/Disable all Interrupts */
#define NARROW_SCSI_CARD BIT(4) /* NARROW/WIDE SCSI config pin */
#define hp_reserved_2A 0x2A
#define hp_pci_cmd_cfg 0x2B
#define IO_SPACE_ENA BIT(0) /*enable I/O space */
#define MEM_SPACE_ENA BIT(1) /*enable memory space */
#define BUS_MSTR_ENA BIT(2) /*enable bus master operation */
#define MEM_WI_ENA BIT(4) /*enable Write and Invalidate */
#define PAR_ERR_RESP BIT(6) /*enable parity error responce. */
#define hp_reserved_2C 0x2C
#define hp_pci_stat_cfg 0x2D
#define DATA_PARITY_ERR BIT(0)
#define REC_TARGET_ABORT BIT(4) /*received Target abort */
#define REC_MASTER_ABORT BIT(5) /*received Master abort */
#define SIG_SYSTEM_ERR BIT(6)
#define DETECTED_PAR_ERR BIT(7)
#define hp_reserved_2E 0x2E
#define hp_sys_status 0x2F
#define SLV_DATA_RDY BIT(0) /*Slave data ready */
#define XFER_CNT_ZERO BIT(1) /*Transfer counter = 0 */
#define BM_FIFO_EMPTY BIT(2) /*FIFO empty */
#define BM_FIFO_FULL BIT(3) /*FIFO full */
#define HOST_OP_DONE BIT(4) /*host operation done */
#define DMA_OP_DONE BIT(5) /*DMA operation done */
#define SLV_OP_DONE BIT(6) /*Slave operation done */
#define PWR_ON_FLAG BIT(7) /*Power on flag */
#define hp_reserved_30 0x30
#define hp_host_status0 0x31
#define HOST_TERM BIT(5) /*Host Terminal Count */
#define HOST_TRSHLD BIT(6) /*Host Threshold */
#define CONNECTED_2_HOST BIT(7) /*Connected to Host */
#define hp_reserved_32 0x32
#define hp_rev_num 0x33
#define REV_A_CONST 0x0E
#define REV_B_CONST 0x0E
#define hp_stack_data 0x34
#define hp_stack_addr 0x35
#define hp_ext_status 0x36
#define BM_FORCE_OFF BIT(0) /*Bus Master is forced to get off */
#define PCI_TGT_ABORT BIT(0) /*PCI bus master transaction aborted */
#define PCI_DEV_TMOUT BIT(1) /*PCI Device Time out */
#define FIFO_TC_NOT_ZERO BIT(2) /*FIFO or transfer counter not zero */
#define CHIP_RST_OCCUR BIT(3) /*Chip reset occurs */
#define CMD_ABORTED BIT(4) /*Command aborted */
#define BM_PARITY_ERR BIT(5) /*parity error on data received */
#define PIO_OVERRUN BIT(6) /*Slave data overrun */
#define BM_CMD_BUSY BIT(7) /*Bus master transfer command busy */
#define BAD_EXT_STATUS (BM_FORCE_OFF | PCI_DEV_TMOUT | CMD_ABORTED |
BM_PARITY_ERR | PIO_OVERRUN)
#define hp_int_status 0x37
#define BM_CMD_CMPL BIT(0) /*Bus Master command complete */
#define EXT_STATUS_ON BIT(1) /*Extended status is valid */
#define SCSI_INTERRUPT BIT(2) /*Global indication of a SCSI int. */
#define BM_FIFO_RDY BIT(4)
#define INT_ASSERTED BIT(5) /* */
#define SRAM_BUSY BIT(6) /*Scatter/Gather RAM busy */
#define CMD_REG_BUSY BIT(7)
#define hp_fifo_cnt 0x38
#define hp_curr_host_cnt 0x39
#define hp_reserved_3A 0x3A
#define hp_fifo_in_addr 0x3B
#define hp_fifo_out_addr 0x3C
#define hp_reserved_3D 0x3D
#define hp_reserved_3E 0x3E
#define hp_reserved_3F 0x3F
extern USHORT default_intena;
#define hp_intena 0x40
#define RESET BITW(7)
#define PROG_HLT BITW(6)
#define PARITY BITW(5)
#define FIFO BITW(4)
#define SEL BITW(3)
#define SCAM_SEL BITW(2)
#define RSEL BITW(1)
#define TIMEOUT BITW(0)
#define BUS_FREE BITW(15)
#define XFER_CNT_0 BITW(14)
#define PHASE BITW(13)
#define IUNKWN BITW(12)
#define ICMD_COMP BITW(11)
#define ITICKLE BITW(10)
#define IDO_STRT BITW(9)
#define ITAR_DISC BITW(8)
#define AUTO_INT (BITW(12)+BITW(11)+BITW(10)+BITW(9)+BITW(8))
#define CLR_ALL_INT 0xFFFF
#define CLR_ALL_INT_1 0xFF00
#define hp_intstat 0x42
#define hp_scsisig 0x44
#define SCSI_SEL BIT(7)
#define SCSI_BSY BIT(6)
#define SCSI_REQ BIT(5)
#define SCSI_ACK BIT(4)
#define SCSI_ATN BIT(3)
#define SCSI_CD BIT(2)
#define SCSI_MSG BIT(1)
#define SCSI_IOBIT BIT(0)
#define S_SCSI_PHZ (BIT(2)+BIT(1)+BIT(0))
#define S_CMD_PH (BIT(2) )
#define S_MSGO_PH (BIT(2)+BIT(1) )
#define S_STAT_PH (BIT(2) +BIT(0))
#define S_MSGI_PH (BIT(2)+BIT(1)+BIT(0))
#define S_DATAI_PH ( BIT(0))
#define S_DATAO_PH 0x00
#define S_ILL_PH ( BIT(1) )
#define hp_scsictrl_0 0x45
#define NO_ARB BIT(7)
#define SEL_TAR BIT(6)
#define ENA_ATN BIT(4)
#define ENA_RESEL BIT(2)
#define SCSI_RST BIT(1)
#define ENA_SCAM_SEL BIT(0)
#define hp_portctrl_0 0x46
#define SCSI_PORT BIT(7)
#define SCSI_INBIT BIT(6)
#define DMA_PORT BIT(5)
#define DMA_RD BIT(4)
#define HOST_PORT BIT(3)
#define HOST_WRT BIT(2)
#define SCSI_BUS_EN BIT(1)
#define START_TO BIT(0)
#define hp_scsireset 0x47
#define SCSI_TAR BIT(7)
#define SCSI_INI BIT(6)
#define SCAM_EN BIT(5)
#define ACK_HOLD BIT(4)
#define DMA_RESET BIT(3)
#define HPSCSI_RESET BIT(2)
#define PROG_RESET BIT(1)
#define FIFO_CLR BIT(0)
#define hp_xfercnt_0 0x48
#define hp_xfercnt_1 0x49
#define hp_xfercnt_2 0x4A
#define hp_xfercnt_3 0x4B
#define hp_fifodata_0 0x4C
#define hp_fifodata_1 0x4D
#define hp_addstat 0x4E
#define SCAM_TIMER BIT(7)
#define AUTO_RUNNING BIT(6)
#define FAST_SYNC BIT(5)
#define SCSI_MODE8 BIT(3)
#define SCSI_PAR_ERR BIT(0)
#define hp_prgmcnt_0 0x4F
#define AUTO_PC_MASK 0x3F
#define hp_selfid_0 0x50
#define hp_selfid_1 0x51
#define hp_arb_id 0x52
#define ARB_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0))
#define hp_select_id 0x53
#define RESEL_ID (BIT(7) + BIT(6) + BIT(5) + BIT(4))
#define SELECT_ID (BIT(3) + BIT(2) + BIT(1) + BIT(0))
#define hp_synctarg_base 0x54
#define hp_synctarg_12 0x54
#define hp_synctarg_13 0x55
#define hp_synctarg_14 0x56
#define hp_synctarg_15 0x57
#define hp_synctarg_8 0x58
#define hp_synctarg_9 0x59
#define hp_synctarg_10 0x5A
#define hp_synctarg_11 0x5B
#define hp_synctarg_4 0x5C
#define hp_synctarg_5 0x5D
#define hp_synctarg_6 0x5E
#define hp_synctarg_7 0x5F
#define hp_synctarg_0 0x60
#define hp_synctarg_1 0x61
#define hp_synctarg_2 0x62
#define hp_synctarg_3 0x63
#define RATE_20MB 0x00
#define RATE_10MB ( BIT(5))
#define RATE_6_6MB ( BIT(6) )
#define RATE_5MB ( BIT(6)+BIT(5))
#define RATE_4MB (BIT(7) )
#define RATE_3_33MB (BIT(7) +BIT(5))
#define RATE_2_85MB (BIT(7)+BIT(6) )
#define RATE_2_5MB (BIT(7)+BIT(5)+BIT(6))
#define NEXT_CLK BIT(5)
#define SLOWEST_SYNC (BIT(7)+BIT(6)+BIT(5))
#define NARROW_SCSI BIT(4)
#define SYNC_OFFSET (BIT(3) + BIT(2) + BIT(1) + BIT(0))
#define DEFAULT_ASYNC 0x00
#define DEFAULT_OFFSET 0x0F
#define hp_autostart_0 0x64
#define hp_autostart_1 0x65
#define hp_autostart_2 0x66
#define hp_autostart_3 0x67
#define DISABLE 0x00
#define AUTO_IMMED BIT(5)
#define SELECT BIT(6)
#define RESELECT (BIT(6)+BIT(5))
#define BUSFREE BIT(7)
#define XFER_0 (BIT(7)+BIT(5))
#define END_DATA (BIT(7)+BIT(6))
#define MSG_PHZ (BIT(7)+BIT(6)+BIT(5))
#define hp_gp_reg_0 0x68
#define hp_gp_reg_1 0x69
#define hp_gp_reg_2 0x6A
#define hp_gp_reg_3 0x6B
#define hp_seltimeout 0x6C
#define TO_2ms 0x54 /* 2.0503ms */
#define TO_4ms 0x67 /* 3.9959ms */
#define TO_5ms 0x03 /* 4.9152ms */
#define TO_10ms 0x07 /* 11.xxxms */
#define TO_250ms 0x99 /* 250.68ms */
#define TO_290ms 0xB1 /* 289.99ms */
#define TO_350ms 0xD6 /* 350.62ms */
#define TO_417ms 0xFF /* 417.79ms */
#define hp_clkctrl_0 0x6D
#define PWR_DWN BIT(6)
#define ACTdeassert BIT(4)
#define ATNonErr BIT(3)
#define CLK_30MHZ BIT(1)
#define CLK_40MHZ (BIT(1) + BIT(0))
#define CLK_50MHZ BIT(2)
#define CLKCTRL_DEFAULT (ACTdeassert | CLK_40MHZ)
#define hp_fiforead 0x6E
#define hp_fifowrite 0x6F
#define hp_offsetctr 0x70
#define hp_xferstat 0x71
#define FIFO_FULL BIT(7)
#define FIFO_EMPTY BIT(6)
#define FIFO_MASK 0x3F /* Mask for the FIFO count value. */
#define FIFO_LEN 0x20
#define hp_portctrl_1 0x72
#define EVEN_HOST_P BIT(5)
#define INVT_SCSI BIT(4)
#define CHK_SCSI_P BIT(3)
#define HOST_MODE8 BIT(0)
#define HOST_MODE16 0x00
#define hp_xfer_pad 0x73
#define ID_UNLOCK BIT(3)
#define XFER_PAD BIT(2)
#define hp_scsidata_0 0x74
#define hp_scsidata_1 0x75
#define hp_timer_0 0x76
#define hp_timer_1 0x77
#define hp_reserved_78 0x78
#define hp_reserved_79 0x79
#define hp_reserved_7A 0x7A
#define hp_reserved_7B 0x7B
#define hp_reserved_7C 0x7C
#define hp_reserved_7D 0x7D
#define hp_reserved_7E 0x7E
#define hp_reserved_7F 0x7F
#define hp_aramBase 0x80
#define BIOS_DATA_OFFSET 0x60
#define BIOS_RELATIVE_CARD 0x64
#define AUTO_LEN 0x80
#define AR0 0x00
#define AR1 BITW(8)
#define AR2 BITW(9)
#define AR3 (BITW(9) + BITW(8))
#define SDATA BITW(10)
#define NOP_OP 0x00 /* Nop command */
#define CRD_OP BITW(11) /* Cmp Reg. w/ Data */
#define CRR_OP BITW(12) /* Cmp Reg. w. Reg. */
#define CBE_OP (BITW(14)+BITW(12)+BITW(11)) /* Cmp SCSI cmd class & Branch EQ */
#define CBN_OP (BITW(14)+BITW(13)) /* Cmp SCSI cmd class & Branch NOT EQ */
#define CPE_OP (BITW(14)+BITW(11)) /* Cmp SCSI phs & Branch EQ */
#define CPN_OP (BITW(14)+BITW(12)) /* Cmp SCSI phs & Branch NOT EQ */
#define ADATA_OUT 0x00
#define ADATA_IN BITW(8)
#define ACOMMAND BITW(10)
#define ASTATUS (BITW(10)+BITW(8))
#define AMSG_OUT (BITW(10)+BITW(9))
#define AMSG_IN (BITW(10)+BITW(9)+BITW(8))
#define AILLEGAL (BITW(9)+BITW(8))
#define BRH_OP BITW(13) /* Branch */
#define ALWAYS 0x00
#define EQUAL BITW(8)
#define NOT_EQ BITW(9)
#define TCB_OP (BITW(13)+BITW(11)) /* Test condition & branch */
#define ATN_SET BITW(8)
#define ATN_RESET BITW(9)
#define XFER_CNT (BITW(9)+BITW(8))
#define FIFO_0 BITW(10)
#define FIFO_NOT0 (BITW(10)+BITW(8))
#define T_USE_SYNC0 (BITW(10)+BITW(9))
#define MPM_OP BITW(15) /* Match phase and move data */
#define MDR_OP (BITW(12)+BITW(11)) /* Move data to Reg. */
#define MRR_OP BITW(14) /* Move DReg. to Reg. */
#define S_IDREG (BIT(2)+BIT(1)+BIT(0))
#define D_AR0 0x00
#define D_AR1 BIT(0)
#define D_AR2 BIT(1)
#define D_AR3 (BIT(1) + BIT(0))
#define D_SDATA BIT(2)
#define D_BUCKET (BIT(2) + BIT(1) + BIT(0))
#define ADR_OP (BITW(13)+BITW(12)) /* Logical AND Reg. w. Data */
#define ADS_OP (BITW(14)+BITW(13)+BITW(12))
#define ODR_OP (BITW(13)+BITW(12)+BITW(11))
#define ODS_OP (BITW(14)+BITW(13)+BITW(12)+BITW(11))
#define STR_OP (BITW(15)+BITW(14)) /* Store to A_Reg. */
#define AINT_ENA1 0x00
#define AINT_STAT1 BITW(8)
#define ASCSI_SIG BITW(9)
#define ASCSI_CNTL (BITW(9)+BITW(8))
#define APORT_CNTL BITW(10)
#define ARST_CNTL (BITW(10)+BITW(8))
#define AXFERCNT0 (BITW(10)+BITW(9))
#define AXFERCNT1 (BITW(10)+BITW(9)+BITW(8))
#define AXFERCNT2 BITW(11)
#define AFIFO_DATA (BITW(11)+BITW(8))
#define ASCSISELID (BITW(11)+BITW(9))
#define ASCSISYNC0 (BITW(11)+BITW(9)+BITW(8))
#define RAT_OP (BITW(14)+BITW(13)+BITW(11))
#define SSI_OP (BITW(15)+BITW(11))
#define SSI_ITAR_DISC (ITAR_DISC >> 8)
#define SSI_IDO_STRT (IDO_STRT >> 8)
#define SSI_IDI_STRT (IDO_STRT >> 8)
#define SSI_ICMD_COMP (ICMD_COMP >> 8)
#define SSI_ITICKLE (ITICKLE >> 8)
#define SSI_IUNKWN (IUNKWN >> 8)
#define SSI_INO_CC (IUNKWN >> 8)
#define SSI_IRFAIL (IUNKWN >> 8)
#define NP 0x10 /*Next Phase */
#define NTCMD 0x02 /*Non- Tagged Command start */
#define CMDPZ 0x04 /*Command phase */
#define DINT 0x12 /*Data Out/In interrupt */
#define DI 0x13 /*Data Out */
#define MI 0x14 /*Message In */
#define DC 0x19 /*Disconnect Message */
#define ST 0x1D /*Status Phase */
#define UNKNWN 0x24 /*Unknown bus action */
#define CC 0x25 /*Command Completion failure */
#define TICK 0x26 /*New target reselected us. */
#define RFAIL 0x27 /*Reselection failed */
#define SELCHK 0x28 /*Select & Check SCSI ID latch reg */
#define ID_MSG_STRT hp_aramBase + 0x00
#define NON_TAG_ID_MSG hp_aramBase + 0x06
#define CMD_STRT hp_aramBase + 0x08
#define SYNC_MSGS hp_aramBase + 0x08
#define TAG_STRT 0x00
#define SELECTION_START 0x00
#define DISCONNECT_START 0x10/2
#define END_DATA_START 0x14/2
#define NONTAG_STRT 0x02/2
#define CMD_ONLY_STRT CMDPZ/2
#define TICKLE_STRT TICK/2
#define SELCHK_STRT SELCHK/2
#define mEEPROM_CLK_DELAY(port) (RD_HARPOON(port+hp_intstat_1))
#define mWAIT_10MS(port) (RD_HARPOON(port+hp_intstat_1))
#define CLR_XFER_CNT(port) (WR_HARPOON(port+hp_xfercnt_0, 0x00))
#define SET_XFER_CNT(port, data) (WR_HARP32(port,hp_xfercnt_0,data))
#define GET_XFER_CNT(port, xfercnt) {RD_HARP32(port,hp_xfercnt_0,xfercnt); xfercnt &= 0xFFFFFF;}
/* #define GET_XFER_CNT(port, xfercnt) (xfercnt = RD_HARPOON(port+hp_xfercnt_2),
xfercnt <<= 16,
xfercnt |= RDW_HARPOON((USHORT)(port+hp_xfercnt_0)))
*/
#if defined(DOS)
#define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((USHORT)(port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),
addr >>= 16,
WRW_HARPOON((USHORT)(port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),
WR_HARP32(port,hp_xfercnt_0,count),
WRW_HARPOON((USHORT)(port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),
count >>= 16,
WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
#else
#define HP_SETUP_ADDR_CNT(port,addr,count) (WRW_HARPOON((port+hp_host_addr_lo), (USHORT)(addr & 0x0000FFFFL)),
addr >>= 16,
WRW_HARPOON((port+hp_host_addr_hmi), (USHORT)(addr & 0x0000FFFFL)),
WR_HARP32(port,hp_xfercnt_0,count),
WRW_HARPOON((port+hp_xfer_cnt_lo), (USHORT)(count & 0x0000FFFFL)),
count >>= 16,
WR_HARPOON(port+hp_xfer_cnt_hi, (count & 0xFF)))
#endif
#define ACCEPT_MSG(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}
WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
#define ACCEPT_MSG_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}
WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
#define ACCEPT_STAT(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}
WR_HARPOON(port+hp_scsisig, S_ILL_PH);}
#define ACCEPT_STAT_ATN(port) {while(RD_HARPOON(port+hp_scsisig) & SCSI_REQ){}
WR_HARPOON(port+hp_scsisig, (S_ILL_PH|SCSI_ATN));}
#define DISABLE_AUTO(port) (WR_HARPOON(port+hp_scsireset, PROG_RESET),
WR_HARPOON(port+hp_scsireset, 0x00))
#define ARAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl,
(RD_HARPOON(p_port+hp_page_ctrl) | SGRAM_ARAM)))
#define SGRAM_ACCESS(p_port) (WR_HARPOON(p_port+hp_page_ctrl,
(RD_HARPOON(p_port+hp_page_ctrl) & ~SGRAM_ARAM)))
#define MDISABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl,
(RD_HARPOON(p_port+hp_page_ctrl) | G_INT_DISABLE)))
#define MENABLE_INT(p_port) (WR_HARPOON(p_port+hp_page_ctrl,
(RD_HARPOON(p_port+hp_page_ctrl) & ~G_INT_DISABLE)))
#endif
#if (FW_TYPE==_UCB_MGR_)
void ReadNVRam(PSCCBcard pCurrCard,PUCB p_ucb);
void WriteNVRam(PSCCBcard pCurrCard,PUCB p_ucb);
void UpdateCheckSum(u32bits baseport);
#endif // (FW_TYPE==_UCB_MGR_)
#if defined(DOS)
UCHAR sfm(USHORT port, PSCCB pcurrSCCB);
void scsiStartAuto(USHORT port);
UCHAR sisyncn(USHORT port, UCHAR p_card, UCHAR syncFlag);
void ssel(USHORT port, UCHAR p_card);
void sres(USHORT port, UCHAR p_card, PSCCBcard pCurrCard);
void sdecm(UCHAR message, USHORT port, UCHAR p_card);
void shandem(USHORT port, UCHAR p_card,PSCCB pCurrSCCB);
void stsyncn(USHORT port, UCHAR p_card);
void sisyncr(USHORT port,UCHAR sync_pulse, UCHAR offset);
void sssyncv(USHORT p_port, UCHAR p_id, UCHAR p_sync_value, PSCCBMgr_tar_info currTar_Info);
void sresb(USHORT port, UCHAR p_card);
void sxfrp(USHORT p_port, UCHAR p_card);
void schkdd(USHORT port, UCHAR p_card);
UCHAR RdStack(USHORT port, UCHAR index);
void WrStack(USHORT portBase, UCHAR index, UCHAR data);
UCHAR ChkIfChipInitialized(USHORT ioPort);
#if defined(V302)
UCHAR GetTarLun(USHORT port, UCHAR p_card, UCHAR our_target, PSCCBcard pCurrCard, PUCHAR tag, PUCHAR lun);
#endif
void SendMsg(USHORT port, UCHAR message);
void queueFlushTargSccb(UCHAR p_card, UCHAR thisTarg, UCHAR error_code);
UCHAR scsellDOS(USHORT p_port, UCHAR targ_id);
#else
UCHAR sfm(ULONG port, PSCCB pcurrSCCB);
void scsiStartAuto(ULONG port);
UCHAR sisyncn(ULONG port, UCHAR p_card, UCHAR syncFlag);
void ssel(ULONG port, UCHAR p_card);
void sres(ULONG port, UCHAR p_card, PSCCBcard pCurrCard);
void sdecm(UCHAR message, ULONG port, UCHAR p_card);
void shandem(ULONG port, UCHAR p_card,PSCCB pCurrSCCB);
void stsyncn(ULONG port, UCHAR p_card);
void sisyncr(ULONG port,UCHAR sync_pulse, UCHAR offset);
void sssyncv(ULONG p_port, UCHAR p_id, UCHAR p_sync_value, PSCCBMgr_tar_info currTar_Info);
void sresb(ULONG port, UCHAR p_card);
void sxfrp(ULONG p_port, UCHAR p_card);
void schkdd(ULONG port, UCHAR p_card);
UCHAR RdStack(ULONG port, UCHAR index);
void WrStack(ULONG portBase, UCHAR index, UCHAR data);
UCHAR ChkIfChipInitialized(ULONG ioPort);
#if defined(V302)
UCHAR GetTarLun(ULONG port, UCHAR p_card, UCHAR our_target, PSCCBcard pCurrCard, PUCHAR tar, PUCHAR lun);
#endif
void SendMsg(ULONG port, UCHAR message);
void queueFlushTargSccb(UCHAR p_card, UCHAR thisTarg, UCHAR error_code);
#endif
void ssenss(PSCCBcard pCurrCard);
void sinits(PSCCB p_sccb, UCHAR p_card);
void RNVRamData(PNVRamInfo pNvRamInfo);
#if defined(WIDE_SCSI)
#if defined(DOS)
UCHAR siwidn(USHORT port, UCHAR p_card);
void stwidn(USHORT port, UCHAR p_card);
void siwidr(USHORT port, UCHAR width);
#else
UCHAR siwidn(ULONG port, UCHAR p_card);
void stwidn(ULONG port, UCHAR p_card);
void siwidr(ULONG port, UCHAR width);
#endif
#endif
void queueSelectFail(PSCCBcard pCurrCard, UCHAR p_card);
void queueDisconnect(PSCCB p_SCCB, UCHAR p_card);
void queueCmdComplete(PSCCBcard pCurrCard, PSCCB p_SCCB, UCHAR p_card);
void queueSearchSelect(PSCCBcard pCurrCard, UCHAR p_card);
void queueFlushSccb(UCHAR p_card, UCHAR error_code);
void queueAddSccb(PSCCB p_SCCB, UCHAR card);
UCHAR queueFindSccb(PSCCB p_SCCB, UCHAR p_card);
void utilUpdateResidual(PSCCB p_SCCB);
USHORT CalcCrc16(UCHAR buffer[]);
UCHAR CalcLrc(UCHAR buffer[]);
#if defined(DOS)
void Wait1Second(USHORT p_port);
void Wait(USHORT p_port, UCHAR p_delay);
void utilEEWriteOnOff(USHORT p_port,UCHAR p_mode);
void utilEEWrite(USHORT p_port, USHORT ee_data, USHORT ee_addr);
USHORT utilEERead(USHORT p_port, USHORT ee_addr);
USHORT utilEEReadOrg(USHORT p_port, USHORT ee_addr);
void utilEESendCmdAddr(USHORT p_port, UCHAR ee_cmd, USHORT ee_addr);
#else
void Wait1Second(ULONG p_port);
void Wait(ULONG p_port, UCHAR p_delay);
void utilEEWriteOnOff(ULONG p_port,UCHAR p_mode);
void utilEEWrite(ULONG p_port, USHORT ee_data, USHORT ee_addr);
USHORT utilEERead(ULONG p_port, USHORT ee_addr);
USHORT utilEEReadOrg(ULONG p_port, USHORT ee_addr);
void utilEESendCmdAddr(ULONG p_port, UCHAR ee_cmd, USHORT ee_addr);
#endif
#if defined(OS2)
void far phaseDataOut(ULONG port, UCHAR p_card);
void far phaseDataIn(ULONG port, UCHAR p_card);
void far phaseCommand(ULONG port, UCHAR p_card);
void far phaseStatus(ULONG port, UCHAR p_card);
void far phaseMsgOut(ULONG port, UCHAR p_card);
void far phaseMsgIn(ULONG port, UCHAR p_card);
void far phaseIllegal(ULONG port, UCHAR p_card);
#else
#if defined(DOS)
void phaseDataOut(USHORT port, UCHAR p_card);
void phaseDataIn(USHORT port, UCHAR p_card);
void phaseCommand(USHORT port, UCHAR p_card);
void phaseStatus(USHORT port, UCHAR p_card);
void phaseMsgOut(USHORT port, UCHAR p_card);
void phaseMsgIn(USHORT port, UCHAR p_card);
void phaseIllegal(USHORT port, UCHAR p_card);
#else
void phaseDataOut(ULONG port, UCHAR p_card);
void phaseDataIn(ULONG port, UCHAR p_card);
void phaseCommand(ULONG port, UCHAR p_card);
void phaseStatus(ULONG port, UCHAR p_card);
void phaseMsgOut(ULONG port, UCHAR p_card);
void phaseMsgIn(ULONG port, UCHAR p_card);
void phaseIllegal(ULONG port, UCHAR p_card);
#endif
#endif
#if defined(DOS)
void phaseDecode(USHORT port, UCHAR p_card);
void phaseChkFifo(USHORT port, UCHAR p_card);
void phaseBusFree(USHORT p_port, UCHAR p_card);
#else
void phaseDecode(ULONG port, UCHAR p_card);
void phaseChkFifo(ULONG port, UCHAR p_card);
void phaseBusFree(ULONG p_port, UCHAR p_card);
#endif
#if defined(DOS)
void XbowInit(USHORT port, UCHAR scamFlg);
void BusMasterInit(USHORT p_port);
int DiagXbow(USHORT port);
int DiagBusMaster(USHORT port);
void DiagEEPROM(USHORT p_port);
#else
void XbowInit(ULONG port, UCHAR scamFlg);
void BusMasterInit(ULONG p_port);
int DiagXbow(ULONG port);
int DiagBusMaster(ULONG port);
void DiagEEPROM(ULONG p_port);
#endif
#if defined(DOS)
void busMstrAbort(USHORT port);
UCHAR busMstrTimeOut(USHORT port);
void dataXferProcessor(USHORT port, PSCCBcard pCurrCard);
void busMstrSGDataXferStart(USHORT port, PSCCB pCurrSCCB);
void busMstrDataXferStart(USHORT port, PSCCB pCurrSCCB);
void hostDataXferAbort(USHORT port, UCHAR p_card, PSCCB pCurrSCCB);
#else
void busMstrAbort(ULONG port);
UCHAR busMstrTimeOut(ULONG port);
void dataXferProcessor(ULONG port, PSCCBcard pCurrCard);
void busMstrSGDataXferStart(ULONG port, PSCCB pCurrSCCB);
void busMstrDataXferStart(ULONG port, PSCCB pCurrSCCB);
void hostDataXferAbort(ULONG port, UCHAR p_card, PSCCB pCurrSCCB);
#endif
void hostDataXferRestart(PSCCB currSCCB);
#if defined (DOS)
UCHAR SccbMgr_bad_isr(USHORT p_port, UCHAR p_card, PSCCBcard pCurrCard, USHORT p_int);
#else
UCHAR SccbMgr_bad_isr(ULONG p_port, UCHAR p_card, PSCCBcard pCurrCard, USHORT p_int);
#endif
void SccbMgrTableInitAll(void);
void SccbMgrTableInitCard(PSCCBcard pCurrCard, UCHAR p_card);
void SccbMgrTableInitTarget(UCHAR p_card, UCHAR target);
void scini(UCHAR p_card, UCHAR p_our_id, UCHAR p_power_up);
#if defined(DOS)
int scarb(USHORT p_port, UCHAR p_sel_type);
void scbusf(USHORT p_port);
void scsel(USHORT p_port);
void scasid(UCHAR p_card, USHORT p_port);
UCHAR scxferc(USHORT p_port, UCHAR p_data);
UCHAR scsendi(USHORT p_port, UCHAR p_id_string[]);
UCHAR sciso(USHORT p_port, UCHAR p_id_string[]);
void scwirod(USHORT p_port, UCHAR p_data_bit);
void scwiros(USHORT p_port, UCHAR p_data_bit);
UCHAR scvalq(UCHAR p_quintet);
UCHAR scsell(USHORT p_port, UCHAR targ_id);
void scwtsel(USHORT p_port);
void inisci(UCHAR p_card, USHORT p_port, UCHAR p_our_id);
void scsavdi(UCHAR p_card, USHORT p_port);
#else
int scarb(ULONG p_port, UCHAR p_sel_type);
void scbusf(ULONG p_port);
void scsel(ULONG p_port);
void scasid(UCHAR p_card, ULONG p_port);
UCHAR scxferc(ULONG p_port, UCHAR p_data);
UCHAR scsendi(ULONG p_port, UCHAR p_id_string[]);
UCHAR sciso(ULONG p_port, UCHAR p_id_string[]);
void scwirod(ULONG p_port, UCHAR p_data_bit);
void scwiros(ULONG p_port, UCHAR p_data_bit);
UCHAR scvalq(UCHAR p_quintet);
UCHAR scsell(ULONG p_port, UCHAR targ_id);
void scwtsel(ULONG p_port);
void inisci(UCHAR p_card, ULONG p_port, UCHAR p_our_id);
void scsavdi(UCHAR p_card, ULONG p_port);
#endif
UCHAR scmachid(UCHAR p_card, UCHAR p_id_string[]);
#if defined(DOS)
void autoCmdCmplt(USHORT p_port, UCHAR p_card);
void autoLoadDefaultMap(USHORT p_port);
#else
void autoCmdCmplt(ULONG p_port, UCHAR p_card);
void autoLoadDefaultMap(ULONG p_port);
#endif
#if (FW_TYPE==_SCCB_MGR_)
void OS_start_timer(unsigned long ioport, unsigned long timeout);
void OS_stop_timer(unsigned long ioport, unsigned long timeout);
void OS_disable_int(unsigned char intvec);
void OS_enable_int(unsigned char intvec);
void OS_delay(unsigned long count);
int OS_VirtToPhys(u32bits CardHandle, u32bits *physaddr, u32bits *virtaddr);
#if !(defined(UNIX) || defined(OS2) || defined(SOLARIS_REAL_MODE))
void OS_Lock(PSCCBMGR_INFO pCardInfo);
void OS_UnLock(PSCCBMGR_INFO pCardInfo);
#endif // if FW_TYPE == ...
#endif
extern SCCBCARD BL_Card[MAX_CARDS];
extern SCCBMGR_TAR_INFO sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR];
#if defined(OS2)
extern void (far *s_PhaseTbl[8]) (ULONG, UCHAR);
#else
#if defined(DOS)
extern void (*s_PhaseTbl[8]) (USHORT, UCHAR);
#else
extern void (*s_PhaseTbl[8]) (ULONG, UCHAR);
#endif
#endif
extern SCCBSCAM_INFO scamInfo[MAX_SCSI_TAR];
extern NVRAMINFO nvRamInfo[MAX_MB_CARDS];
#if defined(DOS) || defined(OS2)
extern UCHAR temp_id_string[ID_STRING_LENGTH];
#endif
extern UCHAR scamHAString[];
extern UCHAR mbCards;
#if defined(BUGBUG)
extern UCHAR debug_int[MAX_CARDS][debug_size];
extern UCHAR debug_index[MAX_CARDS];
void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
#endif
#if (FW_TYPE==_SCCB_MGR_)
#if defined(DOS)
extern UCHAR first_time;
#endif
#endif /* (FW_TYPE==_SCCB_MGR_) */
#if (FW_TYPE==_UCB_MGR_)
#if defined(DOS)
extern u08bits first_time;
#endif
#endif /* (FW_TYPE==_UCB_MGR_) */
#if defined(BUGBUG)
void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
#endif
extern unsigned int SccbGlobalFlags;
#ident "$Id: sccb.c 1.18 1997/06/10 16:47:04 mohan Exp $"
/*----------------------------------------------------------------------
*
*
*
* This file is available under both the GNU General Public License
* and a BSD-style copyright; see LICENSE.FlashPoint for details.
*
* $Workfile: sccb.c $
*
* Description: Functions relating to handling of the SCCB interface
* between the device driver and the HARPOON.
*
* $Date: 1997/06/10 16:47:04 $
*
* $Revision: 1.18 $
*
*----------------------------------------------------------------------*/
/*#include <globals.h>*/
#if (FW_TYPE==_UCB_MGR_)
/*#include <budi.h>*/
/*#include <budioctl.h>*/
#endif
/*#include <sccbmgr.h>*/
/*#include <blx30.h>*/
/*#include <target.h>*/
/*#include <eeprom.h>*/
/*#include <scsi2.h>*/
/*#include <harpoon.h>*/
#if (FW_TYPE==_SCCB_MGR_)
#define mOS_Lock(card) OS_Lock((PSCCBMGR_INFO)(((PSCCBcard)card)->cardInfo))
#define mOS_UnLock(card) OS_UnLock((PSCCBMGR_INFO)(((PSCCBcard)card)->cardInfo))
#else /* FW_TYPE==_UCB_MGR_ */
#define mOS_Lock(card) OS_Lock((u32bits)(((PSCCBcard)card)->ioPort))
#define mOS_UnLock(card) OS_UnLock((u32bits)(((PSCCBcard)card)->ioPort))
#endif
/*
extern SCCBMGR_TAR_INFO sccbMgrTbl[MAX_CARDS][MAX_SCSI_TAR];
extern SCCBCARD BL_Card[MAX_CARDS];
extern NVRAMINFO nvRamInfo[MAX_MB_CARDS];
extern UCHAR mbCards;
#if defined (OS2)
extern void (far *s_PhaseTbl[8]) (ULONG, UCHAR);
#else
#if defined(DOS)
extern void (*s_PhaseTbl[8]) (USHORT, UCHAR);
#else
extern void (*s_PhaseTbl[8]) (ULONG, UCHAR);
#endif
#endif
#if defined(BUGBUG)
extern UCHAR debug_int[MAX_CARDS][debug_size];
extern UCHAR debug_index[MAX_CARDS];
void Debug_Load(UCHAR p_card, UCHAR p_bug_data);
#endif
*/
#if (FW_TYPE==_SCCB_MGR_)
/*---------------------------------------------------------------------
*
* Function: SccbMgr_sense_adapter
*
* Description: Setup and/or Search for cards and return info to caller.
*
*---------------------------------------------------------------------*/
int SccbMgr_sense_adapter(PSCCBMGR_INFO pCardInfo)
{
#if defined(DOS)
#else
static UCHAR first_time = 1;
#endif
UCHAR i,j,id,ScamFlg;
USHORT temp,temp2,temp3,temp4,temp5,temp6;
#if defined(DOS)
USHORT ioport;
#else
ULONG ioport;
#endif
PNVRamInfo pCurrNvRam;
#if defined(DOS)
ioport = (USHORT)pCardInfo->si_baseaddr;
#else
ioport = pCardInfo->si_baseaddr;
#endif
if (RD_HARPOON(ioport+hp_vendor_id_0) != ORION_VEND_0)
return((int)FAILURE);
if ((RD_HARPOON(ioport+hp_vendor_id_1) != ORION_VEND_1))
return((int)FAILURE);
if ((RD_HARPOON(ioport+hp_device_id_0) != ORION_DEV_0))
return((int)FAILURE);
if ((RD_HARPOON(ioport+hp_device_id_1) != ORION_DEV_1))
return((int)FAILURE);
if (RD_HARPOON(ioport+hp_rev_num) != 0x0f){
/* For new Harpoon then check for sub_device ID LSB
the bits(0-3) must be all ZERO for compatible with
current version of SCCBMgr, else skip this Harpoon
device. */
if (RD_HARPOON(ioport+hp_sub_device_id_0) & 0x0f)
return((int)FAILURE);
}
if (first_time)
{
SccbMgrTableInitAll();
first_time = 0;
mbCards = 0;
}
if(RdStack(ioport, 0) != 0x00) {
if(ChkIfChipInitialized(ioport) == FALSE)
{
pCurrNvRam = NULL;
WR_HARPOON(ioport+hp_semaphore, 0x00);
XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
DiagEEPROM(ioport);
}
else
{
if(mbCards < MAX_MB_CARDS) {
pCurrNvRam = &nvRamInfo[mbCards];
mbCards++;
pCurrNvRam->niBaseAddr = ioport;
RNVRamData(pCurrNvRam);
}else
return((int) FAILURE);
}
}else
pCurrNvRam = NULL;
#if defined (NO_BIOS_OPTION)
pCurrNvRam = NULL;
XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
DiagEEPROM(ioport);
#endif /* No BIOS Option */
WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
if(pCurrNvRam)
pCardInfo->si_id = pCurrNvRam->niAdapId;
else
pCardInfo->si_id = (UCHAR)(utilEERead(ioport, (ADAPTER_SCSI_ID/2)) &
(UCHAR)0x0FF);
pCardInfo->si_lun = 0x00;
pCardInfo->si_fw_revision = ORION_FW_REV;
temp2 = 0x0000;
temp3 = 0x0000;
temp4 = 0x0000;
temp5 = 0x0000;
temp6 = 0x0000;
for (id = 0; id < (16/2); id++) {
if(pCurrNvRam){
temp = (USHORT) pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
}else
temp = utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
for (i = 0; i < 2; temp >>=8,i++) {
temp2 >>= 1;
temp3 >>= 1;
temp4 >>= 1;
temp5 >>= 1;
temp6 >>= 1;
switch (temp & 0x3)
{
case AUTO_RATE_20: /* Synchronous, 20 mega-transfers/second */
temp6 |= 0x8000; /* Fall through */
case AUTO_RATE_10: /* Synchronous, 10 mega-transfers/second */
temp5 |= 0x8000; /* Fall through */
case AUTO_RATE_05: /* Synchronous, 5 mega-transfers/second */
temp2 |= 0x8000; /* Fall through */
case AUTO_RATE_00: /* Asynchronous */
break;
}
if (temp & DISC_ENABLE_BIT)
temp3 |= 0x8000;
if (temp & WIDE_NEGO_BIT)
temp4 |= 0x8000;
}
}
pCardInfo->si_per_targ_init_sync = temp2;
pCardInfo->si_per_targ_no_disc = temp3;
pCardInfo->si_per_targ_wide_nego = temp4;
pCardInfo->si_per_targ_fast_nego = temp5;
pCardInfo->si_per_targ_ultra_nego = temp6;
if(pCurrNvRam)
i = pCurrNvRam->niSysConf;
else
i = (UCHAR)(utilEERead(ioport, (SYSTEM_CONFIG/2)));
if(pCurrNvRam)
ScamFlg = pCurrNvRam->niScamConf;
else
ScamFlg = (UCHAR) utilEERead(ioport, SCAM_CONFIG/2);
pCardInfo->si_flags = 0x0000;
if (i & 0x01)
pCardInfo->si_flags |= SCSI_PARITY_ENA;
if (!(i & 0x02))
pCardInfo->si_flags |= SOFT_RESET;
if (i & 0x10)
pCardInfo->si_flags |= EXTENDED_TRANSLATION;
if (ScamFlg & SCAM_ENABLED)
pCardInfo->si_flags |= FLAG_SCAM_ENABLED;
if (ScamFlg & SCAM_LEVEL2)
pCardInfo->si_flags |= FLAG_SCAM_LEVEL2;
j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & 0x04) {
j |= SCSI_TERM_ENA_L;
}
WR_HARPOON(ioport+hp_bm_ctrl, j );
j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & 0x08) {
j |= SCSI_TERM_ENA_H;
}
WR_HARPOON(ioport+hp_ee_ctrl, j );
if (!(RD_HARPOON(ioport+hp_page_ctrl) & NARROW_SCSI_CARD))
pCardInfo->si_flags |= SUPPORT_16TAR_32LUN;
pCardInfo->si_card_family = HARPOON_FAMILY;
pCardInfo->si_bustype = BUSTYPE_PCI;
if(pCurrNvRam){
pCardInfo->si_card_model[0] = '9';
switch(pCurrNvRam->niModel & 0x0f){
case MODEL_LT:
pCardInfo->si_card_model[1] = '3';
pCardInfo->si_card_model[2] = '0';
break;
case MODEL_LW:
pCardInfo->si_card_model[1] = '5';
pCardInfo->si_card_model[2] = '0';
break;
case MODEL_DL:
pCardInfo->si_card_model[1] = '3';
pCardInfo->si_card_model[2] = '2';
break;
case MODEL_DW:
pCardInfo->si_card_model[1] = '5';
pCardInfo->si_card_model[2] = '2';
break;
}
}else{
temp = utilEERead(ioport, (MODEL_NUMB_0/2));
pCardInfo->si_card_model[0] = (UCHAR)(temp >> 8);
temp = utilEERead(ioport, (MODEL_NUMB_2/2));
pCardInfo->si_card_model[1] = (UCHAR)(temp & 0x00FF);
pCardInfo->si_card_model[2] = (UCHAR)(temp >> 8);
}
if (pCardInfo->si_card_model[1] == '3')
{
if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= LOW_BYTE_TERM;
}
else if (pCardInfo->si_card_model[2] == '0')
{
temp = RD_HARPOON(ioport+hp_xfer_pad);
WR_HARPOON(ioport+hp_xfer_pad, (temp & ~BIT(4)));
if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= LOW_BYTE_TERM;
WR_HARPOON(ioport+hp_xfer_pad, (temp | BIT(4)));
if (RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7))
pCardInfo->si_flags |= HIGH_BYTE_TERM;
WR_HARPOON(ioport+hp_xfer_pad, temp);
}
else
{
temp = RD_HARPOON(ioport+hp_ee_ctrl);
temp2 = RD_HARPOON(ioport+hp_xfer_pad);
WR_HARPOON(ioport+hp_ee_ctrl, (temp | SEE_CS));
WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
temp3 = 0;
for (i = 0; i < 8; i++)
{
temp3 <<= 1;
if (!(RD_HARPOON(ioport+hp_ee_ctrl) & BIT(7)))
temp3 |= 1;
WR_HARPOON(ioport+hp_xfer_pad, (temp2 & ~BIT(4)));
WR_HARPOON(ioport+hp_xfer_pad, (temp2 | BIT(4)));
}
WR_HARPOON(ioport+hp_ee_ctrl, temp);
WR_HARPOON(ioport+hp_xfer_pad, temp2);
if (!(temp3 & BIT(7)))
pCardInfo->si_flags |= LOW_BYTE_TERM;
if (!(temp3 & BIT(6)))
pCardInfo->si_flags |= HIGH_BYTE_TERM;
}
ARAM_ACCESS(ioport);
for ( i = 0; i < 4; i++ ) {
pCardInfo->si_XlatInfo[i] =
RD_HARPOON(ioport+hp_aramBase+BIOS_DATA_OFFSET+i);
}
/* return with -1 if no sort, else return with
logical card number sorted by BIOS (zero-based) */
pCardInfo->si_relative_cardnum =
(UCHAR)(RD_HARPOON(ioport+hp_aramBase+BIOS_RELATIVE_CARD)-1);
SGRAM_ACCESS(ioport);
s_PhaseTbl[0] = phaseDataOut;
s_PhaseTbl[1] = phaseDataIn;
s_PhaseTbl[2] = phaseIllegal;
s_PhaseTbl[3] = phaseIllegal;
s_PhaseTbl[4] = phaseCommand;
s_PhaseTbl[5] = phaseStatus;
s_PhaseTbl[6] = phaseMsgOut;
s_PhaseTbl[7] = phaseMsgIn;
pCardInfo->si_present = 0x01;
#if defined(BUGBUG)
for (i = 0; i < MAX_CARDS; i++) {
for (id=0; id<debug_size; id++)
debug_int[i][id] = (UCHAR)0x00;
debug_index[i] = 0;
}
#endif
return(0);
}
/*---------------------------------------------------------------------
*
* Function: SccbMgr_config_adapter
*
* Description: Setup adapter for normal operation (hard reset).
*
*---------------------------------------------------------------------*/
#if defined(DOS)
USHORT SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo)
#else
ULONG SccbMgr_config_adapter(PSCCBMGR_INFO pCardInfo)
#endif
{
PSCCBcard CurrCard = NULL;
PNVRamInfo pCurrNvRam;
UCHAR i,j,thisCard, ScamFlg;
USHORT temp,sync_bit_map,id;
#if defined(DOS)
USHORT ioport;
#else
ULONG ioport;
#endif
#if defined(DOS)
ioport = (USHORT)pCardInfo->si_baseaddr;
#else
ioport = pCardInfo->si_baseaddr;
#endif
for(thisCard =0; thisCard <= MAX_CARDS; thisCard++) {
if (thisCard == MAX_CARDS) {
return(FAILURE);
}
if (BL_Card[thisCard].ioPort == ioport) {
CurrCard = &BL_Card[thisCard];
SccbMgrTableInitCard(CurrCard,thisCard);
break;
}
else if (BL_Card[thisCard].ioPort == 0x00) {
BL_Card[thisCard].ioPort = ioport;
CurrCard = &BL_Card[thisCard];
if(mbCards)
for(i = 0; i < mbCards; i++){
if(CurrCard->ioPort == nvRamInfo[i].niBaseAddr)
CurrCard->pNvRamInfo = &nvRamInfo[i];
}
SccbMgrTableInitCard(CurrCard,thisCard);
CurrCard->cardIndex = thisCard;
CurrCard->cardInfo = pCardInfo;
break;
}
}
pCurrNvRam = CurrCard->pNvRamInfo;
if(pCurrNvRam){
ScamFlg = pCurrNvRam->niScamConf;
}
else{
ScamFlg = (UCHAR) utilEERead(ioport, SCAM_CONFIG/2);
}
BusMasterInit(ioport);
XbowInit(ioport, ScamFlg);
#if defined (NO_BIOS_OPTION)
if (DiagXbow(ioport)) return(FAILURE);
if (DiagBusMaster(ioport)) return(FAILURE);
#endif /* No BIOS Option */
autoLoadDefaultMap(ioport);
for (i = 0,id = 0x01; i != pCardInfo->si_id; i++,id <<= 1){}
WR_HARPOON(ioport+hp_selfid_0, id);
WR_HARPOON(ioport+hp_selfid_1, 0x00);
WR_HARPOON(ioport+hp_arb_id, pCardInfo->si_id);
CurrCard->ourId = pCardInfo->si_id;
i = (UCHAR) pCardInfo->si_flags;
if (i & SCSI_PARITY_ENA)
WR_HARPOON(ioport+hp_portctrl_1,(HOST_MODE8 | CHK_SCSI_P));
j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & LOW_BYTE_TERM)
j |= SCSI_TERM_ENA_L;
WR_HARPOON(ioport+hp_bm_ctrl, j);
j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & HIGH_BYTE_TERM)
j |= SCSI_TERM_ENA_H;
WR_HARPOON(ioport+hp_ee_ctrl, j );
if (!(pCardInfo->si_flags & SOFT_RESET)) {
sresb(ioport,thisCard);
scini(thisCard, pCardInfo->si_id, 0);
}
if (pCardInfo->si_flags & POST_ALL_UNDERRRUNS)
CurrCard->globalFlags |= F_NO_FILTER;
if(pCurrNvRam){
if(pCurrNvRam->niSysConf & 0x10)
CurrCard->globalFlags |= F_GREEN_PC;
}
else{
if (utilEERead(ioport, (SYSTEM_CONFIG/2)) & GREEN_PC_ENA)
CurrCard->globalFlags |= F_GREEN_PC;
}
/* Set global flag to indicate Re-Negotiation to be done on all
ckeck condition */
if(pCurrNvRam){
if(pCurrNvRam->niScsiConf & 0x04)
CurrCard->globalFlags |= F_DO_RENEGO;
}
else{
if (utilEERead(ioport, (SCSI_CONFIG/2)) & RENEGO_ENA)
CurrCard->globalFlags |= F_DO_RENEGO;
}
if(pCurrNvRam){
if(pCurrNvRam->niScsiConf & 0x08)
CurrCard->globalFlags |= F_CONLUN_IO;
}
else{
if (utilEERead(ioport, (SCSI_CONFIG/2)) & CONNIO_ENA)
CurrCard->globalFlags |= F_CONLUN_IO;
}
temp = pCardInfo->si_per_targ_no_disc;
for (i = 0,id = 1; i < MAX_SCSI_TAR; i++, id <<= 1) {
if (temp & id)
sccbMgrTbl[thisCard][i].TarStatus |= TAR_ALLOW_DISC;
}
sync_bit_map = 0x0001;
for (id = 0; id < (MAX_SCSI_TAR/2); id++) {
if(pCurrNvRam){
temp = (USHORT) pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
}else
temp = utilEERead(ioport, (USHORT)((SYNC_RATE_TBL/2)+id));
for (i = 0; i < 2; temp >>=8,i++) {
if (pCardInfo->si_per_targ_init_sync & sync_bit_map) {
sccbMgrTbl[thisCard][id*2+i].TarEEValue = (UCHAR)temp;
}
else {
sccbMgrTbl[thisCard][id*2+i].TarStatus |= SYNC_SUPPORTED;
sccbMgrTbl[thisCard][id*2+i].TarEEValue =
(UCHAR)(temp & ~EE_SYNC_MASK);
}
#if defined(WIDE_SCSI)
/* if ((pCardInfo->si_per_targ_wide_nego & sync_bit_map) ||
(id*2+i >= 8)){
*/
if (pCardInfo->si_per_targ_wide_nego & sync_bit_map){
sccbMgrTbl[thisCard][id*2+i].TarEEValue |= EE_WIDE_SCSI;
}
else { /* NARROW SCSI */
sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
}
#else
sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
#endif
sync_bit_map <<= 1;
}
}
WR_HARPOON((ioport+hp_semaphore),
(UCHAR)(RD_HARPOON((ioport+hp_semaphore)) | SCCB_MGR_PRESENT));
#if defined(DOS)
return((USHORT)CurrCard);
#else
return((ULONG)CurrCard);
#endif
}
#else /* end (FW_TYPE==_SCCB_MGR_) */
STATIC s16bits FP_PresenceCheck(PMGR_INFO pMgrInfo)
{
PMGR_ENTRYPNTS pMgr_EntryPnts = &pMgrInfo->mi_Functions;
pMgr_EntryPnts->UCBMgr_probe_adapter = probe_adapter;
pMgr_EntryPnts->UCBMgr_init_adapter = init_adapter;
pMgr_EntryPnts->UCBMgr_start_UCB = SccbMgr_start_sccb;
pMgr_EntryPnts->UCBMgr_build_UCB = build_UCB;
pMgr_EntryPnts->UCBMgr_abort_UCB = SccbMgr_abort_sccb;
pMgr_EntryPnts->UCBMgr_my_int = SccbMgr_my_int;
pMgr_EntryPnts->UCBMgr_isr = SccbMgr_isr;
pMgr_EntryPnts->UCBMgr_scsi_reset = SccbMgr_scsi_reset;
pMgr_EntryPnts->UCBMgr_timer_expired = SccbMgr_timer_expired;
#ifndef NO_IOCTLS
pMgr_EntryPnts->UCBMgr_unload_card = SccbMgr_unload_card;
pMgr_EntryPnts->UCBMgr_save_foreign_state =
SccbMgr_save_foreign_state;
pMgr_EntryPnts->UCBMgr_restore_foreign_state =
SccbMgr_restore_foreign_state;
pMgr_EntryPnts->UCBMgr_restore_native_state =
SccbMgr_restore_native_state;
#endif /*NO_IOCTLS*/
pMgrInfo->mi_SGListFormat=0x01;
pMgrInfo->mi_DataPtrFormat=0x01;
pMgrInfo->mi_MaxSGElements= (u16bits) 0xffffffff;
pMgrInfo->mi_MgrPrivateLen=sizeof(SCCB);
pMgrInfo->mi_PCIVendorID=BL_VENDOR_ID;
pMgrInfo->mi_PCIDeviceID=FP_DEVICE_ID;
pMgrInfo->mi_MgrAttributes= ATTR_IO_MAPPED +
ATTR_PHYSICAL_ADDRESS +
ATTR_VIRTUAL_ADDRESS +
ATTR_OVERLAPPED_IO_IOCTLS_OK;
pMgrInfo->mi_IoRangeLen = 256;
return(0);
}
/*---------------------------------------------------------------------
*
* Function: probe_adapter
*
* Description: Setup and/or Search for cards and return info to caller.
*
*---------------------------------------------------------------------*/
STATIC s32bits probe_adapter(PADAPTER_INFO pAdapterInfo)
{
u16bits temp,temp2,temp3,temp4;
u08bits i,j,id;
#if defined(DOS)
#else
static u08bits first_time = 1;
#endif
BASE_PORT ioport;
PNVRamInfo pCurrNvRam;
ioport = (BASE_PORT)pAdapterInfo->ai_baseaddr;
if (RD_HARPOON(ioport+hp_vendor_id_0) != ORION_VEND_0)
return(1);
if ((RD_HARPOON(ioport+hp_vendor_id_1) != ORION_VEND_1))
return(2);
if ((RD_HARPOON(ioport+hp_device_id_0) != ORION_DEV_0))
return(3);
if ((RD_HARPOON(ioport+hp_device_id_1) != ORION_DEV_1))
return(4);
if (RD_HARPOON(ioport+hp_rev_num) != 0x0f){
/* For new Harpoon then check for sub_device ID LSB
the bits(0-3) must be all ZERO for compatible with
current version of SCCBMgr, else skip this Harpoon
device. */
if (RD_HARPOON(ioport+hp_sub_device_id_0) & 0x0f)
return(5);
}
if (first_time) {
SccbMgrTableInitAll();
first_time = 0;
mbCards = 0;
}
if(RdStack(ioport, 0) != 0x00) {
if(ChkIfChipInitialized(ioport) == FALSE)
{
pCurrNvRam = NULL;
WR_HARPOON(ioport+hp_semaphore, 0x00);
XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
DiagEEPROM(ioport);
}
else
{
if(mbCards < MAX_MB_CARDS) {
pCurrNvRam = &nvRamInfo[mbCards];
mbCards++;
pCurrNvRam->niBaseAddr = ioport;
RNVRamData(pCurrNvRam);
}else
return((int) FAILURE);
}
}else
pCurrNvRam = NULL;
#if defined (NO_BIOS_OPTION)
pCurrNvRam = NULL;
XbowInit(ioport, 0); /*Must Init the SCSI before attempting */
DiagEEPROM(ioport);
#endif /* No BIOS Option */
WR_HARPOON(ioport+hp_clkctrl_0, CLKCTRL_DEFAULT);
WR_HARPOON(ioport+hp_sys_ctrl, 0x00);
if(pCurrNvRam)
pAdapterInfo->ai_id = pCurrNvRam->niAdapId;
else
pAdapterInfo->ai_id = (u08bits)(utilEERead(ioport, (ADAPTER_SCSI_ID/2)) &
(u08bits)0x0FF);
pAdapterInfo->ai_lun = 0x00;
pAdapterInfo->ai_fw_revision[0] = '3';
pAdapterInfo->ai_fw_revision[1] = '1';
pAdapterInfo->ai_fw_revision[2] = '1';
pAdapterInfo->ai_fw_revision[3] = ' ';
pAdapterInfo->ai_NumChannels = 1;
temp2 = 0x0000;
temp3 = 0x0000;
temp4 = 0x0000;
for (id = 0; id < (16/2); id++) {
if(pCurrNvRam){
temp = (USHORT) pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
}else
temp = utilEERead(ioport, (u16bits)((SYNC_RATE_TBL/2)+id));
for (i = 0; i < 2; temp >>=8,i++) {
if ((temp & 0x03) != AUTO_RATE_00) {
temp2 >>= 0x01;
temp2 |= 0x8000;
}
else {
temp2 >>= 0x01;
}
if (temp & DISC_ENABLE_BIT) {
temp3 >>= 0x01;
temp3 |= 0x8000;
}
else {
temp3 >>= 0x01;
}
if (temp & WIDE_NEGO_BIT) {
temp4 >>= 0x01;
temp4 |= 0x8000;
}
else {
temp4 >>= 0x01;
}
}
}
pAdapterInfo->ai_per_targ_init_sync = temp2;
pAdapterInfo->ai_per_targ_no_disc = temp3;
pAdapterInfo->ai_per_targ_wide_nego = temp4;
if(pCurrNvRam)
i = pCurrNvRam->niSysConf;
else
i = (u08bits)(utilEERead(ioport, (SYSTEM_CONFIG/2)));
/*
** interrupts always level-triggered for FlashPoint
*/
pAdapterInfo->ai_stateinfo |= LEVEL_TRIG;
if (i & 0x01)
pAdapterInfo->ai_stateinfo |= SCSI_PARITY_ENA;
if (i & 0x02) /* SCSI Bus reset in AutoSCSI Set ? */
{
if(pCurrNvRam)
{
j = pCurrNvRam->niScamConf;
}
else
{
j = (u08bits) utilEERead(ioport, SCAM_CONFIG/2);
}
if(j & SCAM_ENABLED)
{
if(j & SCAM_LEVEL2)
{
pAdapterInfo->ai_stateinfo |= SCAM2_ENA;
}
else
{
pAdapterInfo->ai_stateinfo |= SCAM1_ENA;
}
}
}
j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & 0x04) {
j |= SCSI_TERM_ENA_L;
pAdapterInfo->ai_stateinfo |= LOW_BYTE_TERM_ENA;
}
WR_HARPOON(ioport+hp_bm_ctrl, j );
j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & 0x08) {
j |= SCSI_TERM_ENA_H;
pAdapterInfo->ai_stateinfo |= HIGH_BYTE_TERM_ENA;
}
WR_HARPOON(ioport+hp_ee_ctrl, j );
if(RD_HARPOON(ioport + hp_page_ctrl) & BIOS_SHADOW)
{
pAdapterInfo->ai_FlashRomSize = 64 * 1024; /* 64k ROM */
}
else
{
pAdapterInfo->ai_FlashRomSize = 32 * 1024; /* 32k ROM */
}
pAdapterInfo->ai_stateinfo |= (FAST20_ENA | TAG_QUEUE_ENA);
if (!(RD_HARPOON(ioport+hp_page_ctrl) & NARROW_SCSI_CARD))
{
pAdapterInfo->ai_attributes |= (WIDE_CAPABLE | FAST20_CAPABLE
| SCAM2_CAPABLE
| TAG_QUEUE_CAPABLE
| SUPRESS_UNDERRRUNS_CAPABLE
| SCSI_PARITY_CAPABLE);
pAdapterInfo->ai_MaxTarg = 16;
pAdapterInfo->ai_MaxLun = 32;
}
else
{
pAdapterInfo->ai_attributes |= (FAST20_CAPABLE | SCAM2_CAPABLE
| TAG_QUEUE_CAPABLE
| SUPRESS_UNDERRRUNS_CAPABLE
| SCSI_PARITY_CAPABLE);
pAdapterInfo->ai_MaxTarg = 8;
pAdapterInfo->ai_MaxLun = 8;
}
pAdapterInfo->ai_product_family = HARPOON_FAMILY;
pAdapterInfo->ai_HBAbustype = BUSTYPE_PCI;
for (i=0;i<CARD_MODEL_NAMELEN;i++)
{
pAdapterInfo->ai_card_model[i]=' '; /* initialize the ai_card_model */
}
if(pCurrNvRam){
pAdapterInfo->ai_card_model[0] = '9';
switch(pCurrNvRam->niModel & 0x0f){
case MODEL_LT:
pAdapterInfo->ai_card_model[1] = '3';
pAdapterInfo->ai_card_model[2] = '0';
break;
case MODEL_LW:
pAdapterInfo->ai_card_model[1] = '5';
pAdapterInfo->ai_card_model[2] = '0';
break;
case MODEL_DL:
pAdapterInfo->ai_card_model[1] = '3';
pAdapterInfo->ai_card_model[2] = '2';
break;
case MODEL_DW:
pAdapterInfo->ai_card_model[1] = '5';
pAdapterInfo->ai_card_model[2] = '2';
break;
}
}else{
temp = utilEERead(ioport, (MODEL_NUMB_0/2));
pAdapterInfo->ai_card_model[0] = (u08bits)(temp >> 8);
temp = utilEERead(ioport, (MODEL_NUMB_2/2));
pAdapterInfo->ai_card_model[1] = (u08bits)(temp & 0x00FF);
pAdapterInfo->ai_card_model[2] = (u08bits)(temp >> 8);
}
pAdapterInfo->ai_FiberProductType = 0;
pAdapterInfo->ai_secondary_range = 0;
for (i=0;i<WORLD_WIDE_NAMELEN;i++)
{
pAdapterInfo->ai_worldwidename[i]='';
}
for (i=0;i<VENDOR_NAMELEN;i++)
{
pAdapterInfo->ai_vendorstring[i]='';
}
pAdapterInfo->ai_vendorstring[0]='B';
pAdapterInfo->ai_vendorstring[1]='U';
pAdapterInfo->ai_vendorstring[2]='S';
pAdapterInfo->ai_vendorstring[3]='L';
pAdapterInfo->ai_vendorstring[4]='O';
pAdapterInfo->ai_vendorstring[5]='G';
pAdapterInfo->ai_vendorstring[6]='I';
pAdapterInfo->ai_vendorstring[7]='C';
for (i=0;i<FAMILY_NAMELEN;i++)
{
pAdapterInfo->ai_AdapterFamilyString[i]='';
}
pAdapterInfo->ai_AdapterFamilyString[0]='F';
pAdapterInfo->ai_AdapterFamilyString[1]='L';
pAdapterInfo->ai_AdapterFamilyString[2]='A';
pAdapterInfo->ai_AdapterFamilyString[3]='S';
pAdapterInfo->ai_AdapterFamilyString[4]='H';
pAdapterInfo->ai_AdapterFamilyString[5]='P';
pAdapterInfo->ai_AdapterFamilyString[6]='O';
pAdapterInfo->ai_AdapterFamilyString[7]='I';
pAdapterInfo->ai_AdapterFamilyString[8]='N';
pAdapterInfo->ai_AdapterFamilyString[9]='T';
ARAM_ACCESS(ioport);
for ( i = 0; i < 4; i++ ) {
pAdapterInfo->ai_XlatInfo[i] =
RD_HARPOON(ioport+hp_aramBase+BIOS_DATA_OFFSET+i);
}
/* return with -1 if no sort, else return with
logical card number sorted by BIOS (zero-based) */
pAdapterInfo->ai_relative_cardnum =
(u08bits)(RD_HARPOON(ioport+hp_aramBase+BIOS_RELATIVE_CARD)-1);
SGRAM_ACCESS(ioport);
s_PhaseTbl[0] = phaseDataOut;
s_PhaseTbl[1] = phaseDataIn;
s_PhaseTbl[2] = phaseIllegal;
s_PhaseTbl[3] = phaseIllegal;
s_PhaseTbl[4] = phaseCommand;
s_PhaseTbl[5] = phaseStatus;
s_PhaseTbl[6] = phaseMsgOut;
s_PhaseTbl[7] = phaseMsgIn;
pAdapterInfo->ai_present = 0x01;
#if defined(BUGBUG)
for (i = 0; i < MAX_CARDS; i++) {
for (id=0; id<debug_size; id++)
debug_int[i][id] = (u08bits)0x00;
debug_index[i] = 0;
}
#endif
return(0);
}
/*---------------------------------------------------------------------
*
* Function: init_adapter, exported to BUDI via UCBMgr_init_adapter entry
*
*
* Description: Setup adapter for normal operation (hard reset).
*
*---------------------------------------------------------------------*/
STATIC CARD_HANDLE init_adapter(PADAPTER_INFO pCardInfo)
{
PSCCBcard CurrCard;
PNVRamInfo pCurrNvRam;
u08bits i,j,thisCard, ScamFlg;
u16bits temp,sync_bit_map,id;
BASE_PORT ioport;
ioport = (BASE_PORT)pCardInfo->ai_baseaddr;
for(thisCard =0; thisCard <= MAX_CARDS; thisCard++) {
if (thisCard == MAX_CARDS) {
return(FAILURE);
}
if (BL_Card[thisCard].ioPort == ioport) {
CurrCard = &BL_Card[thisCard];
SccbMgrTableInitCard(CurrCard,thisCard);
break;
}
else if (BL_Card[thisCard].ioPort == 0x00) {
BL_Card[thisCard].ioPort = ioport;
CurrCard = &BL_Card[thisCard];
if(mbCards)
for(i = 0; i < mbCards; i++){
if(CurrCard->ioPort == nvRamInfo[i].niBaseAddr)
CurrCard->pNvRamInfo = &nvRamInfo[i];
}
SccbMgrTableInitCard(CurrCard,thisCard);
CurrCard->cardIndex = thisCard;
CurrCard->cardInfo = pCardInfo;
break;
}
}
pCurrNvRam = CurrCard->pNvRamInfo;
if(pCurrNvRam){
ScamFlg = pCurrNvRam->niScamConf;
}
else{
ScamFlg = (UCHAR) utilEERead(ioport, SCAM_CONFIG/2);
}
BusMasterInit(ioport);
XbowInit(ioport, ScamFlg);
#if defined (NO_BIOS_OPTION)
if (DiagXbow(ioport)) return(FAILURE);
if (DiagBusMaster(ioport)) return(FAILURE);
#endif /* No BIOS Option */
autoLoadDefaultMap(ioport);
for (i = 0,id = 0x01; i != pCardInfo->ai_id; i++,id <<= 1){}
WR_HARPOON(ioport+hp_selfid_0, id);
WR_HARPOON(ioport+hp_selfid_1, 0x00);
WR_HARPOON(ioport+hp_arb_id, pCardInfo->ai_id);
CurrCard->ourId = (unsigned char) pCardInfo->ai_id;
i = (u08bits) pCardInfo->ai_stateinfo;
if (i & SCSI_PARITY_ENA)
WR_HARPOON(ioport+hp_portctrl_1,(HOST_MODE8 | CHK_SCSI_P));
j = (RD_HARPOON(ioport+hp_bm_ctrl) & ~SCSI_TERM_ENA_L);
if (i & LOW_BYTE_TERM_ENA)
j |= SCSI_TERM_ENA_L;
WR_HARPOON(ioport+hp_bm_ctrl, j);
j = (RD_HARPOON(ioport+hp_ee_ctrl) & ~SCSI_TERM_ENA_H);
if (i & HIGH_BYTE_TERM_ENA)
j |= SCSI_TERM_ENA_H;
WR_HARPOON(ioport+hp_ee_ctrl, j );
if (!(pCardInfo->ai_stateinfo & NO_RESET_IN_INIT)) {
sresb(ioport,thisCard);
scini(thisCard, (u08bits) pCardInfo->ai_id, 0);
}
if (pCardInfo->ai_stateinfo & SUPRESS_UNDERRRUNS_ENA)
CurrCard->globalFlags |= F_NO_FILTER;
if(pCurrNvRam){
if(pCurrNvRam->niSysConf & 0x10)
CurrCard->globalFlags |= F_GREEN_PC;
}
else{
if (utilEERead(ioport, (SYSTEM_CONFIG/2)) & GREEN_PC_ENA)
CurrCard->globalFlags |= F_GREEN_PC;
}
/* Set global flag to indicate Re-Negotiation to be done on all
ckeck condition */
if(pCurrNvRam){
if(pCurrNvRam->niScsiConf & 0x04)
CurrCard->globalFlags |= F_DO_RENEGO;
}
else{
if (utilEERead(ioport, (SCSI_CONFIG/2)) & RENEGO_ENA)
CurrCard->globalFlags |= F_DO_RENEGO;
}
if(pCurrNvRam){
if(pCurrNvRam->niScsiConf & 0x08)
CurrCard->globalFlags |= F_CONLUN_IO;
}
else{
if (utilEERead(ioport, (SCSI_CONFIG/2)) & CONNIO_ENA)
CurrCard->globalFlags |= F_CONLUN_IO;
}
temp = pCardInfo->ai_per_targ_no_disc;
for (i = 0,id = 1; i < MAX_SCSI_TAR; i++, id <<= 1) {
if (temp & id)
sccbMgrTbl[thisCard][i].TarStatus |= TAR_ALLOW_DISC;
}
sync_bit_map = 0x0001;
for (id = 0; id < (MAX_SCSI_TAR/2); id++){
if(pCurrNvRam){
temp = (USHORT) pCurrNvRam->niSyncTbl[id];
temp = ((temp & 0x03) + ((temp << 4) & 0xc0)) +
(((temp << 4) & 0x0300) + ((temp << 8) & 0xc000));
}else
temp = utilEERead(ioport, (u16bits)((SYNC_RATE_TBL/2)+id));
for (i = 0; i < 2; temp >>=8,i++){
if (pCardInfo->ai_per_targ_init_sync & sync_bit_map){
sccbMgrTbl[thisCard][id*2+i].TarEEValue = (u08bits)temp;
}
else {
sccbMgrTbl[thisCard][id*2+i].TarStatus |= SYNC_SUPPORTED;
sccbMgrTbl[thisCard][id*2+i].TarEEValue =
(u08bits)(temp & ~EE_SYNC_MASK);
}
#if defined(WIDE_SCSI)
/* if ((pCardInfo->ai_per_targ_wide_nego & sync_bit_map) ||
(id*2+i >= 8)){
*/
if (pCardInfo->ai_per_targ_wide_nego & sync_bit_map){
sccbMgrTbl[thisCard][id*2+i].TarEEValue |= EE_WIDE_SCSI;
}
else { /* NARROW SCSI */
sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
}
#else
sccbMgrTbl[thisCard][id*2+i].TarStatus |= WIDE_NEGOCIATED;
#endif
sync_bit_map <<= 1;
}
}
pCardInfo->ai_SGListFormat=0x01;
pCardInfo->ai_DataPtrFormat=0x01;
pCardInfo->ai_AEN_mask &= SCSI_RESET_COMPLETE;
WR_HARPOON((ioport+hp_semaphore),
(u08bits)(RD_HARPOON((ioport+hp_semaphore)) | SCCB_MGR_PRESENT));
return((u32bits)CurrCard);
}
/*---------------------------------------------------------------------
*
* Function: build_ucb, exported to BUDI via UCBMgr_build_ucb entry
*
* Description: prepare fw portion of ucb. do not start, resource not guaranteed
* so don't manipulate anything that's derived from states which
* may change
*
*---------------------------------------------------------------------*/
void build_UCB(CARD_HANDLE pCurrCard, PUCB p_ucb)
{
u08bits thisCard;
u08bits i,j;
PSCCB p_sccb;
thisCard = ((PSCCBcard) pCurrCard)->cardIndex;
p_sccb=(PSCCB)p_ucb->UCB_MgrPrivatePtr;
p_sccb->Sccb_ucb_ptr=p_ucb;
switch (p_ucb->UCB_opcode & (OPC_DEVICE_RESET+OPC_XFER_SG+OPC_CHK_RESIDUAL))
{
case OPC_DEVICE_RESET:
p_sccb->OperationCode=RESET_COMMAND;
break;
case OPC_XFER_SG:
p_sccb->OperationCode=SCATTER_GATHER_COMMAND;
break;
case OPC_XFER_SG+OPC_CHK_RESIDUAL:
p_sccb->OperationCode=RESIDUAL_SG_COMMAND;
break;
case OPC_CHK_RESIDUAL:
p_sccb->OperationCode=RESIDUAL_COMMAND;
break;
default:
p_sccb->OperationCode=SCSI_INITIATOR_COMMAND;
break;
}
if (p_ucb->UCB_opcode & OPC_TQ_ENABLE)
{
p_sccb->ControlByte = (u08bits)((p_ucb->UCB_opcode & OPC_TQ_MASK)>>2) | F_USE_CMD_Q;
}
else
{
p_sccb->ControlByte = 0;
}
p_sccb->CdbLength = (u08bits)p_ucb->UCB_cdblen;
if (p_ucb->UCB_opcode & OPC_NO_AUTO_SENSE)
{
p_sccb->RequestSenseLength = 0;
}
else
{
p_sccb->RequestSenseLength = (unsigned char) p_ucb->UCB_senselen;
}
if (p_ucb->UCB_opcode & OPC_XFER_SG)
{
p_sccb->DataPointer=p_ucb->UCB_virt_dataptr;
p_sccb->DataLength = (((u32bits)p_ucb->UCB_NumSgElements)<<3);
}
else
{
p_sccb->DataPointer=p_ucb->UCB_phys_dataptr;
p_sccb->DataLength=p_ucb->UCB_datalen;
};
p_sccb->HostStatus=0;
p_sccb->TargetStatus=0;
p_sccb->TargID=(unsigned char)p_ucb->UCB_targid;
p_sccb->Lun=(unsigned char) p_ucb->UCB_lun;
p_sccb->SccbIOPort=((PSCCBcard)pCurrCard)->ioPort;
j=p_ucb->UCB_cdblen;
for (i=0;i<j;i++)
{
p_sccb->Cdb[i] = p_ucb->UCB_cdb[i];
}
p_sccb->SensePointer=p_ucb->UCB_phys_senseptr;
sinits(p_sccb,thisCard);
}
#ifndef NO_IOCTLS
/*---------------------------------------------------------------------
*
* Function: GetDevSyncRate
*
*---------------------------------------------------------------------*/
STATIC int GetDevSyncRate(PSCCBcard pCurrCard,PUCB p_ucb)
{
struct _SYNC_RATE_INFO * pSyncStr;
PSCCBMgr_tar_info currTar_Info;
BASE_PORT ioport;
u08bits scsiID, j;
#if (FW_TYPE != _SCCB_MGR_)
if( p_ucb->UCB_targid >= pCurrCard->cardInfo->ai_MaxTarg )
{
return(1);
}
#endif
ioport = pCurrCard->ioPort;
pSyncStr = (struct _SYNC_RATE_INFO *) p_ucb->UCB_virt_dataptr;
scsiID = (u08bits) p_ucb->UCB_targid;
currTar_Info = &sccbMgrTbl[pCurrCard->cardIndex][scsiID];
j = currTar_Info->TarSyncCtrl;
switch (currTar_Info->TarEEValue & EE_SYNC_MASK)
{
case EE_SYNC_ASYNC:
pSyncStr->RequestMegaXferRate = 0x00;
break;
case EE_SYNC_5MB:
pSyncStr->RequestMegaXferRate = (j & NARROW_SCSI) ? 50 : 100;
break;
case EE_SYNC_10MB:
pSyncStr->RequestMegaXferRate = (j & NARROW_SCSI) ? 100 : 200;
break;
case EE_SYNC_20MB:
pSyncStr->RequestMegaXferRate = (j & NARROW_SCSI) ? 200 : 400;
break;
}
switch ((j >> 5) & 0x07)
{
case 0x00:
if((j & 0x07) == 0x00)
{
pSyncStr->ActualMegaXferRate = 0x00; /* Async Mode */
}
else
{
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 200 : 400;
}
break;
case 0x01:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 100 : 200;
break;
case 0x02:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 66 : 122;
break;
case 0x03:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 50 : 100;
break;
case 0x04:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 40 : 80;
break;
case 0x05:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 33 : 66;
break;
case 0x06:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 28 : 56;
break;
case 0x07:
pSyncStr->ActualMegaXferRate = (j & NARROW_SCSI) ? 25 : 50;
break;
}
pSyncStr->NegotiatedOffset = j & 0x0f;
return(0);
}
/*---------------------------------------------------------------------
*
* Function: SetDevSyncRate
*
*---------------------------------------------------------------------*/
STATIC int SetDevSyncRate(PSCCBcard pCurrCard, PUCB p_ucb)
{
struct _SYNC_RATE_INFO * pSyncStr;
PSCCBMgr_tar_info currTar_Info;
BASE_PORT ioPort;
u08bits scsiID, i, j, syncVal;
u16bits syncOffset, actualXferRate;
union {
u08bits tempb[2];
u16bits tempw;
}temp2;
#if (FW_TYPE != _SCCB_MGR_)
if( p_ucb->UCB_targid >= pCurrCard->cardInfo->ai_MaxTarg )
{
return(1);
}
#endif
ioPort = pCurrCard->ioPort;
pSyncStr = (struct _SYNC_RATE_INFO *) p_ucb->UCB_virt_dataptr;
scsiID = (u08bits) p_ucb->UCB_targid;
currTar_Info = &sccbMgrTbl[pCurrCard->cardIndex][scsiID];
i = RD_HARPOON(ioPort+hp_xfer_pad); /* Save current value */
WR_HARPOON(ioPort+hp_xfer_pad, (i | ID_UNLOCK));
WR_HARPOON(ioPort+hp_select_id, ((scsiID << 4) | scsiID));
j = RD_HARPOON(ioPort+hp_synctarg_0);
WR_HARPOON(ioPort+hp_xfer_pad, i); /* restore value */
actualXferRate = pSyncStr->ActualMegaXferRate;
if(!(j & NARROW_SCSI))
{
actualXferRate <<= 1;
}
if(actualXferRate == 0x00)
{
syncVal = EE_SYNC_ASYNC; /* Async Mode */
}
if(actualXferRate == 0x0200)
{
syncVal = EE_SYNC_20MB; /* 20/40 MB Mode */
}
if(actualXferRate > 0x0050 && actualXferRate < 0x0200 )
{
syncVal = EE_SYNC_10MB; /* 10/20 MB Mode */
}
else
{
syncVal = EE_SYNC_5MB; /* 5/10 MB Mode */
}
if(currTar_Info->TarEEValue && EE_SYNC_MASK == syncVal)
return(0);
currTar_Info->TarEEValue = (currTar_Info->TarEEValue & !EE_SYNC_MASK)
| syncVal;
syncOffset = (SYNC_RATE_TBL + scsiID) / 2;
temp2.tempw = utilEERead(ioPort, syncOffset);
if(scsiID & 0x01)
{
temp2.tempb[0] = (temp2.tempb[0] & !EE_SYNC_MASK) | syncVal;
}
else
{
temp2.tempb[1] = (temp2.tempb[1] & !EE_SYNC_MASK) | syncVal;
}
utilEEWriteOnOff(ioPort, 1);
utilEEWrite(ioPort, temp2.tempw, syncOffset);
utilEEWriteOnOff(ioPort, 0);
UpdateCheckSum(ioPort);
return(0);
}
/*---------------------------------------------------------------------
*
* Function: GetDevWideMode
*
*---------------------------------------------------------------------*/
int GetDevWideMode(PSCCBcard pCurrCard,PUCB p_ucb)
{
u08bits *pData;
pData = (u08bits *)p_ucb->UCB_virt_dataptr;
if(sccbMgrTbl[pCurrCard->cardIndex][p_ucb->UCB_targid].TarEEValue
& EE_WIDE_SCSI)
{
*pData = 1;
}
else
{
*pData = 0;
}
return(0);
}
/*---------------------------------------------------------------------
*
* Function: SetDevWideMode
*
*---------------------------------------------------------------------*/
int SetDevWideMode(PSCCBcard pCurrCard,PUCB p_ucb)
{
u08bits *pData;
PSCCBMgr_tar_info currTar_Info;
BASE_PORT ioPort;
u08bits scsiID, scsiWideMode;
u16bits syncOffset;
union {
u08bits tempb[2];
u16bits tempw;
}temp2;
#if (FW_TYPE != _SCCB_MGR_)
if( !(pCurrCard->cardInfo->ai_attributes & WIDE_CAPABLE) )
{
return(1);
}
if( p_ucb->UCB_targid >= pCurrCard->cardInfo->ai_MaxTarg )
{
return(1);
}
#endif
ioPort = pCurrCard->ioPort;
pData = (u08bits *)p_ucb->UCB_virt_dataptr;
scsiID = (u08bits) p_ucb->UCB_targid;
currTar_Info = &sccbMgrTbl[pCurrCard->cardIndex][scsiID];
if(*pData)
{
if(currTar_Info->TarEEValue & EE_WIDE_SCSI)
{
return(0);
}
else
{
scsiWideMode = EE_WIDE_SCSI;
}
}
else
{
if(!currTar_Info->TarEEValue & EE_WIDE_SCSI)
{
return(0);
}
else
{
scsiWideMode = 0;
}
}
currTar_Info->TarEEValue = (currTar_Info->TarEEValue & !EE_WIDE_SCSI)
| scsiWideMode;
syncOffset = (SYNC_RATE_TBL + scsiID) / 2;
temp2.tempw = utilEERead(ioPort, syncOffset);
if(scsiID & 0x01)
{
temp2.tempb[0] = (temp2.tempb[0] & !EE_WIDE_SCSI) | scsiWideMode;
}
else
{
temp2.tempb[1] = (temp2.tempb[1] & !EE_WIDE_SCSI) | scsiWideMode;
}
utilEEWriteOnOff(ioPort, 1);
utilEEWrite(ioPort, temp2.tempw, syncOffset);
utilEEWriteOnOff(ioPort, 0);
UpdateCheckSum(ioPort);
return(0);
}
/*---------------------------------------------------------------------
*
* Function: ReadNVRam
*
*---------------------------------------------------------------------*/
void ReadNVRam(PSCCBcard pCurrCard,PUCB p_ucb)
{
u08bits *pdata;
u16bits i,numwrds,numbytes,offset,temp;
u08bits OneMore = FALSE;
#if defined(DOS)
u16bits ioport;
#else
u32bits ioport;
#endif
numbytes = (u16bits) p_ucb->UCB_datalen;
ioport = pCurrCard->ioPort;
pdata = (u08bits *) p_ucb->UCB_virt_dataptr;
offset = (u16bits) (p_ucb->UCB_IOCTLParams[0]);
if (offset & 0x1)
{
*((u16bits*) pdata) = utilEERead(ioport,(u16bits)((offset - 1) / 2)); /* 16 bit read */
*pdata = *(pdata + 1);
++offset;
++pdata;
--numbytes;
}
numwrds = numbytes / 2;
if (numbytes & 1)
OneMore = TRUE;
for (i = 0; i < numwrds; i++)
{
*((u16bits*) pdata) = utilEERead(ioport,(u16bits)(offset / 2));
pdata += 2;
offset += 2;
}
if (OneMore)
{
--pdata;
-- offset;
temp = utilEERead(ioport,(u16bits)(offset / 2));
*pdata = (u08bits) (temp);
}
} /* end proc ReadNVRam */
/*---------------------------------------------------------------------
*
* Function: WriteNVRam
*
*---------------------------------------------------------------------*/
void WriteNVRam(PSCCBcard pCurrCard,PUCB p_ucb)
{
u08bits *pdata;
u16bits i,numwrds,numbytes,offset, eeprom_end;
u08bits OneMore = FALSE;
union {
u08bits tempb[2];
u16bits tempw;
} temp2;
#if defined(DOS)
u16bits ioport;
#else
u32bits ioport;
#endif
numbytes = (u16bits) p_ucb->UCB_datalen;
ioport = pCurrCard->ioPort;
pdata = (u08bits *) p_ucb->UCB_virt_dataptr;
offset = (u16bits) (p_ucb->UCB_IOCTLParams[0]);
if (RD_HARPOON(ioport+hp_page_ctrl) & NARROW_SCSI_CARD)
eeprom_end = 512;
else
eeprom_end = 768;
if(offset > eeprom_end)
return;
if((offset + numbytes) > eeprom_end)
numbytes = eeprom_end - offset;
utilEEWriteOnOff(ioport,1); /* Enable write access to the EEPROM */
if (offset & 0x1)
{
temp2.tempw = utilEERead(ioport,(u16bits)((offset - 1) / 2)); /* 16 bit read */
temp2.tempb[1] = *pdata;
utilEEWrite(ioport, temp2.tempw, (u16bits)((offset -1) / 2));
*pdata = *(pdata + 1);
++offset;
++pdata;
--numbytes;
}
numwrds = numbytes / 2;
if (numbytes & 1)
OneMore = TRUE;
for (i = 0; i < numwrds; i++)
{
utilEEWrite(ioport, *((pu16bits)pdata),(u16bits)(offset / 2));
pdata += 2;
offset += 2;
}
if (OneMore)
{
temp2.tempw = utilEERead(ioport,(u16bits)(offset / 2));
temp2.tempb[0] = *pdata;
utilEEWrite(ioport, temp2.tempw, (u16bits)(offset / 2));
}
utilEEWriteOnOff(ioport,0); /* Turn off write access */
UpdateCheckSum((u32bits)ioport);
} /* end proc WriteNVRam */
/*---------------------------------------------------------------------
*
* Function: UpdateCheckSum
*
* Description: Update Check Sum in EEPROM
*
*---------------------------------------------------------------------*/
void UpdateCheckSum(u32bits baseport)
{
USHORT i,sum_data, eeprom_end;
sum_data = 0x0000;
if (RD_HARPOON(baseport+hp_page_ctrl) & NARROW_SCSI_CARD)
eeprom_end = 512;
else
eeprom_end = 768;
for (i = 1; i < eeprom_end/2; i++)
{
sum_data += utilEERead(baseport, i);
}
utilEEWriteOnOff(baseport,1); /* Enable write access to the EEPROM */
utilEEWrite(baseport, sum_data, EEPROM_CHECK_SUM/2);
utilEEWriteOnOff(baseport,0); /* Turn off write access */
}
void SccbMgr_save_foreign_state(PADAPTER_INFO pAdapterInfo)
{
}
void SccbMgr_restore_foreign_state(CARD_HANDLE pCurrCard)
{
}
void SccbMgr_restore_native_state(CARD_HANDLE pCurrCard)
{
}
#endif /* NO_IOCTLS */