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cs4281m.c：源码内容

/*******************************************************************************
*
* "cs4281m.c" -- Cirrus Logic-Crystal CS4281 linux audio driver.
*
* -- adapted from drivers by Thomas Sailer,
* -- but don't bug him; Problems should go to:
* -- tom woller (twoller@crystal.cirrus.com) or
* (pcaudio@crystal.cirrus.com).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Module command line parameters:
* none
*
* Supported devices:
* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
* /dev/midi simple MIDI UART interface, no ioctl
*
* Modification History
* 08/20/00 trw - silence and no stopping DAC until release
* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
* 09/18/00 trw - added 16bit only record with conversion
* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
* capture/playback rates)
* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
* libOSSm.so)
* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
* 11/03/00 trw - fixed interrupt loss/stutter, added debug.
* 11/10/00 bkz - added __devinit to cs4281_hw_init()
* 11/10/00 trw - fixed SMP and capture spinlock hang.
* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
* 12/08/00 trw - added PM support.
* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
* defaultorder-100 as power of 2 for the buffer size. example:
* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
* 04/02/01 trw - reworked the includes, so kgdb wouldn't get confused.
* 04/17/01 trw - added ifdef CONFIG_PM for 2.4.x non-pm kernels. static pmprint.
* 04/19/01 trw - reworked all of the wrapper macros to keep native 2.4.x code
* predominate in the driver.
* 07/01/01 trw - added ability to modify the record source mask to alleviate
* problems with toshiba systems. also, check for toshiba
* system to set default up properly.
* 11/12/01 trw - removed cs4281_update_ptr() in the polling interface code.
* returning with only a few bytes available in the write buffer
* seems to cause some problems with some apps (xmms OSS plugin).
* Also, fixed bug in cs4281_update_ptr() code to wakeup when
* 1/2 buffer is empty, not when completely full.
*
*******************************************************************************/
/* uncomment the following line to disable building PM support into the driver */
//#define NOT_CS4281_PM 1
#include <linux/list.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/ioport.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/sound.h>
#include <linux/slab.h>
#include <linux/soundcard.h>
#include <linux/pci.h>
#include <linux/bitops.h>
#include <asm/io.h>
#include <asm/dma.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/smp_lock.h>
#include <linux/wrapper.h>
#include <asm/uaccess.h>
#include <asm/hardirq.h>
#include "cs4281_hwdefs.h"
EXPORT_NO_SYMBOLS;
struct cs4281_state;
int cs4281_suspend(struct cs4281_state *s);
int cs4281_resume(struct cs4281_state *s);
#include "cs4281_wrapper.h"
#include "cs4281pm-24.h"
static void stop_dac(struct cs4281_state *s);
static void stop_adc(struct cs4281_state *s);
static void start_dac(struct cs4281_state *s);
static void start_adc(struct cs4281_state *s);
#undef OSS_DOCUMENTED_MIXER_SEMANTICS
// ---------------------------------------------------------------------
#ifndef PCI_VENDOR_ID_CIRRUS
#define PCI_VENDOR_ID_CIRRUS 0x1013
#endif
#ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
#define PCI_DEVICE_ID_CRYSTAL_CS4281 0x6005
#endif
#ifndef SS_ID_TOSHIBA_1640CDT
#define SS_ID_TOSHIBA_1640CDT 0xff00
#endif
#ifndef PCI_VENDOR_ID_TOSHIBA
#define PCI_VENDOR_ID_TOSHIBA 0x1179
#endif
#define CS4281_MAGIC ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
#define CS4281_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
#define CS4281_BA0_CPWR_DEFAULT 0x4281
/* buffer order determines the size of the dma buffer for the driver.
* under Linux, a smaller buffer allows more responsiveness from many of the
* applications (e.g. games). A larger buffer allows some of the apps (esound)
* to not underrun the dma buffer as easily. As default, use 32k (order=3)
* rather than 64k as some of the games work more responsively.
* (2^N) * PAGE_SIZE = allocated buffer size
*
* also added fractional "defaultorder" inputs. if >100 then use
* defaultorder-100 as power of 2 for the buffer size. example:
* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
* games are even MORE responsive now, but prone to underruns.
*/
static unsigned long defaultorder = 3;
MODULE_PARM(defaultorder, "i");
/*
* use this module parm to invalidate recording sources
* as on some machines (Toshiba Satellites... again) setting to LINE
* causes an error and some of the mixers (gmix) to not load.
*/
static unsigned long recsrc_invalid = 0;
MODULE_PARM(recsrc_invalid, "i");
//
// Turn on/off debugging compilation by commenting out "#define CSDEBUG"
//
#define CSDEBUG 1
#if CSDEBUG
#define CSDEBUG_INTERFACE 1
#else
#undef CSDEBUG_INTERFACE
#endif
//
// cs_debugmask areas
//
#define CS_INIT 0x00000001 // initialization and probe functions
#define CS_ERROR 0x00000002 // tmp debugging bit placeholder
#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
#define CS_FUNCTION 0x00000008 // enter/leave functions
#define CS_WAVE_WRITE 0x00000010 // write information for wave
#define CS_WAVE_READ 0x00000020 // read information for wave
#define CS_MIDI_WRITE 0x00000040 // write information for midi
#define CS_MIDI_READ 0x00000080 // read information for midi
#define CS_MPU401_WRITE 0x00000100 // write information for mpu401
#define CS_MPU401_READ 0x00000200 // read information for mpu401
#define CS_OPEN 0x00000400 // all open functions in the driver
#define CS_RELEASE 0x00000800 // all release functions in the driver
#define CS_PARMS 0x00001000 // functional and operational parameters
#define CS_IOCTL 0x00002000 // ioctl (non-mixer)
#define CS_PM 0x00004000 // power management
#define CS_TMP 0x10000000 // tmp debug mask bit
#define CS_IOCTL_CMD_SUSPEND 0x1 // suspend
#define CS_IOCTL_CMD_RESUME 0x2 // resume
//
// CSDEBUG is usual mode is set to 1, then use the
// cs_debuglevel and cs_debugmask to turn on or off debugging.
// Debug level of 1 has been defined to be kernel errors and info
// that should be printed on any released driver.
//
#if CSDEBUG
#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
#else
#define CS_DBGOUT(mask,level,x)
#endif
#if CSDEBUG
static unsigned long cs_debuglevel = 1; // levels range from 1-9
static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
MODULE_PARM(cs_debuglevel, "i");
MODULE_PARM(cs_debugmask, "i");
#endif
#define CS_TRUE 1
#define CS_FALSE 0
// MIDI buffer sizes
#define MIDIINBUF 500
#define MIDIOUTBUF 500
#define FMODE_MIDI_SHIFT 3
#define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
#define CS4281_MAJOR_VERSION 1
#define CS4281_MINOR_VERSION 30
#ifdef __ia64__
#define CS4281_ARCH 64 //architecture key
#else
#define CS4281_ARCH 32 //architecture key
#endif
#define CS_TYPE_ADC 0
#define CS_TYPE_DAC 1
static const char invalid_magic[] =
KERN_CRIT "cs4281: invalid magic valuen";
#define VALIDATE_STATE(s)
({
if (!(s) || (s)->magic != CS4281_MAGIC) {
printk(invalid_magic);
return -ENXIO;
}
})
struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
struct cs4281_state {
// magic
unsigned int magic;
u16 ss_id, ss_vendor; /* subsystem and vendor IDs from pci space */
// we keep the cards in a linked list
struct cs4281_state *next;
// pcidev is needed to turn off the DDMA controller at driver shutdown
struct pci_dev *pcidev;
struct list_head list;
// soundcore stuff
int dev_audio;
int dev_mixer;
int dev_midi;
// hardware resources
unsigned int pBA0phys, pBA1phys;
char *pBA0, *pBA1;
unsigned int irq;
unsigned recsrc;
// mixer registers
struct {
unsigned short vol[10];
unsigned int recsrc;
unsigned int modcnt;
unsigned short micpreamp;
} mix;
// wave stuff
struct properties {
unsigned fmt;
unsigned fmt_original; // original requested format
unsigned channels;
unsigned rate;
unsigned char clkdiv;
} prop_dac, prop_adc;
unsigned conversion:1; // conversion from 16 to 8 bit in progress
void *tmpbuff; // tmp buffer for sample conversions
unsigned ena;
spinlock_t lock;
struct semaphore open_sem;
struct semaphore open_sem_adc;
struct semaphore open_sem_dac;
mode_t open_mode;
wait_queue_head_t open_wait;
wait_queue_head_t open_wait_adc;
wait_queue_head_t open_wait_dac;
dma_addr_t dmaaddr_tmpbuff;
unsigned buforder_tmpbuff; // Log base 2 of 'rawbuf' size in bytes..
struct dmabuf {
void *rawbuf; // Physical address of
dma_addr_t dmaaddr;
unsigned buforder; // Log base 2 of 'rawbuf' size in bytes..
unsigned numfrag; // # of 'fragments' in the buffer.
unsigned fragshift; // Log base 2 of fragment size.
unsigned hwptr, swptr;
unsigned total_bytes; // # bytes process since open.
unsigned blocks; // last returned blocks value GETOPTR
unsigned wakeup; // interrupt occurred on block
int count;
unsigned underrun; // underrun flag
unsigned error; // over/underrun
wait_queue_head_t wait;
// redundant, but makes calculations easier
unsigned fragsize; // 2**fragshift..
unsigned dmasize; // 2**buforder.
unsigned fragsamples;
// OSS stuff
unsigned mapped:1; // Buffer mapped in cs4281_mmap()?
unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
unsigned endcleared:1;
unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
unsigned ossfragshift;
int ossmaxfrags;
unsigned subdivision;
} dma_dac, dma_adc;
// midi stuff
struct {
unsigned ird, iwr, icnt;
unsigned ord, owr, ocnt;
wait_queue_head_t iwait;
wait_queue_head_t owait;
struct timer_list timer;
unsigned char ibuf[MIDIINBUF];
unsigned char obuf[MIDIOUTBUF];
} midi;
#ifndef NOT_CS4281_PM
struct cs4281_pm pm;
struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
#endif
};
#if CSDEBUG
// DEBUG ROUTINES
#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
#define SOUND_MIXER_CS_APM _SIOWR('M',124, int)
static void cs_printioctl(unsigned int x)
{
unsigned int i;
unsigned char vidx;
// Index of mixtable1[] member is Device ID
// and must be <= SOUND_MIXER_NRDEVICES.
// Value of array member is index into s->mix.vol[]
static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
[SOUND_MIXER_PCM] = 1, // voice
[SOUND_MIXER_LINE1] = 2, // AUX
[SOUND_MIXER_CD] = 3, // CD
[SOUND_MIXER_LINE] = 4, // Line
[SOUND_MIXER_SYNTH] = 5, // FM
[SOUND_MIXER_MIC] = 6, // Mic
[SOUND_MIXER_SPEAKER] = 7, // Speaker
[SOUND_MIXER_RECLEV] = 8, // Recording level
[SOUND_MIXER_VOLUME] = 9 // Master Volume
};
switch (x) {
case SOUND_MIXER_CS_GETDBGMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_GETDBGMASK:n"));
break;
case SOUND_MIXER_CS_GETDBGLEVEL:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_GETDBGLEVEL:n"));
break;
case SOUND_MIXER_CS_SETDBGMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_SETDBGMASK:n"));
break;
case SOUND_MIXER_CS_SETDBGLEVEL:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_CS_SETDBGLEVEL:n"));
break;
case OSS_GETVERSION:
CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:n"));
break;
case SNDCTL_DSP_SYNC:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:n"));
break;
case SNDCTL_DSP_SETDUPLEX:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:n"));
break;
case SNDCTL_DSP_GETCAPS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:n"));
break;
case SNDCTL_DSP_RESET:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:n"));
break;
case SNDCTL_DSP_SPEED:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:n"));
break;
case SNDCTL_DSP_STEREO:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:n"));
break;
case SNDCTL_DSP_CHANNELS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:n"));
break;
case SNDCTL_DSP_GETFMTS:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:n"));
break;
case SNDCTL_DSP_SETFMT:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:n"));
break;
case SNDCTL_DSP_POST:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:n"));
break;
case SNDCTL_DSP_GETTRIGGER:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:n"));
break;
case SNDCTL_DSP_SETTRIGGER:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:n"));
break;
case SNDCTL_DSP_GETOSPACE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:n"));
break;
case SNDCTL_DSP_GETISPACE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:n"));
break;
case SNDCTL_DSP_NONBLOCK:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:n"));
break;
case SNDCTL_DSP_GETODELAY:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:n"));
break;
case SNDCTL_DSP_GETIPTR:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:n"));
break;
case SNDCTL_DSP_GETOPTR:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:n"));
break;
case SNDCTL_DSP_GETBLKSIZE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:n"));
break;
case SNDCTL_DSP_SETFRAGMENT:
CS_DBGOUT(CS_IOCTL, 4,
printk("SNDCTL_DSP_SETFRAGMENT:n"));
break;
case SNDCTL_DSP_SUBDIVIDE:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:n"));
break;
case SOUND_PCM_READ_RATE:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:n"));
break;
case SOUND_PCM_READ_CHANNELS:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_PCM_READ_CHANNELS:n"));
break;
case SOUND_PCM_READ_BITS:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:n"));
break;
case SOUND_PCM_WRITE_FILTER:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_PCM_WRITE_FILTER:n"));
break;
case SNDCTL_DSP_SETSYNCRO:
CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:n"));
break;
case SOUND_PCM_READ_FILTER:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:n"));
break;
case SOUND_MIXER_PRIVATE1:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:n"));
break;
case SOUND_MIXER_PRIVATE2:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:n"));
break;
case SOUND_MIXER_PRIVATE3:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:n"));
break;
case SOUND_MIXER_PRIVATE4:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:n"));
break;
case SOUND_MIXER_PRIVATE5:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:n"));
break;
case SOUND_MIXER_INFO:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:n"));
break;
case SOUND_OLD_MIXER_INFO:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:n"));
break;
default:
switch (_IOC_NR(x)) {
case SOUND_MIXER_VOLUME:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_VOLUME:n"));
break;
case SOUND_MIXER_SPEAKER:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_SPEAKER:n"));
break;
case SOUND_MIXER_RECLEV:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECLEV:n"));
break;
case SOUND_MIXER_MIC:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_MIC:n"));
break;
case SOUND_MIXER_SYNTH:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_SYNTH:n"));
break;
case SOUND_MIXER_RECSRC:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECSRC:n"));
break;
case SOUND_MIXER_DEVMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_DEVMASK:n"));
break;
case SOUND_MIXER_RECMASK:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_RECMASK:n"));
break;
case SOUND_MIXER_STEREODEVS:
CS_DBGOUT(CS_IOCTL, 4,
printk("SOUND_MIXER_STEREODEVS:n"));
break;
case SOUND_MIXER_CAPS:
CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:n"));
break;
default:
i = _IOC_NR(x);
if (i >= SOUND_MIXER_NRDEVICES
|| !(vidx = mixtable1[i])) {
CS_DBGOUT(CS_IOCTL, 4, printk
("UNKNOWN IOCTL: 0x%.8x NR=%dn",
x, i));
} else {
CS_DBGOUT(CS_IOCTL, 4, printk
("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%dn",
x, i));
}
break;
}
}
}
#endif
static int prog_dmabuf_adc(struct cs4281_state *s);
static void prog_codec(struct cs4281_state *s, unsigned type);
// ---------------------------------------------------------------------
//
// Hardware Interfaces For the CS4281
//
//******************************************************************************
// "delayus()-- Delay for the specified # of microseconds.
//******************************************************************************
static void delayus(struct cs4281_state *s, u32 delay)
{
u32 j;
if ((delay > 9999)
#ifndef NOT_CS4281_PM
&& (s->pm.flags & CS4281_PM_IDLE))
#else
)
#endif
{
j = (delay * HZ) / 1000000; /* calculate delay in jiffies */
if (j < 1)
j = 1; /* minimum one jiffy. */
current->state = TASK_UNINTERRUPTIBLE;
schedule_timeout(j);
} else
udelay(delay);
return;
}
//******************************************************************************
// "cs4281_read_ac97" -- Reads a word from the specified location in the
// CS4281's address space(based on the BA0 register).
//
// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
// 0h for reads.
// 3. Write ACCTL = Control Register = 460h for initiating the write
// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
// 5. if DCV not cleared, break and return error
// 6. Read ACSTS = Status Register = 464h, check VSTS bit
//****************************************************************************
static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
u32 * value)
{
u32 count, status;
// Make sure that there is not data sitting
// around from a previous uncompleted access.
// ACSDA = Status Data Register = 47Ch
status = readl(card->pBA0 + BA0_ACSDA);
// Setup the AC97 control registers on the CS4281 to send the
// appropriate command to the AC97 to perform the read.
// ACCAD = Command Address Register = 46Ch
// ACCDA = Command Data Register = 470h
// ACCTL = Control Register = 460h
// bit DCV - will clear when process completed
// bit CRW - Read command
// bit VFRM - valid frame enabled
// bit ESYN - ASYNC generation enabled
// Get the actual AC97 register from the offset
writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
writel(0, card->pBA0 + BA0_ACCDA);
writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
card->pBA0 + BA0_ACCTL);
// Wait for the read to occur.
for (count = 0; count < 100; count++) {
// First, we want to wait for a short time.
udelay(25);
// Now, check to see if the read has completed.
// ACCTL = 460h, DCV should be reset by now and 460h = 17h
if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
break;
}
// Make sure the read completed.
if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
return 1;
// Wait for the valid status bit to go active.
for (count = 0; count < 100; count++) {
// Read the AC97 status register.
// ACSTS = Status Register = 464h
status = readl(card->pBA0 + BA0_ACSTS);
// See if we have valid status.
// VSTS - Valid Status
if (status & ACSTS_VSTS)
break;
// Wait for a short while.
udelay(25);
}
// Make sure we got valid status.
if (!(status & ACSTS_VSTS))
return 1;
// Read the data returned from the AC97 register.
// ACSDA = Status Data Register = 474h
*value = readl(card->pBA0 + BA0_ACSDA);
// Success.
return (0);
}
//****************************************************************************
//
// "cs4281_write_ac97()"-- writes a word to the specified location in the
// CS461x's address space (based on the part's base address zero register).
//
// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
// 3. Write ACCTL = Control Register = 460h for initiating the write
// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
// 5. if DCV not cleared, break and return error
//
//****************************************************************************
static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
u32 value)
{
u32 count, status=0;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ n"));
// Setup the AC97 control registers on the CS4281 to send the
// appropriate command to the AC97 to perform the read.
// ACCAD = Command Address Register = 46Ch
// ACCDA = Command Data Register = 470h
// ACCTL = Control Register = 460h
// set DCV - will clear when process completed
// reset CRW - Write command
// set VFRM - valid frame enabled
// set ESYN - ASYNC generation enabled
// set RSTN - ARST# inactive, AC97 codec not reset
// Get the actual AC97 register from the offset
writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
writel(value, card->pBA0 + BA0_ACCDA);
writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
card->pBA0 + BA0_ACCTL);
// Wait for the write to occur.
for (count = 0; count < 100; count++) {
// First, we want to wait for a short time.
udelay(25);
// Now, check to see if the write has completed.
// ACCTL = 460h, DCV should be reset by now and 460h = 07h
status = readl(card->pBA0 + BA0_ACCTL);
if (!(status & ACCTL_DCV))
break;
}
// Make sure the write completed.
if (status & ACCTL_DCV) {
CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
"cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV activen"));
return 1;
}
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0n"));
// Success.
return 0;
}
//******************************************************************************
// "Init4281()" -- Bring up the part.
//******************************************************************************
static __devinit int cs4281_hw_init(struct cs4281_state *card)
{
u32 ac97_slotid;
u32 temp1, temp2;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: cs4281_hw_init()+ n"));
#ifndef NOT_CS4281_PM
if(!card)
return 1;
#endif
temp2 = readl(card->pBA0 + BA0_CFLR);
CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO
"cs4281: cs4281_hw_init() CFLR 0x%xn", temp2));
if(temp2 != CS4281_CFLR_DEFAULT)
{
CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
"cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%xn",
temp2,CS4281_CFLR_DEFAULT));
temp2 = readl(card->pBA0 + BA0_CWPR);
if(temp2 != CS4281_BA0_CPWR_DEFAULT)
{
writel(CS4281_BA0_CPWR_DEFAULT, card->pBA0 + BA0_CWPR);
temp2 = readl(card->pBA0 + BA0_CWPR);
if(temp2 != CS4281_BA0_CPWR_DEFAULT)
{
CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
"cs4281: cs4281_hw_init() Invalid hardware - unable to configure CPWR (0x%x)n",
temp2));
return 1;
}
}
writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
temp2 = readl(card->pBA0 + BA0_CFLR);
if(temp2 != CS4281_CFLR_DEFAULT)
{
CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
"cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR (0x%x)n",
temp2));
return 1;
}
}
//***************************************7
// Set up the Sound System Configuration
//***************************************
// Set the 'Configuration Write Protect' register
// to 4281h. Allows vendor-defined configuration
// space between 0e4h and 0ffh to be written.
writel(0x4281, card->pBA0 + BA0_CWPR); // (3e0h)
// (0), Blast the clock control register to zero so that the
// PLL starts out in a known state, and blast the master serial
// port control register to zero so that the serial ports also
// start out in a known state.
writel(0, card->pBA0 + BA0_CLKCR1); // (400h)
writel(0, card->pBA0 + BA0_SERMC); // (420h)
// (1), Make ESYN go to zero to turn off
// the Sync pulse on the AC97 link.
writel(0, card->pBA0 + BA0_ACCTL);
udelay(50);
// (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
// the AC97 spec) and then drive it high. This is done for non
// AC97 modes since there might be logic external to the CS461x
// that uses the ARST# line for a reset.
writel(0, card->pBA0 + BA0_SPMC); // (3ech)
udelay(100);
writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
delayus(card,50000); // Wait 50 ms for ABITCLK to become stable.
// (3) Turn on the Sound System Clocks.
writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1); // (400h)
delayus(card,50000); // Wait for the PLL to stabilize.
// Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
// (4) Power on everything for now..
writel(0x7E, card->pBA0 + BA0_SSPM); // (740h)
// (5) Wait for clock stabilization.
for (temp1 = 0; temp1 < 1000; temp1++) {
udelay(1000);
if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
break;
}
if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
"cs4281: DLLRDY failed!n"));
return -EIO;
}
// (6) Enable ASYNC generation.
writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
// Now wait 'for a short while' to allow the AC97
// part to start generating bit clock. (so we don't
// Try to start the PLL without an input clock.)
delayus(card,50000);
// Set the serial port timing configuration, so that the
// clock control circuit gets its clock from the right place.
writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
// (7) Wait for the codec ready signal from the AC97 codec.
for (temp1 = 0; temp1 < 1000; temp1++) {
// Delay a mil to let things settle out and
// to prevent retrying the read too quickly.
udelay(1000);
if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready, (464h)
break; // exit the 'for' loop.
}
if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY)) // If never came ready,
{
CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
"cs4281: ACSTS never came ready!n"));
return -EIO; // exit initialization.
}
// (8) Assert the 'valid frame' signal so we can
// begin sending commands to the AC97 codec.
writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL); // (460h)
// (9), Wait until CODEC calibration is finished.
// Print an error message if it doesn't.
for (temp1 = 0; temp1 < 1000; temp1++) {
delayus(card,10000);
// Read the AC97 Powerdown Control/Status Register.
cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
if ((temp2 & 0x0000000F) == 0x0000000F)
break;
}
if ((temp2 & 0x0000000F) != 0x0000000F) {
CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
"cs4281: Codec failed to calibrate. Status = %.8x.n",
temp2));
return -EIO;
}
// (10), Set the serial port timing configuration, so that the
// clock control circuit gets its clock from the right place.
writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
// (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
// that the codec is pumping ADC data across the AC link.
for (temp1 = 0; temp1 < 1000; temp1++) {
// Delay a mil to let things settle out and
// to prevent retrying the read too quickly.
delayus(card,1000); //(test)
// Read the input slot valid register; See
// if input slots 3 and 4 are valid yet.
if (
(readl(card->pBA0 + BA0_ACISV) &
(ACISV_ISV3 | ACISV_ISV4)) ==
(ACISV_ISV3 | ACISV_ISV4)) break; // Exit the 'for' if slots are valid.
}
// If we never got valid data, exit initialization.
if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
!= (ACISV_ISV3 | ACISV_ISV4)) {
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_ERR
"cs4281: Never got valid data!n"));
return -EIO; // If no valid data, exit initialization.
}
// (12), Start digital data transfer of audio data to the codec.
writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV); // (468h)
//**************************************
// Unmute the Master and Alternate
// (headphone) volumes. Set to max.
//**************************************
cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
//******************************************
// Power on the DAC(AddDACUser()from main())
//******************************************
cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
// Wait until we sample a DAC ready state.
for (temp2 = 0; temp2 < 32; temp2++) {
// Let's wait a mil to let things settle.
delayus(card,1000);
// Read the current state of the power control reg.
cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
// If the DAC ready state bit is set, stop waiting.
if (temp1 & 0x2)
break;
}
//******************************************
// Power on the ADC(AddADCUser()from main())
//******************************************
cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
// Wait until we sample ADC ready state.
for (temp2 = 0; temp2 < 32; temp2++) {
// Let's wait a mil to let things settle.
delayus(card,1000);
// Read the current state of the power control reg.
cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
// If the ADC ready state bit is set, stop waiting.
if (temp1 & 0x1)
break;
}
// Set up 4281 Register contents that
// don't change for boot duration.
// For playback, we map AC97 slot 3 and 4(Left
// & Right PCM playback) to DMA Channel 0.
// Set the fifo to be 15 bytes at offset zero.
ac97_slotid = 0x01000f00; // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
// FCR0.LS[4:0]=0(=>slot3, left PCM playback).
// FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
writel(ac97_slotid, card->pBA0 + BA0_FCR0); // (180h)
writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0); // Turn on FIFO Enable.
// For capture, we map AC97 slot 10 and 11(Left
// and Right PCM Record) to DMA Channel 1.
// Set the fifo to be 15 bytes at offset sixteen.
ac97_slotid = 0x0B0A0f10; // FCR1.RS[4:0]=11(=>slot11, right PCM record).
// FCR1.LS[4:0]=10(=>slot10, left PCM record).
// FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1); // (184h)
writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1); // Turn on FIFO Enable.
// Map the Playback SRC to the same AC97 slots(3 & 4--
// --Playback left & right)as DMA channel 0.
// Map the record SRC to the same AC97 slots(10 & 11--
// -- Record left & right) as DMA channel 1.
ac97_slotid = 0x0b0a0100; // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
// SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
// SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
// SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
writel(ac97_slotid, card->pBA0 + BA0_SRCSA); // (75ch)
// Set 'Half Terminal Count Interrupt Enable' and 'Terminal
// Count Interrupt Enable' in DMA Control Registers 0 & 1.
// Set 'MSK' flag to 1 to keep the DMA engines paused.
temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK); // (00030001h)
writel(temp1, card->pBA0 + BA0_DCR0); // (154h
writel(temp1, card->pBA0 + BA0_DCR1); // (15ch)
// Set 'Auto-Initialize Control' to 'enabled'; For playback,
// set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
// for record, set Transfer Type Control to 'write transfer'.
// All other bits set to zero; Some will be changed @ transfer start.
temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); // (20000018h)
writel(temp1, card->pBA0 + BA0_DMR0); // (150h)
temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
writel(temp1, card->pBA0 + BA0_DMR1); // (158h)
// Enable DMA interrupts generally, and
// DMA0 & DMA1 interrupts specifically.
temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
writel(temp1, card->pBA0 + BA0_HIMR);
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: cs4281_hw_init()- 0n"));
return 0;
}
#ifndef NOT_CS4281_PM
static void printpm(struct cs4281_state *s)
{
CS_DBGOUT(CS_PM, 9, printk("pm struct:n"));
CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%xn",
(unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%xn",
s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%xn",
s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%xn",
s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%xn",
s->pm.u32SSCR,s->pm.u32SRCSA));
CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%xn",
s->pm.u32DacASR,s->pm.u32AdcASR));
CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%xn",
s->pm.u32DacSR,s->pm.u32AdcSR));
CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%xn",
s->pm.u32MIDCR_Save));
}
static void printpipe(struct cs4281_pipeline *pl)
{
CS_DBGOUT(CS_PM, 9, printk("pm struct:n"));
CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%xn",
(unsigned)pl->flags,pl->number));
CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%xn",
pl->u32DBAnValue,pl->u32DBCnValue));
CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%xn",
pl->u32DMRnValue,pl->u32DCRnValue));
CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%xn",
pl->u32DBAnAddress,pl->u32DBCnAddress));
CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%xn",
pl->u32DCCnAddress,pl->u32DCCnAddress));
CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%xn",
pl->u32DMRnAddress,pl->u32DCRnAddress));
CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%xn",
pl->u32HDSRnAddress,pl->u32DBAn_Save));
CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%xn",
pl->u32DBCn_Save,pl->u32DMRn_Save));
CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%xn",
pl->u32DCRn_Save,pl->u32DCCn_Save));
CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%xn",
pl->u32DCAn_Save));
CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%xn",
pl->u32FCRn_Save,pl->u32FSICn_Save));
CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%xn",
pl->u32FCRnValue,pl->u32FSICnValue));
CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%xn",
pl->u32FCRnAddress,pl->u32FSICnAddress));
CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%xn",
pl->u32FPDRnValue,pl->u32FPDRnAddress));
}
static void printpipelines(struct cs4281_state *s)
{
int i;
for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
{
if(s->pl[i].flags & CS4281_PIPELINE_VALID)
{
printpipe(&s->pl[i]);
}
}
}
/****************************************************************************
*
* Suspend - save the ac97 regs, mute the outputs and power down the part.
*
****************************************************************************/
void cs4281_ac97_suspend(struct cs4281_state *s)
{
int Count,i;
CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+n"));
for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
&& (i < CS4281_AC97_NUMBER_RESTORE_REGS);
Count += 2, i++)
{
cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
}
/*
* Save the ac97 volume registers as well as the current powerdown state.
* Now, mute the all the outputs (master, headphone, and mono), as well
* as the PCM volume, in preparation for powering down the entire part.
*/
cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
/*
* And power down everything on the AC97 codec.
*/
cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-n"));
}
/****************************************************************************
*
* Resume - power up the part and restore its registers..
*
****************************************************************************/
void cs4281_ac97_resume(struct cs4281_state *s)
{
int Count,i;
CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+n"));
/* do not save the power state registers at this time
//
// If we saved away the power control registers, write them into the
// shadows so those saved values get restored instead of the current
// shadowed value.
//
if( bPowerStateSaved )
{
PokeShadow( 0x26, ulSaveReg0x26 );
bPowerStateSaved = FALSE;
}
*/
//
// First, we restore the state of the general purpose register. This
// contains the mic select (mic1 or mic2) and if we restore this after
// we restore the mic volume/boost state and mic2 was selected at
// suspend time, we will end up with a brief period of time where mic1
// is selected with the volume/boost settings for mic2, causing
// acoustic feedback. So we restore the general purpose register
// first, thereby getting the correct mic selected before we restore
// the mic volume/boost.
//
cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
//
// Now, while the outputs are still muted, restore the state of power
// on the AC97 part.
//
cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
/*
* Restore just the first set of registers, from register number
* 0x02 to the register number that ulHighestRegToRestore specifies.
*/
for( Count = 0x2, i=0;
(Count <= CS4281_AC97_HIGHESTREGTORESTORE)
&& (i < CS4281_AC97_NUMBER_RESTORE_REGS);
Count += 2, i++)
{
cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
}
CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-n"));
}
/* do not save the power state registers at this time
****************************************************************************
*
* SavePowerState - Save the power registers away.
*
****************************************************************************
void
HWAC97codec::SavePowerState(void)
{
ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()rn");
ulSaveReg0x26 = PeekShadow(0x26);
//
// Note that we have saved registers that need to be restored during a
// resume instead of ulAC97Regs[].
//
bPowerStateSaved = TRUE;
} // SavePowerState
*/
void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
{
/*
* We need to save the contents of the BASIC FIFO Registers.
*/
pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
}
void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
{
/*
* We need to restore the contents of the BASIC FIFO Registers.
*/
writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
}
void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
{
//
// We need to save the contents of the BASIC DMA Registers.
//
pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
}
void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
{
//
// We need to save the contents of the BASIC DMA Registers.
//
writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
}
int cs4281_suspend(struct cs4281_state *s)
{
int i;
u32 u32CLKCR1;
struct cs4281_pm *pm = &s->pm;
CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
printk("cs4281: cs4281_suspend()+ flags=%dn",
(unsigned)s->pm.flags));
/*
* check the current state, only suspend if IDLE
*/
if(!(s->pm.flags & CS4281_PM_IDLE))
{
CS_DBGOUT(CS_PM | CS_ERROR, 2,
printk("cs4281: cs4281_suspend() unable to suspend, not IDLEn"));
return 1;
}
s->pm.flags &= ~CS4281_PM_IDLE;
s->pm.flags |= CS4281_PM_SUSPENDING;
//
// Gershwin CLKRUN - Set CKRA
//
u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
pm->u32CLKCR1_SAVE = u32CLKCR1;
if(!(u32CLKCR1 & 0x00010000 ) )
writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
//
// First, turn on the clocks (yikes) to the devices, so that they will
// respond when we try to save their state.
//
if(!(u32CLKCR1 & CLKCR1_SWCE))
{
writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
}
//
// Save the power state
//
pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
//
// Disable interrupts.
//
writel(HICR_CHGM, s->pBA0 + BA0_HICR);
//
// Save the PCM Playback Left and Right Volume Control.
//
pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
//
// Save the FM Synthesis Left and Right Volume Control.
//
pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
//
// Save the GPIOR value.
//
pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
//
// Save the JSCTL value.
//
pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
//
// Save Sound System Control Register
//
pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
//
// Save SRC Slot Assinment register
//
pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
//
// Save sample rate
//
pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
/*
* save the current hwptr, then stop the dac/adc
*/
pm->u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
pm->u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
stop_dac(s);
stop_adc(s);
//
// Loop through all of the PipeLines
//
for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
{
if(s->pl[i].flags & CS4281_PIPELINE_VALID)
{
//
// Ask the DMAengines and FIFOs to Suspend.
//
cs4281_SuspendDMAengine(s,&s->pl[i]);
cs4281_SuspendFIFO(s,&s->pl[i]);
}
}
//
// We need to save the contents of the Midi Control Register.
//
pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
/*
* save off the AC97 part information
*/
cs4281_ac97_suspend(s);
//
// Turn off the serial ports.
//
writel(0, s->pBA0 + BA0_SERMC);
//
// Power off FM, Joystick, AC link,
//
writel(0, s->pBA0 + BA0_SSPM);
//
// DLL off.
//
writel(0, s->pBA0 + BA0_CLKCR1);
//
// AC link off.
//
writel(0, s->pBA0 + BA0_SPMC);
//
// Put the chip into D3(hot) state.
//
// PokeBA0(BA0_PMCS, 0x00000003);
//
// Gershwin CLKRUN - Clear CKRA
//
u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
#ifdef CSDEBUG
printpm(s);
printpipelines(s);
#endif
s->pm.flags &= ~CS4281_PM_SUSPENDING;
s->pm.flags |= CS4281_PM_SUSPENDED;
CS_DBGOUT(CS_PM | CS_FUNCTION, 9,
printk("cs4281: cs4281_suspend()- flags=%dn",
(unsigned)s->pm.flags));
return 0;
}
int cs4281_resume(struct cs4281_state *s)
{
int i;
unsigned temp1;
u32 u32CLKCR1;
struct cs4281_pm *pm = &s->pm;
CS_DBGOUT(CS_PM | CS_FUNCTION, 4,
printk( "cs4281: cs4281_resume()+ flags=%dn",
(unsigned)s->pm.flags));
if(!(s->pm.flags & CS4281_PM_SUSPENDED))
{
CS_DBGOUT(CS_PM | CS_ERROR, 2,
printk("cs4281: cs4281_resume() unable to resume, not SUSPENDEDn"));
return 1;
}
s->pm.flags &= ~CS4281_PM_SUSPENDED;
s->pm.flags |= CS4281_PM_RESUMING;
//
// Gershwin CLKRUN - Set CKRA
//
u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
//
// set the power state.
//
//old PokeBA0(BA0_PMCS, 0);
//
// Program the clock circuit and serial ports.
//
temp1 = cs4281_hw_init(s);
if (temp1) {
CS_DBGOUT(CS_ERROR | CS_INIT, 1,
printk(KERN_ERR
"cs4281: resume cs4281_hw_init() error.n"));
return -1;
}
//
// restore the Power state
//
writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
//
// Set post SRC mix setting (FM or ALT48K)
//
writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
//
// Loop through all of the PipeLines
//
for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
{
if(s->pl[i].flags & CS4281_PIPELINE_VALID)
{
//
// Ask the DMAengines and FIFOs to Resume.
//
cs4281_ResumeDMAengine(s,&s->pl[i]);
cs4281_ResumeFIFO(s,&s->pl[i]);
}
}
//
// We need to restore the contents of the Midi Control Register.
//
writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
cs4281_ac97_resume(s);
//
// Restore the PCM Playback Left and Right Volume Control.
//
writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
//
// Restore the FM Synthesis Left and Right Volume Control.
//
writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
//
// Restore the JSCTL value.
//
writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
//
// Restore the GPIOR register value.
//
writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
//
// Restore Sound System Control Register
//
writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
//
// Restore SRC Slot Assignment register
//
writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
//
// Restore sample rate
//
writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
//
// Restore CFL1/2 registers we saved to compensate for OEM bugs.
//
// PokeBA0(BA0_CFLR, ulConfig);
//
// Gershwin CLKRUN - Clear CKRA
//
writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
//
// Enable interrupts on the part.
//
writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
#ifdef CSDEBUG
printpm(s);
printpipelines(s);
#endif
/*
* change the state, restore the current hwptrs, then stop the dac/adc
*/
s->pm.flags |= CS4281_PM_IDLE;
s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED
| CS4281_PM_RESUMING | CS4281_PM_RESUMED);
writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
start_dac(s);
start_adc(s);
CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%dn",
(unsigned)s->pm.flags));
return 0;
}
#endif
//******************************************************************************
// "cs4281_play_rate()" --
//******************************************************************************
static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
{
u32 DACSRvalue = 1;
// Based on the sample rate, program the DACSR register.
if (playrate == 8000)
DACSRvalue = 5;
if (playrate == 11025)
DACSRvalue = 4;
else if (playrate == 22050)
DACSRvalue = 2;
else if (playrate == 44100)
DACSRvalue = 1;
else if ((playrate <= 48000) && (playrate >= 6023))
DACSRvalue = 24576000 / (playrate * 16);
else if (playrate < 6023)
// Not allowed by open.
return;
else if (playrate > 48000)
// Not allowed by open.
return;
CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
"cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%dn",
DACSRvalue, playrate));
// Write the 'sample rate select code'
// to the 'DAC Sample Rate' register.
writel(DACSRvalue, card->pBA0 + BA0_DACSR); // (744h)
}
//******************************************************************************
// "cs4281_record_rate()" -- Initialize the record sample rate converter.
//******************************************************************************
static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
{
u32 ADCSRvalue = 1;
//
// Based on the sample rate, program the ADCSR register
//
if (outrate == 8000)
ADCSRvalue = 5;
if (outrate == 11025)
ADCSRvalue = 4;
else if (outrate == 22050)
ADCSRvalue = 2;
else if (outrate == 44100)
ADCSRvalue = 1;
else if ((outrate <= 48000) && (outrate >= 6023))
ADCSRvalue = 24576000 / (outrate * 16);
else if (outrate < 6023) {
// Not allowed by open.
return;
} else if (outrate > 48000) {
// Not allowed by open.
return;
}
CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
"cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%dn",
ADCSRvalue, outrate));
// Write the 'sample rate select code
// to the 'ADC Sample Rate' register.
writel(ADCSRvalue, card->pBA0 + BA0_ADCSR); // (748h)
}
static void stop_dac(struct cs4281_state *s)
{
unsigned long flags;
unsigned temp1;
CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():n"));
spin_lock_irqsave(&s->lock, flags);
s->ena &= ~FMODE_WRITE;
temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
writel(temp1, s->pBA0 + BA0_DCR0);
spin_unlock_irqrestore(&s->lock, flags);
}
static void start_dac(struct cs4281_state *s)
{
unsigned long flags;
unsigned temp1;
CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+n"));
spin_lock_irqsave(&s->lock, flags);
if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
(s->dma_dac.count > 0
&& s->dma_dac.ready))
#ifndef NOT_CS4281_PM
&& (s->pm.flags & CS4281_PM_IDLE))
#else
)
#endif
{
s->ena |= FMODE_WRITE;
temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK; // Clear DMA0 channel mask.
writel(temp1, s->pBA0 + BA0_DCR0); // Start DMA'ing.
writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
writel(7, s->pBA0 + BA0_PPRVC);
writel(7, s->pBA0 + BA0_PPLVC);
CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
"cs4281: start_dac(): writel 0x%x start dman", temp1));
}
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4281: start_dac()-n"));
}
static void stop_adc(struct cs4281_state *s)
{
unsigned long flags;
unsigned temp1;
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4281: stop_adc()+n"));
spin_lock_irqsave(&s->lock, flags);
s->ena &= ~FMODE_READ;
if (s->conversion == 1) {
s->conversion = 0;
s->prop_adc.fmt = s->prop_adc.fmt_original;
}
temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
writel(temp1, s->pBA0 + BA0_DCR1);
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_FUNCTION, 3,
printk(KERN_INFO "cs4281: stop_adc()-n"));
}
static void start_adc(struct cs4281_state *s)
{
unsigned long flags;
unsigned temp1;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: start_adc()+n"));
if (!(s->ena & FMODE_READ) &&
(s->dma_adc.mapped || s->dma_adc.count <=
(signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
&& s->dma_adc.ready
#ifndef NOT_CS4281_PM
&& (s->pm.flags & CS4281_PM_IDLE))
#else
)
#endif
{
if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
//
// now only use 16 bit capture, due to truncation issue
// in the chip, noticable distortion occurs.
// allocate buffer and then convert from 16 bit to
// 8 bit for the user buffer.
//
s->prop_adc.fmt_original = s->prop_adc.fmt;
if (s->prop_adc.fmt & AFMT_S8) {
s->prop_adc.fmt &= ~AFMT_S8;
s->prop_adc.fmt |= AFMT_S16_LE;
}
if (s->prop_adc.fmt & AFMT_U8) {
s->prop_adc.fmt &= ~AFMT_U8;
s->prop_adc.fmt |= AFMT_U16_LE;
}
//
// prog_dmabuf_adc performs a stop_adc() but that is
// ok since we really haven't started the DMA yet.
//
prog_codec(s, CS_TYPE_ADC);
if (prog_dmabuf_adc(s) != 0) {
CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
"cs4281: start_adc(): error in prog_dmabuf_adcn"));
}
s->conversion = 1;
}
spin_lock_irqsave(&s->lock, flags);
s->ena |= FMODE_READ;
temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK; // Clear DMA1 channel mask bit.
writel(temp1, s->pBA0 + BA0_DCR1); // Start recording
writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR); // Enable interrupts.
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
"cs4281: start_adc(): writel 0x%x n", temp1));
}
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: start_adc()-n"));
}
// ---------------------------------------------------------------------
#define DMABUF_MINORDER 0 // ==> min buffer size = 8K.
extern void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
{
struct page *map, *mapend;
if (db->rawbuf) {
// Undo prog_dmabuf()'s marking the pages as reserved
mapend = virt_to_page(db->rawbuf +
(PAGE_SIZE << db->buforder) - 1);
for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
cs4x_mem_map_unreserve(map);
pci_free_consistent(s->pcidev, PAGE_SIZE << db->buforder,
db->rawbuf, db->dmaaddr);
}
if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
// Undo prog_dmabuf()'s marking the pages as reserved
mapend = virt_to_page(s->tmpbuff +
(PAGE_SIZE << s->buforder_tmpbuff) - 1);
for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
cs4x_mem_map_unreserve(map);
pci_free_consistent(s->pcidev, PAGE_SIZE << s->buforder_tmpbuff,
s->tmpbuff, s->dmaaddr_tmpbuff);
}
s->tmpbuff = NULL;
db->rawbuf = NULL;
db->mapped = db->ready = 0;
}
static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
{
int order;
unsigned bytespersec, temp1;
unsigned bufs, sample_shift = 0;
struct page *map, *mapend;
unsigned long df;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: prog_dmabuf()+n"));
db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
/*
* check for order within limits, but do not overwrite value, check
* later for a fractional defaultorder (i.e. 100+).
*/
if((defaultorder >= 0) && (defaultorder < 12))
df = defaultorder;
else
df = 1;
if (!db->rawbuf) {
db->ready = db->mapped = 0;
for (order = df; order >= DMABUF_MINORDER; order--)
if ( (db->rawbuf = (void *) pci_alloc_consistent(
s->pcidev, PAGE_SIZE << order, &db->dmaaddr)))
break;
if (!db->rawbuf) {
CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
"cs4281: prog_dmabuf(): unable to allocate rawbufn"));
return -ENOMEM;
}
db->buforder = order;
// Now mark the pages as reserved; otherwise the
// remap_page_range() in cs4281_mmap doesn't work.
// 1. get index to last page in mem_map array for rawbuf.
mapend = virt_to_page(db->rawbuf +
(PAGE_SIZE << db->buforder) - 1);
// 2. mark each physical page in range as 'reserved'.
for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
cs4x_mem_map_reserve(map);
}
if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
for (order = df; order >= DMABUF_MINORDER;
order--)
if ( (s->tmpbuff = (void *) pci_alloc_consistent(
s->pcidev, PAGE_SIZE << order,
&s->dmaaddr_tmpbuff)))
break;
if (!s->tmpbuff) {
CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
"cs4281: prog_dmabuf(): unable to allocate tmpbuffn"));
return -ENOMEM;
}
s->buforder_tmpbuff = order;
// Now mark the pages as reserved; otherwise the
// remap_page_range() in cs4281_mmap doesn't work.
// 1. get index to last page in mem_map array for rawbuf.
mapend = virt_to_page(s->tmpbuff +
(PAGE_SIZE << s->buforder_tmpbuff) - 1);
// 2. mark each physical page in range as 'reserved'.
for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
cs4x_mem_map_reserve(map);
}
if (db->type == CS_TYPE_DAC) {
if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
sample_shift++;
if (s->prop_dac.channels > 1)
sample_shift++;
bytespersec = s->prop_dac.rate << sample_shift;
} else // CS_TYPE_ADC
{
if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
sample_shift++;
if (s->prop_adc.channels > 1)
sample_shift++;
bytespersec = s->prop_adc.rate << sample_shift;
}
bufs = PAGE_SIZE << db->buforder;
/*
* added fractional "defaultorder" inputs. if >100 then use
* defaultorder-100 as power of 2 for the buffer size. example:
* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
*/
if(defaultorder >= 100)
{
bufs = 1 << (defaultorder-100);
}
#define INTERRUPT_RATE_MS 100 // Interrupt rate in milliseconds.
db->numfrag = 2;
/*
* Nominal frag size(bytes/interrupt)
*/
temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
db->fragshift = 8; // Min 256 bytes.
while (1 << db->fragshift < temp1) // Calc power of 2 frag size.
db->fragshift += 1;
db->fragsize = 1 << db->fragshift;
db->dmasize = db->fragsize * 2;
db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
// If the calculated size is larger than the allocated
// buffer, divide the allocated buffer into 2 fragments.
if (db->dmasize > bufs) {
db->numfrag = 2; // Two fragments.
db->fragsize = bufs >> 1; // Each 1/2 the alloc'ed buffer.
db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
db->dmasize = bufs; // Use all the alloc'ed buffer.
db->fragshift = 0; // Calculate 'fragshift'.
temp1 = db->fragsize; // update_ptr() uses it
while ((temp1 >>= 1) > 1) // to calc 'total-bytes'
db->fragshift += 1; // returned in DSP_GETI/OPTR.
}
CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
"cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%dn",
db->numfrag, db->fragsize, db->fragsamples,
db->fragshift, bufs,
(db->type == CS_TYPE_DAC) ? s->prop_dac.fmt :
s->prop_adc.fmt,
(db->type == CS_TYPE_DAC) ? s->prop_dac.channels :
s->prop_adc.channels));
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: prog_dmabuf()-n"));
return 0;
}
static int prog_dmabuf_adc(struct cs4281_state *s)
{
unsigned long va;
unsigned count;
int c;
stop_adc(s);
s->dma_adc.type = CS_TYPE_ADC;
if ((c = prog_dmabuf(s, &s->dma_adc)))
return c;
if (s->dma_adc.rawbuf) {
memset(s->dma_adc.rawbuf,
(s->prop_adc.
fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
s->dma_adc.dmasize);
}
if (s->tmpbuff) {
memset(s->tmpbuff,
(s->prop_adc.
fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
PAGE_SIZE << s->buforder_tmpbuff);
}
va = virt_to_bus(s->dma_adc.rawbuf);
count = s->dma_adc.dmasize;
if (s->prop_adc.
fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
count /= 2; // 16-bit.
if (s->prop_adc.channels > 1)
count /= 2; // Assume stereo.
CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
"cs4281: prog_dmabuf_adc(): count=%d va=0x%.8xn",
count, (unsigned) va));
writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
writel(count - 1, s->pBA0 + BA0_DBC1); // Set count.
s->dma_adc.ready = 1;
return 0;
}
static int prog_dmabuf_dac(struct cs4281_state *s)
{
unsigned long va;
unsigned count;
int c;
stop_dac(s);
s->dma_dac.type = CS_TYPE_DAC;
if ((c = prog_dmabuf(s, &s->dma_dac)))
return c;
memset(s->dma_dac.rawbuf,
(s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
s->dma_dac.dmasize);
va = virt_to_bus(s->dma_dac.rawbuf);
count = s->dma_dac.dmasize;
if (s->prop_dac.
fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
count /= 2; // 16-bit.
if (s->prop_dac.channels > 1)
count /= 2; // Assume stereo.
writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
writel(count - 1, s->pBA0 + BA0_DBC0); // Set count.
CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
"cs4281: prog_dmabuf_dac(): count=%d va=0x%.8xn",
count, (unsigned) va));
s->dma_dac.ready = 1;
return 0;
}
static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
unsigned len, unsigned char c)
{
if (bptr + len > bsize) {
unsigned x = bsize - bptr;
memset(((char *) buf) + bptr, c, x);
bptr = 0;
len -= x;
}
CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
"cs4281: clear_advance(): memset %d at 0x%.8x for %d size n",
(unsigned)c, (unsigned)((char *) buf) + bptr, len));
memset(((char *) buf) + bptr, c, len);
}
// call with spinlock held!
static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
{
int diff;
unsigned hwptr, va;
// update ADC pointer
if (s->ena & FMODE_READ) {
hwptr = readl(s->pBA0 + BA0_DCA1); // Read capture DMA address.
va = virt_to_bus(s->dma_adc.rawbuf);
hwptr -= (unsigned) va;
diff =
(s->dma_adc.dmasize + hwptr -
s->dma_adc.hwptr) % s->dma_adc.dmasize;
s->dma_adc.hwptr = hwptr;
s->dma_adc.total_bytes += diff;
s->dma_adc.count += diff;
if (s->dma_adc.count > s->dma_adc.dmasize)
s->dma_adc.count = s->dma_adc.dmasize;
if (s->dma_adc.mapped) {
if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
wake_up(&s->dma_adc.wait);
} else {
if (s->dma_adc.count > 0)
wake_up(&s->dma_adc.wait);
}
CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
"cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d n",
(unsigned)s, s->dma_adc.hwptr,
s->dma_adc.total_bytes, s->dma_adc.count));
}
// update DAC pointer
//
// check for end of buffer, means that we are going to wait for another interrupt
// to allow silence to fill the fifos on the part, to keep pops down to a minimum.
//
if (s->ena & FMODE_WRITE) {
hwptr = readl(s->pBA0 + BA0_DCA0); // Read play DMA address.
va = virt_to_bus(s->dma_dac.rawbuf);
hwptr -= (unsigned) va;
diff = (s->dma_dac.dmasize + hwptr -
s->dma_dac.hwptr) % s->dma_dac.dmasize;
s->dma_dac.hwptr = hwptr;
s->dma_dac.total_bytes += diff;
if (s->dma_dac.mapped) {
s->dma_dac.count += diff;
if (s->dma_dac.count >= s->dma_dac.fragsize) {
s->dma_dac.wakeup = 1;
wake_up(&s->dma_dac.wait);
if (s->dma_dac.count > s->dma_dac.dmasize)
s->dma_dac.count &=
s->dma_dac.dmasize - 1;
}
} else {
s->dma_dac.count -= diff;
if (s->dma_dac.count <= 0) {
//
// fill with silence, and do not shut down the DAC.
// Continue to play silence until the _release.
//
CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
"cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size n",
(unsigned)(s->prop_dac.fmt &
(AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
(unsigned)s->dma_dac.rawbuf,
s->dma_dac.dmasize));
memset(s->dma_dac.rawbuf,
(s->prop_dac.
fmt & (AFMT_U8 | AFMT_U16_LE)) ?
0x80 : 0, s->dma_dac.dmasize);
if (s->dma_dac.count < 0) {
s->dma_dac.underrun = 1;
s->dma_dac.count = 0;
CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
"cs4281: cs4281_update_ptr(): underrunn"));
}
} else if (s->dma_dac.count <=
(signed) s->dma_dac.fragsize
&& !s->dma_dac.endcleared) {
clear_advance(s->dma_dac.rawbuf,
s->dma_dac.dmasize,
s->dma_dac.swptr,
s->dma_dac.fragsize,
(s->prop_dac.
fmt & (AFMT_U8 |
AFMT_U16_LE)) ? 0x80
: 0);
s->dma_dac.endcleared = 1;
}
if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
intflag)
{
wake_up(&s->dma_dac.wait);
}
}
CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
"cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d n",
(unsigned) s, s->dma_dac.hwptr,
s->dma_dac.total_bytes, s->dma_dac.count));
}
}
// ---------------------------------------------------------------------
static void prog_codec(struct cs4281_state *s, unsigned type)
{
unsigned long flags;
unsigned temp1, format;
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: prog_codec()+ n"));
spin_lock_irqsave(&s->lock, flags);
if (type == CS_TYPE_ADC) {
temp1 = readl(s->pBA0 + BA0_DCR1);
writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1); // Stop capture DMA, if active.
// program sampling rates
// Note, for CS4281, capture & play rates can be set independently.
cs4281_record_rate(s, s->prop_adc.rate);
// program ADC parameters
format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
if (s->prop_adc.
fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE)) // Big-endian?
format |= DMRn_BEND;
if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
format |= DMRn_USIGN; // Unsigned.
} else
format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
if (s->prop_adc.channels < 2)
format |= DMRn_MONO;
writel(format, s->pBA0 + BA0_DMR1);
CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
"cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8xn",
(format & DMRn_SIZE8) ? "8" : "16",
(format & DMRn_USIGN) ? "Unsigned" : "Signed",
(format & DMRn_MONO) ? "Mono" : "Stereo",
s->prop_adc.rate, format));
s->ena &= ~FMODE_READ; // not capturing data yet
}
if (type == CS_TYPE_DAC) {
temp1 = readl(s->pBA0 + BA0_DCR0);
writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0); // Stop play DMA, if active.
// program sampling rates
// Note, for CS4281, capture & play rates can be set independently.
cs4281_play_rate(s, s->prop_dac.rate);
// program DAC parameters
format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
if (s->prop_dac.
fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) { // 16-bit
if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
format |= DMRn_BEND; // Big Endian.
if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
format |= DMRn_USIGN; // Unsigned.
} else
format |= DMRn_SIZE8 | DMRn_USIGN; // 8-bit, unsigned
if (s->prop_dac.channels < 2)
format |= DMRn_MONO;
writel(format, s->pBA0 + BA0_DMR0);
CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
"cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8xn",
(format & DMRn_SIZE8) ? "8" : "16",
(format & DMRn_USIGN) ? "Unsigned" : "Signed",
(format & DMRn_MONO) ? "Mono" : "Stereo",
s->prop_dac.rate, format));
s->ena &= ~FMODE_WRITE; // not capturing data yet
}
spin_unlock_irqrestore(&s->lock, flags);
CS_DBGOUT(CS_FUNCTION, 2,
printk(KERN_INFO "cs4281: prog_codec()- n"));
}
static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
unsigned long arg)
{
int return_mask=0;
// Index to mixer_src[] is value of AC97 Input Mux Select Reg.
// Value of array member is recording source Device ID Mask.
static const unsigned int mixer_src[8] = {
SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
};
// Index of mixtable1[] member is Device ID
// and must be <= SOUND_MIXER_NRDEVICES.
// Value of array member is index into s->mix.vol[]
static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
[SOUND_MIXER_PCM] = 1, // voice
[SOUND_MIXER_LINE1] = 2, // AUX
[SOUND_MIXER_CD] = 3, // CD
[SOUND_MIXER_LINE] = 4, // Line
[SOUND_MIXER_SYNTH] = 5, // FM
[SOUND_MIXER_MIC] = 6, // Mic
[SOUND_MIXER_SPEAKER] = 7, // Speaker
[SOUND_MIXER_RECLEV] = 8, // Recording level
[SOUND_MIXER_VOLUME] = 9 // Master Volume
};
static const unsigned mixreg[] = {
BA0_AC97_PCM_OUT_VOLUME,
BA0_AC97_AUX_VOLUME,
BA0_AC97_CD_VOLUME,
BA0_AC97_LINE_IN_VOLUME
};
unsigned char l, r, rl, rr, vidx;
unsigned char attentbl[11] =
{ 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
unsigned temp1;
int i, val;
VALIDATE_STATE(s);
CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
"cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8xn",
(unsigned) s, cmd));
#if CSDEBUG
cs_printioctl(cmd);
#endif
#if CSDEBUG_INTERFACE
if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
(cmd == SOUND_MIXER_CS_SETDBGMASK) ||
(cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
(cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
(cmd == SOUND_MIXER_CS_APM))
{
switch (cmd) {
case SOUND_MIXER_CS_GETDBGMASK:
return put_user(cs_debugmask,
(unsigned long *) arg);
case SOUND_MIXER_CS_GETDBGLEVEL:
return put_user(cs_debuglevel,
(unsigned long *) arg);
case SOUND_MIXER_CS_SETDBGMASK:
if (get_user(val, (unsigned long *) arg))
return -EFAULT;
cs_debugmask = val;
return 0;
case SOUND_MIXER_CS_SETDBGLEVEL:
if (get_user(val, (unsigned long *) arg))
return -EFAULT;
cs_debuglevel = val;
return 0;
#ifndef NOT_CS4281_PM
case SOUND_MIXER_CS_APM:
if (get_user(val, (unsigned long *) arg))
return -EFAULT;
if(val == CS_IOCTL_CMD_SUSPEND)
cs4281_suspend(s);
else if(val == CS_IOCTL_CMD_RESUME)
cs4281_resume(s);
else
{
CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
"cs4281: mixer_ioctl(): invalid APM cmd (%d)n",
val));
}
return 0;
#endif
default:
CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
"cs4281: mixer_ioctl(): ERROR unknown debug cmdn"));
return 0;
}
}
#endif
if (cmd == SOUND_MIXER_PRIVATE1) {
// enable/disable/query mixer preamp
if (get_user(val, (int *) arg))
return -EFAULT;
if (val != -1) {
cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
}
cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
val = (temp1 & 0x40) ? 1 : 0;
return put_user(val, (int *) arg);
}
if (cmd == SOUND_MIXER_PRIVATE2) {
// enable/disable/query spatializer
if (get_user(val, (int *) arg))
return -EFAULT;
if (val != -1) {
temp1 = (val & 0x3f) >> 2;
cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
&temp1);
cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
temp1 | 0x2000);
}
cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
return put_user((temp1 << 2) | 3, (int *) arg);
}
if (cmd == SOUND_MIXER_INFO) {
mixer_info info;
strncpy(info.id, "CS4281", sizeof(info.id));
strncpy(info.name, "Crystal CS4281", sizeof(info.name));
info.modify_counter = s->mix.modcnt;
if (copy_to_user((void *) arg, &info, sizeof(info)))
return -EFAULT;
return 0;
}