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DAC960.h
资源名称：linux-2.4.20.tar.gz　[点击查看]
上传用户：jlfgdled
上传日期：2013-04-10
资源大小：33168k
文件大小：144k
源码类别：

Linux/Unix编程

开发平台：

Unix_Linux

DAC960.h：源码内容
  2. typedef enum DAC960_MessageLevel
  3. {
  4.   DAC960_AnnounceLevel = 0,
  5.   DAC960_InfoLevel = 1,
  6.   DAC960_NoticeLevel = 2,
  7.   DAC960_WarningLevel = 3,
  8.   DAC960_ErrorLevel = 4,
  9.   DAC960_ProgressLevel = 5,
  10.   DAC960_CriticalLevel = 6,
  11.   DAC960_UserCriticalLevel = 7
  12. }
  13. DAC960_MessageLevel_T;
  15. static char
  16.   *DAC960_MessageLevelMap[] =
  17.     { KERN_NOTICE, KERN_NOTICE, KERN_NOTICE, KERN_WARNING,
  18.       KERN_ERR, KERN_CRIT, KERN_CRIT, KERN_CRIT };
  21. /*
  22.   Define Driver Message macros.
  23. */
  25. #define DAC960_Announce(Format, Arguments...) 
  26.   DAC960_Message(DAC960_AnnounceLevel, Format, ##Arguments)
  28. #define DAC960_Info(Format, Arguments...) 
  29.   DAC960_Message(DAC960_InfoLevel, Format, ##Arguments)
  31. #define DAC960_Notice(Format, Arguments...) 
  32.   DAC960_Message(DAC960_NoticeLevel, Format, ##Arguments)
  34. #define DAC960_Warning(Format, Arguments...) 
  35.   DAC960_Message(DAC960_WarningLevel, Format, ##Arguments)
  37. #define DAC960_Error(Format, Arguments...) 
  38.   DAC960_Message(DAC960_ErrorLevel, Format, ##Arguments)
  40. #define DAC960_Progress(Format, Arguments...) 
  41.   DAC960_Message(DAC960_ProgressLevel, Format, ##Arguments)
  43. #define DAC960_Critical(Format, Arguments...) 
  44.   DAC960_Message(DAC960_CriticalLevel, Format, ##Arguments)
  46. #define DAC960_UserCritical(Format, Arguments...) 
  47.   DAC960_Message(DAC960_UserCriticalLevel, Format, ##Arguments)
  50. /*
  51.   Define types for some of the structures that interface with the rest
  52.   of the Linux Kernel and I/O Subsystem.
  53. */
  55. typedef struct buffer_head BufferHeader_T;
  56. typedef struct file File_T;
  57. typedef struct block_device_operations BlockDeviceOperations_T;
  58. typedef struct completion Completion_T;
  59. typedef struct gendisk GenericDiskInfo_T;
  60. typedef struct hd_geometry DiskGeometry_T;
  61. typedef struct hd_struct DiskPartition_T;
  62. typedef struct inode Inode_T;
  63. typedef struct inode_operations InodeOperations_T;
  64. typedef kdev_t KernelDevice_T;
  65. typedef struct list_head ListHead_T;
  66. typedef struct notifier_block NotifierBlock_T;
  67. typedef struct pci_dev PCI_Device_T;
  68. typedef struct proc_dir_entry PROC_DirectoryEntry_T;
  69. typedef unsigned long ProcessorFlags_T;
  70. typedef struct pt_regs Registers_T;
  71. typedef struct request IO_Request_T;
  72. typedef request_queue_t RequestQueue_T;
  73. typedef struct super_block SuperBlock_T;
  74. typedef struct timer_list Timer_T;
  75. typedef wait_queue_head_t WaitQueue_T;
  78. /*
  79.   Define the DAC960 V1 Firmware Controller Status Mailbox structure.
  80. */
  82. typedef union DAC960_V1_StatusMailbox
  83. {
  84.   unsigned int Word; /* Word 0 */
  85.   struct {
  86.     DAC960_V1_CommandIdentifier_T CommandIdentifier; /* Byte 0 */
  87.     unsigned char :7; /* Byte 1 Bits 0-6 */
  88.     boolean Valid:1; /* Byte 1 Bit 7 */
  89.     DAC960_V1_CommandStatus_T CommandStatus; /* Bytes 2-3 */
  90.   } Fields;
  91. }
  92. DAC960_V1_StatusMailbox_T;
  95. /*
  96.   Define the DAC960 V2 Firmware Controller Status Mailbox structure.
  97. */
  99. typedef union DAC960_V2_StatusMailbox
  100. {
  101.   unsigned int Words[2]; /* Words 0-1 */
  102.   struct {
  103.     DAC960_V2_CommandIdentifier_T CommandIdentifier; /* Bytes 0-1 */
  104.     DAC960_V2_CommandStatus_T CommandStatus; /* Byte 2 */
  105.     unsigned char RequestSenseLength; /* Byte 3 */
  106.     int DataTransferResidue; /* Bytes 4-7 */
  107.   } Fields;
  108. }
  109. DAC960_V2_StatusMailbox_T;
  112. /*
  113.   Define the DAC960 Driver Command Types.
  114. */
  116. typedef enum
  117. {
  118.   DAC960_ReadCommand = 1,
  119.   DAC960_WriteCommand = 2,
  120.   DAC960_ReadRetryCommand = 3,
  121.   DAC960_WriteRetryCommand = 4,
  122.   DAC960_MonitoringCommand = 5,
  123.   DAC960_ImmediateCommand = 6,
  124.   DAC960_QueuedCommand = 7
  125. }
  126. DAC960_CommandType_T;
  129. /*
  130.   Define the DAC960 Driver Command structure.
  131. */
  133. typedef struct DAC960_Command
  134. {
  135.   int CommandIdentifier;
  136.   DAC960_CommandType_T CommandType;
  137.   struct DAC960_Controller *Controller;
  138.   struct DAC960_Command *Next;
  139.   Completion_T *Completion;
  140.   unsigned int LogicalDriveNumber;
  141.   unsigned int BlockNumber;
  142.   unsigned int BlockCount;
  143.   unsigned int SegmentCount;
  144.   BufferHeader_T *BufferHeader;
  145.   void *RequestBuffer;
  146.   union {
  147.     struct {
  148.       DAC960_V1_CommandMailbox_T CommandMailbox;
  149.       DAC960_V1_KernelCommand_T *KernelCommand;
  150.       DAC960_V1_CommandStatus_T CommandStatus;
  151.       DAC960_V1_ScatterGatherSegment_T
  152. ScatterGatherList[DAC960_V1_ScatterGatherLimit]
  153. __attribute__ ((aligned (sizeof(DAC960_V1_ScatterGatherSegment_T))));
  154.       unsigned int EndMarker[0];
  155.     } V1;
  156.     struct {
  157.       DAC960_V2_CommandMailbox_T CommandMailbox;
  158.       DAC960_V2_KernelCommand_T *KernelCommand;
  159.       DAC960_V2_CommandStatus_T CommandStatus;
  160.       unsigned char RequestSenseLength;
  161.       int DataTransferResidue;
  162.       DAC960_V2_ScatterGatherSegment_T
  163. ScatterGatherList[DAC960_V2_ScatterGatherLimit]
  164. __attribute__ ((aligned (sizeof(DAC960_V2_ScatterGatherSegment_T))));
  165.       DAC960_SCSI_RequestSense_T RequestSense
  166. __attribute__ ((aligned (sizeof(int))));
  167.       unsigned int EndMarker[0];
  168.     } V2;
  169.   } FW;
  170. }
  171. DAC960_Command_T;
  174. /*
  175.   Define the DAC960 Driver Controller structure.
  176. */
  178. typedef struct DAC960_Controller
  179. {
  180.   void *BaseAddress;
  181.   void *MemoryMappedAddress;
  182.   DAC960_FirmwareType_T FirmwareType;
  183.   DAC960_HardwareType_T HardwareType;
  184.   DAC960_IO_Address_T IO_Address;
  185.   DAC960_PCI_Address_T PCI_Address;
  186.   unsigned char ControllerNumber;
  187.   unsigned char ControllerName[4];
  188.   unsigned char ModelName[20];
  189.   unsigned char FullModelName[28];
  190.   unsigned char FirmwareVersion[12];
  191.   unsigned char Bus;
  192.   unsigned char Device;
  193.   unsigned char Function;
  194.   unsigned char IRQ_Channel;
  195.   unsigned char Channels;
  196.   unsigned char Targets;
  197.   unsigned char MemorySize;
  198.   unsigned char LogicalDriveCount;
  199.   unsigned short CommandAllocationGroupSize;
  200.   unsigned short ControllerQueueDepth;
  201.   unsigned short DriverQueueDepth;
  202.   unsigned short MaxBlocksPerCommand;
  203.   unsigned short ControllerScatterGatherLimit;
  204.   unsigned short DriverScatterGatherLimit;
  205.   unsigned int ControllerUsageCount;
  206.   unsigned int CombinedStatusBufferLength;
  207.   unsigned int InitialStatusLength;
  208.   unsigned int CurrentStatusLength;
  209.   unsigned int ProgressBufferLength;
  210.   unsigned int UserStatusLength;
  211.   unsigned long MemoryMailboxPagesAddress;
  212.   unsigned long MemoryMailboxPagesOrder;
  213.   unsigned long MonitoringTimerCount;
  214.   unsigned long PrimaryMonitoringTime;
  215.   unsigned long SecondaryMonitoringTime;
  216.   unsigned long LastProgressReportTime;
  217.   unsigned long LastCurrentStatusTime;
  218.   boolean ControllerDetectionSuccessful;
  219.   boolean ControllerInitialized;
  220.   boolean MonitoringCommandDeferred;
  221.   boolean EphemeralProgressMessage;
  222.   boolean DriveSpinUpMessageDisplayed;
  223.   boolean MonitoringAlertMode;
  224.   boolean SuppressEnclosureMessages;
  225.   Timer_T MonitoringTimer;
  226.   GenericDiskInfo_T GenericDiskInfo;
  227.   DAC960_Command_T *FreeCommands;
  228.   unsigned char *CombinedStatusBuffer;
  229.   unsigned char *CurrentStatusBuffer;
  230.   RequestQueue_T *RequestQueue;
  231.   WaitQueue_T CommandWaitQueue;
  232.   WaitQueue_T HealthStatusWaitQueue;
  233.   DAC960_Command_T InitialCommand;
  234.   DAC960_Command_T *Commands[DAC960_MaxDriverQueueDepth];
  235.   PROC_DirectoryEntry_T *ControllerProcEntry;
  236.   unsigned int LogicalDriveUsageCount[DAC960_MaxLogicalDrives];
  237.   boolean LogicalDriveInitiallyAccessible[DAC960_MaxLogicalDrives];
  238.   void (*QueueCommand)(DAC960_Command_T *Command);
  239.   boolean (*ReadControllerConfiguration)(struct DAC960_Controller *);
  240.   boolean (*ReadDeviceConfiguration)(struct DAC960_Controller *);
  241.   boolean (*ReportDeviceConfiguration)(struct DAC960_Controller *);
  242.   void (*QueueReadWriteCommand)(DAC960_Command_T *Command);
  243.   union {
  244.     struct {
  245.       unsigned char GeometryTranslationHeads;
  246.       unsigned char GeometryTranslationSectors;
  247.       unsigned char PendingRebuildFlag;
  248.       unsigned short StripeSize;
  249.       unsigned short SegmentSize;
  250.       unsigned short NewEventLogSequenceNumber;
  251.       unsigned short OldEventLogSequenceNumber;
  252.       unsigned short DeviceStateChannel;
  253.       unsigned short DeviceStateTargetID;
  254.       boolean DualModeMemoryMailboxInterface;
  255.       boolean BackgroundInitializationStatusSupported;
  256.       boolean SAFTE_EnclosureManagementEnabled;
  257.       boolean NeedLogicalDriveInformation;
  258.       boolean NeedErrorTableInformation;
  259.       boolean NeedDeviceStateInformation;
  260.       boolean NeedDeviceInquiryInformation;
  261.       boolean NeedDeviceSerialNumberInformation;
  262.       boolean NeedRebuildProgress;
  263.       boolean NeedConsistencyCheckProgress;
  264.       boolean NeedBackgroundInitializationStatus;
  265.       boolean StartDeviceStateScan;
  266.       boolean RebuildProgressFirst;
  267.       boolean RebuildFlagPending;
  268.       boolean RebuildStatusPending;
  269.       DAC960_V1_CommandMailbox_T *FirstCommandMailbox;
  270.       DAC960_V1_CommandMailbox_T *LastCommandMailbox;
  271.       DAC960_V1_CommandMailbox_T *NextCommandMailbox;
  272.       DAC960_V1_CommandMailbox_T *PreviousCommandMailbox1;
  273.       DAC960_V1_CommandMailbox_T *PreviousCommandMailbox2;
  274.       DAC960_V1_StatusMailbox_T *FirstStatusMailbox;
  275.       DAC960_V1_StatusMailbox_T *LastStatusMailbox;
  276.       DAC960_V1_StatusMailbox_T *NextStatusMailbox;
  277.       DAC960_V1_DCDB_T MonitoringDCDB;
  278.       DAC960_V1_Enquiry_T Enquiry;
  279.       DAC960_V1_Enquiry_T NewEnquiry;
  280.       DAC960_V1_ErrorTable_T ErrorTable;
  281.       DAC960_V1_ErrorTable_T NewErrorTable;
  282.       DAC960_V1_EventLogEntry_T EventLogEntry;
  283.       DAC960_V1_RebuildProgress_T RebuildProgress;
  284.       DAC960_V1_CommandStatus_T LastRebuildStatus;
  285.       DAC960_V1_CommandStatus_T PendingRebuildStatus;
  286.       DAC960_V1_LogicalDriveInformationArray_T LogicalDriveInformation;
  287.       DAC960_V1_LogicalDriveInformationArray_T NewLogicalDriveInformation;
  288.       DAC960_V1_BackgroundInitializationStatus_T
  289.         BackgroundInitializationStatus;
  290.       DAC960_V1_BackgroundInitializationStatus_T
  291.         LastBackgroundInitializationStatus;
  292.       DAC960_V1_DeviceState_T
  293. DeviceState[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  294.       DAC960_V1_DeviceState_T NewDeviceState;
  295.       DAC960_SCSI_Inquiry_T
  296. InquiryStandardData[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  297.       DAC960_SCSI_Inquiry_UnitSerialNumber_T
  298. InquiryUnitSerialNumber[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  299.       int DeviceResetCount[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  300.       boolean DirectCommandActive[DAC960_V1_MaxChannels][DAC960_V1_MaxTargets];
  301.     } V1;
  302.     struct {
  303.       unsigned int StatusChangeCounter;
  304.       unsigned int NextEventSequenceNumber;
  305.       unsigned int PhysicalDeviceIndex;
  306.       boolean NeedLogicalDeviceInformation;
  307.       boolean NeedPhysicalDeviceInformation;
  308.       boolean NeedDeviceSerialNumberInformation;
  309.       boolean StartLogicalDeviceInformationScan;
  310.       boolean StartPhysicalDeviceInformationScan;
  311.       DAC960_V2_CommandMailbox_T *FirstCommandMailbox;
  312.       DAC960_V2_CommandMailbox_T *LastCommandMailbox;
  313.       DAC960_V2_CommandMailbox_T *NextCommandMailbox;
  314.       DAC960_V2_CommandMailbox_T *PreviousCommandMailbox1;
  315.       DAC960_V2_CommandMailbox_T *PreviousCommandMailbox2;
  316.       DAC960_V2_StatusMailbox_T *FirstStatusMailbox;
  317.       DAC960_V2_StatusMailbox_T *LastStatusMailbox;
  318.       DAC960_V2_StatusMailbox_T *NextStatusMailbox;
  319.       DAC960_V2_HealthStatusBuffer_T *HealthStatusBuffer;
  320.       DAC960_V2_ControllerInfo_T ControllerInformation;
  321.       DAC960_V2_ControllerInfo_T NewControllerInformation;
  322.       DAC960_V2_LogicalDeviceInfo_T
  323. *LogicalDeviceInformation[DAC960_MaxLogicalDrives];
  324.       DAC960_V2_LogicalDeviceInfo_T NewLogicalDeviceInformation;
  325.       DAC960_V2_PhysicalDeviceInfo_T
  326. *PhysicalDeviceInformation[DAC960_V2_MaxPhysicalDevices];
  327.       DAC960_V2_PhysicalDeviceInfo_T NewPhysicalDeviceInformation;
  328.       DAC960_SCSI_Inquiry_UnitSerialNumber_T
  329. *InquiryUnitSerialNumber[DAC960_V2_MaxPhysicalDevices];
  330.       DAC960_V2_PhysicalDevice_T
  331. LogicalDriveToVirtualDevice[DAC960_MaxLogicalDrives];
  332.       DAC960_V2_Event_T Event;
  333.       boolean LogicalDriveFoundDuringScan[DAC960_MaxLogicalDrives];
  334.     } V2;
  335.   } FW;
  336.   DiskPartition_T DiskPartitions[DAC960_MinorCount];
  337.   int PartitionSizes[DAC960_MinorCount];
  338.   int BlockSizes[DAC960_MinorCount];
  339.   int MaxSectorsPerRequest[DAC960_MinorCount];
  340.   unsigned char ProgressBuffer[DAC960_ProgressBufferSize];
  341.   unsigned char UserStatusBuffer[DAC960_UserMessageSize];
  342. }
  343. DAC960_Controller_T;
  346. /*
  347.   Simplify access to Firmware Version Dependent Data Structure Components
  348.   and Functions.
  349. */
  351. #define V1 FW.V1
  352. #define V2 FW.V2
  353. #define DAC960_QueueCommand(Command) 
  354.   (Controller->QueueCommand)(Command)
  355. #define DAC960_ReadControllerConfiguration(Controller) 
  356.   (Controller->ReadControllerConfiguration)(Controller)
  357. #define DAC960_ReadDeviceConfiguration(Controller) 
  358.   (Controller->ReadDeviceConfiguration)(Controller)
  359. #define DAC960_ReportDeviceConfiguration(Controller) 
  360.   (Controller->ReportDeviceConfiguration)(Controller)
  361. #define DAC960_QueueReadWriteCommand(Command) 
  362.   (Controller->QueueReadWriteCommand)(Command)
  365. /*
  366.   DAC960_AcquireControllerLock acquires exclusive access to Controller.
  367. */
  369. static inline
  370. void DAC960_AcquireControllerLock(DAC960_Controller_T *Controller,
  371.   ProcessorFlags_T *ProcessorFlags)
  372. {
  373.   spin_lock_irqsave(&io_request_lock, *ProcessorFlags);
  374. }
  377. /*
  378.   DAC960_ReleaseControllerLock releases exclusive access to Controller.
  379. */
  381. static inline
  382. void DAC960_ReleaseControllerLock(DAC960_Controller_T *Controller,
  383.   ProcessorFlags_T *ProcessorFlags)
  384. {
  385.   spin_unlock_irqrestore(&io_request_lock, *ProcessorFlags);
  386. }
  389. /*
  390.   DAC960_AcquireControllerLockRF acquires exclusive access to Controller,
  391.   but is only called from the request function with the io_request_lock held.
  392. */
  394. static inline
  395. void DAC960_AcquireControllerLockRF(DAC960_Controller_T *Controller,
  396.     ProcessorFlags_T *ProcessorFlags)
  397. {
  398. }
  401. /*
  402.   DAC960_ReleaseControllerLockRF releases exclusive access to Controller,
  403.   but is only called from the request function with the io_request_lock held.
  404. */
  406. static inline
  407. void DAC960_ReleaseControllerLockRF(DAC960_Controller_T *Controller,
  408.     ProcessorFlags_T *ProcessorFlags)
  409. {
  410. }
  413. /*
  414.   DAC960_AcquireControllerLockIH acquires exclusive access to Controller,
  415.   but is only called from the interrupt handler.
  416. */
  418. static inline
  419. void DAC960_AcquireControllerLockIH(DAC960_Controller_T *Controller,
  420.     ProcessorFlags_T *ProcessorFlags)
  421. {
  422.   spin_lock_irqsave(&io_request_lock, *ProcessorFlags);
  423. }
  426. /*
  427.   DAC960_ReleaseControllerLockIH releases exclusive access to Controller,
  428.   but is only called from the interrupt handler.
  429. */
  431. static inline
  432. void DAC960_ReleaseControllerLockIH(DAC960_Controller_T *Controller,
  433.     ProcessorFlags_T *ProcessorFlags)
  434. {
  435.   spin_unlock_irqrestore(&io_request_lock, *ProcessorFlags);
  436. }
  439. /*
  440.   Virtual_to_Bus32 maps from Kernel Virtual Addresses to 32 Bit PCI Bus
  441.   Addresses.
  442. */
  444. static inline DAC960_BusAddress32_T Virtual_to_Bus32(void *VirtualAddress)
  445. {
  446.   return (DAC960_BusAddress32_T) virt_to_bus(VirtualAddress);
  447. }
  450. /*
  451.   Bus32_to_Virtual maps from 32 Bit PCI Bus Addresses to Kernel Virtual
  452.   Addresses.
  453. */
  455. static inline void *Bus32_to_Virtual(DAC960_BusAddress32_T BusAddress)
  456. {
  457.   return (void *) bus_to_virt(BusAddress);
  458. }
  461. /*
  462.   Virtual_to_Bus64 maps from Kernel Virtual Addresses to 64 Bit PCI Bus
  463.   Addresses.
  464. */
  466. static inline DAC960_BusAddress64_T Virtual_to_Bus64(void *VirtualAddress)
  467. {
  468.   return (DAC960_BusAddress64_T) virt_to_bus(VirtualAddress);
  469. }
  472. /*
  473.   Define the DAC960 BA Series Controller Interface Register Offsets.
  474. */
  476. #define DAC960_BA_RegisterWindowSize 0x80
  478. typedef enum
  479. {
  480.   DAC960_BA_InboundDoorBellRegisterOffset = 0x60,
  481.   DAC960_BA_OutboundDoorBellRegisterOffset = 0x61,
  482.   DAC960_BA_InterruptStatusRegisterOffset = 0x30,
  483.   DAC960_BA_InterruptMaskRegisterOffset = 0x34,
  484.   DAC960_BA_CommandMailboxBusAddressOffset = 0x50,
  485.   DAC960_BA_CommandStatusOffset = 0x58,
  486.   DAC960_BA_ErrorStatusRegisterOffset = 0x63
  487. }
  488. DAC960_BA_RegisterOffsets_T;
  491. /*
  492.   Define the structure of the DAC960 BA Series Inbound Door Bell Register.
  493. */
  495. typedef union DAC960_BA_InboundDoorBellRegister
  496. {
  497.   unsigned char All;
  498.   struct {
  499.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  500.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  501.     boolean GenerateInterrupt:1; /* Bit 2 */
  502.     boolean ControllerReset:1; /* Bit 3 */
  503.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  504.     unsigned char :3; /* Bits 5-7 */
  505.   } Write;
  506.   struct {
  507.     boolean HardwareMailboxEmpty:1; /* Bit 0 */
  508.     boolean InitializationNotInProgress:1; /* Bit 1 */
  509.     unsigned char :6; /* Bits 2-7 */
  510.   } Read;
  511. }
  512. DAC960_BA_InboundDoorBellRegister_T;
  515. /*
  516.   Define the structure of the DAC960 BA Series Outbound Door Bell Register.
  517. */
  519. typedef union DAC960_BA_OutboundDoorBellRegister
  520. {
  521.   unsigned char All;
  522.   struct {
  523.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  524.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  525.     unsigned char :6; /* Bits 2-7 */
  526.   } Write;
  527.   struct {
  528.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  529.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  530.     unsigned char :6; /* Bits 2-7 */
  531.   } Read;
  532. }
  533. DAC960_BA_OutboundDoorBellRegister_T;
  536. /*
  537.   Define the structure of the DAC960 BA Series Interrupt Mask Register.
  538. */
  540. typedef union DAC960_BA_InterruptMaskRegister
  541. {
  542.   unsigned char All;
  543.   struct {
  544.     unsigned int :2; /* Bits 0-1 */
  545.     boolean DisableInterrupts:1; /* Bit 2 */
  546.     boolean DisableInterruptsI2O:1; /* Bit 3 */
  547.     unsigned int :4; /* Bits 4-7 */
  548.   } Bits;
  549. }
  550. DAC960_BA_InterruptMaskRegister_T;
  553. /*
  554.   Define the structure of the DAC960 BA Series Error Status Register.
  555. */
  557. typedef union DAC960_BA_ErrorStatusRegister
  558. {
  559.   unsigned char All;
  560.   struct {
  561.     unsigned int :2; /* Bits 0-1 */
  562.     boolean ErrorStatusPending:1; /* Bit 2 */
  563.     unsigned int :5; /* Bits 3-7 */
  564.   } Bits;
  565. }
  566. DAC960_BA_ErrorStatusRegister_T;
  569. /*
  570.   Define inline functions to provide an abstraction for reading and writing the
  571.   DAC960 BA Series Controller Interface Registers.
  572. */
  574. static inline
  575. void DAC960_BA_HardwareMailboxNewCommand(void *ControllerBaseAddress)
  576. {
  577.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  578.   InboundDoorBellRegister.All = 0;
  579.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  580.   writeb(InboundDoorBellRegister.All,
  581.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  582. }
  584. static inline
  585. void DAC960_BA_AcknowledgeHardwareMailboxStatus(void *ControllerBaseAddress)
  586. {
  587.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  588.   InboundDoorBellRegister.All = 0;
  589.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  590.   writeb(InboundDoorBellRegister.All,
  591.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  592. }
  594. static inline
  595. void DAC960_BA_GenerateInterrupt(void *ControllerBaseAddress)
  596. {
  597.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  598.   InboundDoorBellRegister.All = 0;
  599.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  600.   writeb(InboundDoorBellRegister.All,
  601.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  602. }
  604. static inline
  605. void DAC960_BA_ControllerReset(void *ControllerBaseAddress)
  606. {
  607.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  608.   InboundDoorBellRegister.All = 0;
  609.   InboundDoorBellRegister.Write.ControllerReset = true;
  610.   writeb(InboundDoorBellRegister.All,
  611.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  612. }
  614. static inline
  615. void DAC960_BA_MemoryMailboxNewCommand(void *ControllerBaseAddress)
  616. {
  617.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  618.   InboundDoorBellRegister.All = 0;
  619.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  620.   writeb(InboundDoorBellRegister.All,
  621.  ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  622. }
  624. static inline
  625. boolean DAC960_BA_HardwareMailboxFullP(void *ControllerBaseAddress)
  626. {
  627.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  628.   InboundDoorBellRegister.All =
  629.     readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  630.   return !InboundDoorBellRegister.Read.HardwareMailboxEmpty;
  631. }
  633. static inline
  634. boolean DAC960_BA_InitializationInProgressP(void *ControllerBaseAddress)
  635. {
  636.   DAC960_BA_InboundDoorBellRegister_T InboundDoorBellRegister;
  637.   InboundDoorBellRegister.All =
  638.     readb(ControllerBaseAddress + DAC960_BA_InboundDoorBellRegisterOffset);
  639.   return !InboundDoorBellRegister.Read.InitializationNotInProgress;
  640. }
  642. static inline
  643. void DAC960_BA_AcknowledgeHardwareMailboxInterrupt(void *ControllerBaseAddress)
  644. {
  645.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  646.   OutboundDoorBellRegister.All = 0;
  647.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  648.   writeb(OutboundDoorBellRegister.All,
  649.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  650. }
  652. static inline
  653. void DAC960_BA_AcknowledgeMemoryMailboxInterrupt(void *ControllerBaseAddress)
  654. {
  655.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  656.   OutboundDoorBellRegister.All = 0;
  657.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  658.   writeb(OutboundDoorBellRegister.All,
  659.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  660. }
  662. static inline
  663. void DAC960_BA_AcknowledgeInterrupt(void *ControllerBaseAddress)
  664. {
  665.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  666.   OutboundDoorBellRegister.All = 0;
  667.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  668.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  669.   writeb(OutboundDoorBellRegister.All,
  670.  ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  671. }
  673. static inline
  674. boolean DAC960_BA_HardwareMailboxStatusAvailableP(void *ControllerBaseAddress)
  675. {
  676.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  677.   OutboundDoorBellRegister.All =
  678.     readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  679.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  680. }
  682. static inline
  683. boolean DAC960_BA_MemoryMailboxStatusAvailableP(void *ControllerBaseAddress)
  684. {
  685.   DAC960_BA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  686.   OutboundDoorBellRegister.All =
  687.     readb(ControllerBaseAddress + DAC960_BA_OutboundDoorBellRegisterOffset);
  688.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  689. }
  691. static inline
  692. void DAC960_BA_EnableInterrupts(void *ControllerBaseAddress)
  693. {
  694.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  695.   InterruptMaskRegister.All = 0xFF;
  696.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  697.   InterruptMaskRegister.Bits.DisableInterruptsI2O = true;
  698.   writeb(InterruptMaskRegister.All,
  699.  ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  700. }
  702. static inline
  703. void DAC960_BA_DisableInterrupts(void *ControllerBaseAddress)
  704. {
  705.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  706.   InterruptMaskRegister.All = 0xFF;
  707.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  708.   InterruptMaskRegister.Bits.DisableInterruptsI2O = true;
  709.   writeb(InterruptMaskRegister.All,
  710.  ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  711. }
  713. static inline
  714. boolean DAC960_BA_InterruptsEnabledP(void *ControllerBaseAddress)
  715. {
  716.   DAC960_BA_InterruptMaskRegister_T InterruptMaskRegister;
  717.   InterruptMaskRegister.All =
  718.     readb(ControllerBaseAddress + DAC960_BA_InterruptMaskRegisterOffset);
  719.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  720. }
  722. static inline
  723. void DAC960_BA_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
  724.      *MemoryCommandMailbox,
  725.    DAC960_V2_CommandMailbox_T
  726.      *CommandMailbox)
  727. {
  728.   memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
  729.  sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
  730.   wmb();
  731.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  732.   mb();
  733. }
  735. static inline
  736. void DAC960_BA_WriteHardwareMailbox(void *ControllerBaseAddress,
  737.     DAC960_V2_CommandMailbox_T *CommandMailbox)
  738. {
  739. #ifdef __ia64__
  740.   writeq(Virtual_to_Bus64(CommandMailbox),
  741.  ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset);
  742. #else
  743.   writel(Virtual_to_Bus32(CommandMailbox),
  744.  ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset);
  745. #endif
  746. }
  748. static inline DAC960_V2_CommandIdentifier_T
  749. DAC960_BA_ReadCommandIdentifier(void *ControllerBaseAddress)
  750. {
  751.   return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset);
  752. }
  754. static inline DAC960_V2_CommandStatus_T
  755. DAC960_BA_ReadCommandStatus(void *ControllerBaseAddress)
  756. {
  757.   return readw(ControllerBaseAddress + DAC960_BA_CommandStatusOffset + 2);
  758. }
  760. static inline boolean
  761. DAC960_BA_ReadErrorStatus(void *ControllerBaseAddress,
  762.   unsigned char *ErrorStatus,
  763.   unsigned char *Parameter0,
  764.   unsigned char *Parameter1)
  765. {
  766.   DAC960_BA_ErrorStatusRegister_T ErrorStatusRegister;
  767.   ErrorStatusRegister.All =
  768.     readb(ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset);
  769.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  770.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  771.   *ErrorStatus = ErrorStatusRegister.All;
  772.   *Parameter0 =
  773.     readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 0);
  774.   *Parameter1 =
  775.     readb(ControllerBaseAddress + DAC960_BA_CommandMailboxBusAddressOffset + 1);
  776.   writeb(0xFF, ControllerBaseAddress + DAC960_BA_ErrorStatusRegisterOffset);
  777.   return true;
  778. }
  781. /*
  782.   Define the DAC960 LP Series Controller Interface Register Offsets.
  783. */
  785. #define DAC960_LP_RegisterWindowSize 0x80
  787. typedef enum
  788. {
  789.   DAC960_LP_InboundDoorBellRegisterOffset = 0x20,
  790.   DAC960_LP_OutboundDoorBellRegisterOffset = 0x2C,
  791.   DAC960_LP_InterruptStatusRegisterOffset = 0x30,
  792.   DAC960_LP_InterruptMaskRegisterOffset = 0x34,
  793.   DAC960_LP_CommandMailboxBusAddressOffset = 0x10,
  794.   DAC960_LP_CommandStatusOffset = 0x18,
  795.   DAC960_LP_ErrorStatusRegisterOffset = 0x2E
  796. }
  797. DAC960_LP_RegisterOffsets_T;
  800. /*
  801.   Define the structure of the DAC960 LP Series Inbound Door Bell Register.
  802. */
  804. typedef union DAC960_LP_InboundDoorBellRegister
  805. {
  806.   unsigned char All;
  807.   struct {
  808.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  809.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  810.     boolean GenerateInterrupt:1; /* Bit 2 */
  811.     boolean ControllerReset:1; /* Bit 3 */
  812.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  813.     unsigned char :3; /* Bits 5-7 */
  814.   } Write;
  815.   struct {
  816.     boolean HardwareMailboxFull:1; /* Bit 0 */
  817.     boolean InitializationInProgress:1; /* Bit 1 */
  818.     unsigned char :6; /* Bits 2-7 */
  819.   } Read;
  820. }
  821. DAC960_LP_InboundDoorBellRegister_T;
  824. /*
  825.   Define the structure of the DAC960 LP Series Outbound Door Bell Register.
  826. */
  828. typedef union DAC960_LP_OutboundDoorBellRegister
  829. {
  830.   unsigned char All;
  831.   struct {
  832.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  833.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  834.     unsigned char :6; /* Bits 2-7 */
  835.   } Write;
  836.   struct {
  837.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  838.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  839.     unsigned char :6; /* Bits 2-7 */
  840.   } Read;
  841. }
  842. DAC960_LP_OutboundDoorBellRegister_T;
  845. /*
  846.   Define the structure of the DAC960 LP Series Interrupt Mask Register.
  847. */
  849. typedef union DAC960_LP_InterruptMaskRegister
  850. {
  851.   unsigned char All;
  852.   struct {
  853.     unsigned int :2; /* Bits 0-1 */
  854.     boolean DisableInterrupts:1; /* Bit 2 */
  855.     unsigned int :5; /* Bits 3-7 */
  856.   } Bits;
  857. }
  858. DAC960_LP_InterruptMaskRegister_T;
  861. /*
  862.   Define the structure of the DAC960 LP Series Error Status Register.
  863. */
  865. typedef union DAC960_LP_ErrorStatusRegister
  866. {
  867.   unsigned char All;
  868.   struct {
  869.     unsigned int :2; /* Bits 0-1 */
  870.     boolean ErrorStatusPending:1; /* Bit 2 */
  871.     unsigned int :5; /* Bits 3-7 */
  872.   } Bits;
  873. }
  874. DAC960_LP_ErrorStatusRegister_T;
  877. /*
  878.   Define inline functions to provide an abstraction for reading and writing the
  879.   DAC960 LP Series Controller Interface Registers.
  880. */
  882. static inline
  883. void DAC960_LP_HardwareMailboxNewCommand(void *ControllerBaseAddress)
  884. {
  885.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  886.   InboundDoorBellRegister.All = 0;
  887.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  888.   writeb(InboundDoorBellRegister.All,
  889.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  890. }
  892. static inline
  893. void DAC960_LP_AcknowledgeHardwareMailboxStatus(void *ControllerBaseAddress)
  894. {
  895.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  896.   InboundDoorBellRegister.All = 0;
  897.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  898.   writeb(InboundDoorBellRegister.All,
  899.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  900. }
  902. static inline
  903. void DAC960_LP_GenerateInterrupt(void *ControllerBaseAddress)
  904. {
  905.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  906.   InboundDoorBellRegister.All = 0;
  907.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  908.   writeb(InboundDoorBellRegister.All,
  909.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  910. }
  912. static inline
  913. void DAC960_LP_ControllerReset(void *ControllerBaseAddress)
  914. {
  915.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  916.   InboundDoorBellRegister.All = 0;
  917.   InboundDoorBellRegister.Write.ControllerReset = true;
  918.   writeb(InboundDoorBellRegister.All,
  919.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  920. }
  922. static inline
  923. void DAC960_LP_MemoryMailboxNewCommand(void *ControllerBaseAddress)
  924. {
  925.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  926.   InboundDoorBellRegister.All = 0;
  927.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  928.   writeb(InboundDoorBellRegister.All,
  929.  ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  930. }
  932. static inline
  933. boolean DAC960_LP_HardwareMailboxFullP(void *ControllerBaseAddress)
  934. {
  935.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  936.   InboundDoorBellRegister.All =
  937.     readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  938.   return InboundDoorBellRegister.Read.HardwareMailboxFull;
  939. }
  941. static inline
  942. boolean DAC960_LP_InitializationInProgressP(void *ControllerBaseAddress)
  943. {
  944.   DAC960_LP_InboundDoorBellRegister_T InboundDoorBellRegister;
  945.   InboundDoorBellRegister.All =
  946.     readb(ControllerBaseAddress + DAC960_LP_InboundDoorBellRegisterOffset);
  947.   return InboundDoorBellRegister.Read.InitializationInProgress;
  948. }
  950. static inline
  951. void DAC960_LP_AcknowledgeHardwareMailboxInterrupt(void *ControllerBaseAddress)
  952. {
  953.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  954.   OutboundDoorBellRegister.All = 0;
  955.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  956.   writeb(OutboundDoorBellRegister.All,
  957.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  958. }
  960. static inline
  961. void DAC960_LP_AcknowledgeMemoryMailboxInterrupt(void *ControllerBaseAddress)
  962. {
  963.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  964.   OutboundDoorBellRegister.All = 0;
  965.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  966.   writeb(OutboundDoorBellRegister.All,
  967.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  968. }
  970. static inline
  971. void DAC960_LP_AcknowledgeInterrupt(void *ControllerBaseAddress)
  972. {
  973.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  974.   OutboundDoorBellRegister.All = 0;
  975.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  976.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  977.   writeb(OutboundDoorBellRegister.All,
  978.  ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  979. }
  981. static inline
  982. boolean DAC960_LP_HardwareMailboxStatusAvailableP(void *ControllerBaseAddress)
  983. {
  984.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  985.   OutboundDoorBellRegister.All =
  986.     readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  987.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  988. }
  990. static inline
  991. boolean DAC960_LP_MemoryMailboxStatusAvailableP(void *ControllerBaseAddress)
  992. {
  993.   DAC960_LP_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  994.   OutboundDoorBellRegister.All =
  995.     readb(ControllerBaseAddress + DAC960_LP_OutboundDoorBellRegisterOffset);
  996.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  997. }
  999. static inline
  1000. void DAC960_LP_EnableInterrupts(void *ControllerBaseAddress)
  1001. {
  1002.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1003.   InterruptMaskRegister.All = 0xFF;
  1004.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1005.   writeb(InterruptMaskRegister.All,
  1006.  ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1007. }
  1009. static inline
  1010. void DAC960_LP_DisableInterrupts(void *ControllerBaseAddress)
  1011. {
  1012.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1013.   InterruptMaskRegister.All = 0xFF;
  1014.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1015.   writeb(InterruptMaskRegister.All,
  1016.  ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1017. }
  1019. static inline
  1020. boolean DAC960_LP_InterruptsEnabledP(void *ControllerBaseAddress)
  1021. {
  1022.   DAC960_LP_InterruptMaskRegister_T InterruptMaskRegister;
  1023.   InterruptMaskRegister.All =
  1024.     readb(ControllerBaseAddress + DAC960_LP_InterruptMaskRegisterOffset);
  1025.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1026. }
  1028. static inline
  1029. void DAC960_LP_WriteCommandMailbox(DAC960_V2_CommandMailbox_T
  1030.      *MemoryCommandMailbox,
  1031.    DAC960_V2_CommandMailbox_T
  1032.      *CommandMailbox)
  1033. {
  1034.   memcpy(&MemoryCommandMailbox->Words[1], &CommandMailbox->Words[1],
  1035.  sizeof(DAC960_V2_CommandMailbox_T) - sizeof(unsigned int));
  1036.   wmb();
  1037.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1038.   mb();
  1039. }
  1041. static inline
  1042. void DAC960_LP_WriteHardwareMailbox(void *ControllerBaseAddress,
  1043.     DAC960_V2_CommandMailbox_T *CommandMailbox)
  1044. {
  1045. #ifdef __ia64__
  1046.   writeq(Virtual_to_Bus64(CommandMailbox),
  1047.  ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset);
  1048. #else
  1049.   writel(Virtual_to_Bus32(CommandMailbox),
  1050.  ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset);
  1051. #endif
  1052. }
  1054. static inline DAC960_V2_CommandIdentifier_T
  1055. DAC960_LP_ReadCommandIdentifier(void *ControllerBaseAddress)
  1056. {
  1057.   return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset);
  1058. }
  1060. static inline DAC960_V2_CommandStatus_T
  1061. DAC960_LP_ReadCommandStatus(void *ControllerBaseAddress)
  1062. {
  1063.   return readw(ControllerBaseAddress + DAC960_LP_CommandStatusOffset + 2);
  1064. }
  1066. static inline boolean
  1067. DAC960_LP_ReadErrorStatus(void *ControllerBaseAddress,
  1068.   unsigned char *ErrorStatus,
  1069.   unsigned char *Parameter0,
  1070.   unsigned char *Parameter1)
  1071. {
  1072.   DAC960_LP_ErrorStatusRegister_T ErrorStatusRegister;
  1073.   ErrorStatusRegister.All =
  1074.     readb(ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset);
  1075.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1076.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1077.   *ErrorStatus = ErrorStatusRegister.All;
  1078.   *Parameter0 =
  1079.     readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 0);
  1080.   *Parameter1 =
  1081.     readb(ControllerBaseAddress + DAC960_LP_CommandMailboxBusAddressOffset + 1);
  1082.   writeb(0xFF, ControllerBaseAddress + DAC960_LP_ErrorStatusRegisterOffset);
  1083.   return true;
  1084. }
  1087. /*
  1088.   Define the DAC960 LA Series Controller Interface Register Offsets.
  1089. */
  1091. #define DAC960_LA_RegisterWindowSize 0x80
  1093. typedef enum
  1094. {
  1095.   DAC960_LA_InboundDoorBellRegisterOffset = 0x60,
  1096.   DAC960_LA_OutboundDoorBellRegisterOffset = 0x61,
  1097.   DAC960_LA_InterruptMaskRegisterOffset = 0x34,
  1098.   DAC960_LA_CommandOpcodeRegisterOffset = 0x50,
  1099.   DAC960_LA_CommandIdentifierRegisterOffset = 0x51,
  1100.   DAC960_LA_MailboxRegister2Offset = 0x52,
  1101.   DAC960_LA_MailboxRegister3Offset = 0x53,
  1102.   DAC960_LA_MailboxRegister4Offset = 0x54,
  1103.   DAC960_LA_MailboxRegister5Offset = 0x55,
  1104.   DAC960_LA_MailboxRegister6Offset = 0x56,
  1105.   DAC960_LA_MailboxRegister7Offset = 0x57,
  1106.   DAC960_LA_MailboxRegister8Offset = 0x58,
  1107.   DAC960_LA_MailboxRegister9Offset = 0x59,
  1108.   DAC960_LA_MailboxRegister10Offset = 0x5A,
  1109.   DAC960_LA_MailboxRegister11Offset = 0x5B,
  1110.   DAC960_LA_MailboxRegister12Offset = 0x5C,
  1111.   DAC960_LA_StatusCommandIdentifierRegOffset = 0x5D,
  1112.   DAC960_LA_StatusRegisterOffset = 0x5E,
  1113.   DAC960_LA_ErrorStatusRegisterOffset = 0x63
  1114. }
  1115. DAC960_LA_RegisterOffsets_T;
  1118. /*
  1119.   Define the structure of the DAC960 LA Series Inbound Door Bell Register.
  1120. */
  1122. typedef union DAC960_LA_InboundDoorBellRegister
  1123. {
  1124.   unsigned char All;
  1125.   struct {
  1126.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  1127.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  1128.     boolean GenerateInterrupt:1; /* Bit 2 */
  1129.     boolean ControllerReset:1; /* Bit 3 */
  1130.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  1131.     unsigned char :3; /* Bits 5-7 */
  1132.   } Write;
  1133.   struct {
  1134.     boolean HardwareMailboxEmpty:1; /* Bit 0 */
  1135.     boolean InitializationNotInProgress:1; /* Bit 1 */
  1136.     unsigned char :6; /* Bits 2-7 */
  1137.   } Read;
  1138. }
  1139. DAC960_LA_InboundDoorBellRegister_T;
  1142. /*
  1143.   Define the structure of the DAC960 LA Series Outbound Door Bell Register.
  1144. */
  1146. typedef union DAC960_LA_OutboundDoorBellRegister
  1147. {
  1148.   unsigned char All;
  1149.   struct {
  1150.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  1151.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  1152.     unsigned char :6; /* Bits 2-7 */
  1153.   } Write;
  1154.   struct {
  1155.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  1156.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  1157.     unsigned char :6; /* Bits 2-7 */
  1158.   } Read;
  1159. }
  1160. DAC960_LA_OutboundDoorBellRegister_T;
  1163. /*
  1164.   Define the structure of the DAC960 LA Series Interrupt Mask Register.
  1165. */
  1167. typedef union DAC960_LA_InterruptMaskRegister
  1168. {
  1169.   unsigned char All;
  1170.   struct {
  1171.     unsigned char :2; /* Bits 0-1 */
  1172.     boolean DisableInterrupts:1; /* Bit 2 */
  1173.     unsigned char :5; /* Bits 3-7 */
  1174.   } Bits;
  1175. }
  1176. DAC960_LA_InterruptMaskRegister_T;
  1179. /*
  1180.   Define the structure of the DAC960 LA Series Error Status Register.
  1181. */
  1183. typedef union DAC960_LA_ErrorStatusRegister
  1184. {
  1185.   unsigned char All;
  1186.   struct {
  1187.     unsigned int :2; /* Bits 0-1 */
  1188.     boolean ErrorStatusPending:1; /* Bit 2 */
  1189.     unsigned int :5; /* Bits 3-7 */
  1190.   } Bits;
  1191. }
  1192. DAC960_LA_ErrorStatusRegister_T;
  1195. /*
  1196.   Define inline functions to provide an abstraction for reading and writing the
  1197.   DAC960 LA Series Controller Interface Registers.
  1198. */
  1200. static inline
  1201. void DAC960_LA_HardwareMailboxNewCommand(void *ControllerBaseAddress)
  1202. {
  1203.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1204.   InboundDoorBellRegister.All = 0;
  1205.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  1206.   writeb(InboundDoorBellRegister.All,
  1207.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1208. }
  1210. static inline
  1211. void DAC960_LA_AcknowledgeHardwareMailboxStatus(void *ControllerBaseAddress)
  1212. {
  1213.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1214.   InboundDoorBellRegister.All = 0;
  1215.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  1216.   writeb(InboundDoorBellRegister.All,
  1217.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1218. }
  1220. static inline
  1221. void DAC960_LA_GenerateInterrupt(void *ControllerBaseAddress)
  1222. {
  1223.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1224.   InboundDoorBellRegister.All = 0;
  1225.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1226.   writeb(InboundDoorBellRegister.All,
  1227.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1228. }
  1230. static inline
  1231. void DAC960_LA_ControllerReset(void *ControllerBaseAddress)
  1232. {
  1233.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1234.   InboundDoorBellRegister.All = 0;
  1235.   InboundDoorBellRegister.Write.ControllerReset = true;
  1236.   writeb(InboundDoorBellRegister.All,
  1237.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1238. }
  1240. static inline
  1241. void DAC960_LA_MemoryMailboxNewCommand(void *ControllerBaseAddress)
  1242. {
  1243.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1244.   InboundDoorBellRegister.All = 0;
  1245.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  1246.   writeb(InboundDoorBellRegister.All,
  1247.  ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1248. }
  1250. static inline
  1251. boolean DAC960_LA_HardwareMailboxFullP(void *ControllerBaseAddress)
  1252. {
  1253.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1254.   InboundDoorBellRegister.All =
  1255.     readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1256.   return !InboundDoorBellRegister.Read.HardwareMailboxEmpty;
  1257. }
  1259. static inline
  1260. boolean DAC960_LA_InitializationInProgressP(void *ControllerBaseAddress)
  1261. {
  1262.   DAC960_LA_InboundDoorBellRegister_T InboundDoorBellRegister;
  1263.   InboundDoorBellRegister.All =
  1264.     readb(ControllerBaseAddress + DAC960_LA_InboundDoorBellRegisterOffset);
  1265.   return !InboundDoorBellRegister.Read.InitializationNotInProgress;
  1266. }
  1268. static inline
  1269. void DAC960_LA_AcknowledgeHardwareMailboxInterrupt(void *ControllerBaseAddress)
  1270. {
  1271.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1272.   OutboundDoorBellRegister.All = 0;
  1273.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1274.   writeb(OutboundDoorBellRegister.All,
  1275.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1276. }
  1278. static inline
  1279. void DAC960_LA_AcknowledgeMemoryMailboxInterrupt(void *ControllerBaseAddress)
  1280. {
  1281.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1282.   OutboundDoorBellRegister.All = 0;
  1283.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1284.   writeb(OutboundDoorBellRegister.All,
  1285.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1286. }
  1288. static inline
  1289. void DAC960_LA_AcknowledgeInterrupt(void *ControllerBaseAddress)
  1290. {
  1291.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1292.   OutboundDoorBellRegister.All = 0;
  1293.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1294.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1295.   writeb(OutboundDoorBellRegister.All,
  1296.  ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1297. }
  1299. static inline
  1300. boolean DAC960_LA_HardwareMailboxStatusAvailableP(void *ControllerBaseAddress)
  1301. {
  1302.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1303.   OutboundDoorBellRegister.All =
  1304.     readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1305.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  1306. }
  1308. static inline
  1309. boolean DAC960_LA_MemoryMailboxStatusAvailableP(void *ControllerBaseAddress)
  1310. {
  1311.   DAC960_LA_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1312.   OutboundDoorBellRegister.All =
  1313.     readb(ControllerBaseAddress + DAC960_LA_OutboundDoorBellRegisterOffset);
  1314.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  1315. }
  1317. static inline
  1318. void DAC960_LA_EnableInterrupts(void *ControllerBaseAddress)
  1319. {
  1320.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1321.   InterruptMaskRegister.All = 0xFF;
  1322.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1323.   writeb(InterruptMaskRegister.All,
  1324.  ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1325. }
  1327. static inline
  1328. void DAC960_LA_DisableInterrupts(void *ControllerBaseAddress)
  1329. {
  1330.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1331.   InterruptMaskRegister.All = 0xFF;
  1332.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1333.   writeb(InterruptMaskRegister.All,
  1334.  ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1335. }
  1337. static inline
  1338. boolean DAC960_LA_InterruptsEnabledP(void *ControllerBaseAddress)
  1339. {
  1340.   DAC960_LA_InterruptMaskRegister_T InterruptMaskRegister;
  1341.   InterruptMaskRegister.All =
  1342.     readb(ControllerBaseAddress + DAC960_LA_InterruptMaskRegisterOffset);
  1343.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1344. }
  1346. static inline
  1347. void DAC960_LA_WriteCommandMailbox(DAC960_V1_CommandMailbox_T
  1348.      *MemoryCommandMailbox,
  1349.    DAC960_V1_CommandMailbox_T
  1350.      *CommandMailbox)
  1351. {
  1352.   MemoryCommandMailbox->Words[1] = CommandMailbox->Words[1];
  1353.   MemoryCommandMailbox->Words[2] = CommandMailbox->Words[2];
  1354.   MemoryCommandMailbox->Words[3] = CommandMailbox->Words[3];
  1355.   wmb();
  1356.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1357.   mb();
  1358. }
  1360. static inline
  1361. void DAC960_LA_WriteHardwareMailbox(void *ControllerBaseAddress,
  1362.     DAC960_V1_CommandMailbox_T *CommandMailbox)
  1363. {
  1364.   writel(CommandMailbox->Words[0],
  1365.  ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset);
  1366.   writel(CommandMailbox->Words[1],
  1367.  ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset);
  1368.   writel(CommandMailbox->Words[2],
  1369.  ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset);
  1370.   writeb(CommandMailbox->Bytes[12],
  1371.  ControllerBaseAddress + DAC960_LA_MailboxRegister12Offset);
  1372. }
  1374. static inline DAC960_V1_CommandIdentifier_T
  1375. DAC960_LA_ReadStatusCommandIdentifier(void *ControllerBaseAddress)
  1376. {
  1377.   return readb(ControllerBaseAddress
  1378.        + DAC960_LA_StatusCommandIdentifierRegOffset);
  1379. }
  1381. static inline DAC960_V1_CommandStatus_T
  1382. DAC960_LA_ReadStatusRegister(void *ControllerBaseAddress)
  1383. {
  1384.   return readw(ControllerBaseAddress + DAC960_LA_StatusRegisterOffset);
  1385. }
  1387. static inline boolean
  1388. DAC960_LA_ReadErrorStatus(void *ControllerBaseAddress,
  1389.   unsigned char *ErrorStatus,
  1390.   unsigned char *Parameter0,
  1391.   unsigned char *Parameter1)
  1392. {
  1393.   DAC960_LA_ErrorStatusRegister_T ErrorStatusRegister;
  1394.   ErrorStatusRegister.All =
  1395.     readb(ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset);
  1396.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1397.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1398.   *ErrorStatus = ErrorStatusRegister.All;
  1399.   *Parameter0 =
  1400.     readb(ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset);
  1401.   *Parameter1 =
  1402.     readb(ControllerBaseAddress + DAC960_LA_CommandIdentifierRegisterOffset);
  1403.   writeb(0xFF, ControllerBaseAddress + DAC960_LA_ErrorStatusRegisterOffset);
  1404.   return true;
  1405. }
  1407. static inline
  1408. void DAC960_LA_SaveMemoryMailboxInfo(DAC960_Controller_T *Controller)
  1409. {
  1410. #ifdef __i386__
  1411.   void *ControllerBaseAddress = Controller->BaseAddress;
  1412.   writel(0x743C485E,
  1413.  ControllerBaseAddress + DAC960_LA_CommandOpcodeRegisterOffset);
  1414.   writel((unsigned long) Controller->V1.FirstCommandMailbox,
  1415.  ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset);
  1416.   writew(Controller->V1.NextCommandMailbox - Controller->V1.FirstCommandMailbox,
  1417.  ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset);
  1418.   writew(Controller->V1.NextStatusMailbox - Controller->V1.FirstStatusMailbox,
  1419.  ControllerBaseAddress + DAC960_LA_MailboxRegister10Offset);
  1420. #endif
  1421. }
  1423. static inline
  1424. void DAC960_LA_RestoreMemoryMailboxInfo(DAC960_Controller_T *Controller,
  1425. void **MemoryMailboxAddress,
  1426. short *NextCommandMailboxIndex,
  1427. short *NextStatusMailboxIndex)
  1428. {
  1429. #ifdef __i386__
  1430.   void *ControllerBaseAddress = Controller->BaseAddress;
  1431.   if (readl(ControllerBaseAddress
  1432.     + DAC960_LA_CommandOpcodeRegisterOffset) != 0x743C485E)
  1433.     return;
  1434.   *MemoryMailboxAddress =
  1435.     (void *) readl(ControllerBaseAddress + DAC960_LA_MailboxRegister4Offset);
  1436.   *NextCommandMailboxIndex =
  1437.     readw(ControllerBaseAddress + DAC960_LA_MailboxRegister8Offset);
  1438.   *NextStatusMailboxIndex =
  1439.     readw(ControllerBaseAddress + DAC960_LA_MailboxRegister10Offset);
  1440. #endif
  1441. }
  1444. /*
  1445.   Define the DAC960 PG Series Controller Interface Register Offsets.
  1446. */
  1448. #define DAC960_PG_RegisterWindowSize 0x2000
  1450. typedef enum
  1451. {
  1452.   DAC960_PG_InboundDoorBellRegisterOffset = 0x0020,
  1453.   DAC960_PG_OutboundDoorBellRegisterOffset = 0x002C,
  1454.   DAC960_PG_InterruptMaskRegisterOffset = 0x0034,
  1455.   DAC960_PG_CommandOpcodeRegisterOffset = 0x1000,
  1456.   DAC960_PG_CommandIdentifierRegisterOffset = 0x1001,
  1457.   DAC960_PG_MailboxRegister2Offset = 0x1002,
  1458.   DAC960_PG_MailboxRegister3Offset = 0x1003,
  1459.   DAC960_PG_MailboxRegister4Offset = 0x1004,
  1460.   DAC960_PG_MailboxRegister5Offset = 0x1005,
  1461.   DAC960_PG_MailboxRegister6Offset = 0x1006,
  1462.   DAC960_PG_MailboxRegister7Offset = 0x1007,
  1463.   DAC960_PG_MailboxRegister8Offset = 0x1008,
  1464.   DAC960_PG_MailboxRegister9Offset = 0x1009,
  1465.   DAC960_PG_MailboxRegister10Offset = 0x100A,
  1466.   DAC960_PG_MailboxRegister11Offset = 0x100B,
  1467.   DAC960_PG_MailboxRegister12Offset = 0x100C,
  1468.   DAC960_PG_StatusCommandIdentifierRegOffset = 0x1018,
  1469.   DAC960_PG_StatusRegisterOffset = 0x101A,
  1470.   DAC960_PG_ErrorStatusRegisterOffset = 0x103F
  1471. }
  1472. DAC960_PG_RegisterOffsets_T;
  1475. /*
  1476.   Define the structure of the DAC960 PG Series Inbound Door Bell Register.
  1477. */
  1479. typedef union DAC960_PG_InboundDoorBellRegister
  1480. {
  1481.   unsigned int All;
  1482.   struct {
  1483.     boolean HardwareMailboxNewCommand:1; /* Bit 0 */
  1484.     boolean AcknowledgeHardwareMailboxStatus:1; /* Bit 1 */
  1485.     boolean GenerateInterrupt:1; /* Bit 2 */
  1486.     boolean ControllerReset:1; /* Bit 3 */
  1487.     boolean MemoryMailboxNewCommand:1; /* Bit 4 */
  1488.     unsigned int :27; /* Bits 5-31 */
  1489.   } Write;
  1490.   struct {
  1491.     boolean HardwareMailboxFull:1; /* Bit 0 */
  1492.     boolean InitializationInProgress:1; /* Bit 1 */
  1493.     unsigned int :30; /* Bits 2-31 */
  1494.   } Read;
  1495. }
  1496. DAC960_PG_InboundDoorBellRegister_T;
  1499. /*
  1500.   Define the structure of the DAC960 PG Series Outbound Door Bell Register.
  1501. */
  1503. typedef union DAC960_PG_OutboundDoorBellRegister
  1504. {
  1505.   unsigned int All;
  1506.   struct {
  1507.     boolean AcknowledgeHardwareMailboxInterrupt:1; /* Bit 0 */
  1508.     boolean AcknowledgeMemoryMailboxInterrupt:1; /* Bit 1 */
  1509.     unsigned int :30; /* Bits 2-31 */
  1510.   } Write;
  1511.   struct {
  1512.     boolean HardwareMailboxStatusAvailable:1; /* Bit 0 */
  1513.     boolean MemoryMailboxStatusAvailable:1; /* Bit 1 */
  1514.     unsigned int :30; /* Bits 2-31 */
  1515.   } Read;
  1516. }
  1517. DAC960_PG_OutboundDoorBellRegister_T;
  1520. /*
  1521.   Define the structure of the DAC960 PG Series Interrupt Mask Register.
  1522. */
  1524. typedef union DAC960_PG_InterruptMaskRegister
  1525. {
  1526.   unsigned int All;
  1527.   struct {
  1528.     unsigned int MessageUnitInterruptMask1:2; /* Bits 0-1 */
  1529.     boolean DisableInterrupts:1; /* Bit 2 */
  1530.     unsigned int MessageUnitInterruptMask2:5; /* Bits 3-7 */
  1531.     unsigned int Reserved0:24; /* Bits 8-31 */
  1532.   } Bits;
  1533. }
  1534. DAC960_PG_InterruptMaskRegister_T;
  1537. /*
  1538.   Define the structure of the DAC960 PG Series Error Status Register.
  1539. */
  1541. typedef union DAC960_PG_ErrorStatusRegister
  1542. {
  1543.   unsigned char All;
  1544.   struct {
  1545.     unsigned int :2; /* Bits 0-1 */
  1546.     boolean ErrorStatusPending:1; /* Bit 2 */
  1547.     unsigned int :5; /* Bits 3-7 */
  1548.   } Bits;
  1549. }
  1550. DAC960_PG_ErrorStatusRegister_T;
  1553. /*
  1554.   Define inline functions to provide an abstraction for reading and writing the
  1555.   DAC960 PG Series Controller Interface Registers.
  1556. */
  1558. static inline
  1559. void DAC960_PG_HardwareMailboxNewCommand(void *ControllerBaseAddress)
  1560. {
  1561.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1562.   InboundDoorBellRegister.All = 0;
  1563.   InboundDoorBellRegister.Write.HardwareMailboxNewCommand = true;
  1564.   writel(InboundDoorBellRegister.All,
  1565.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1566. }
  1568. static inline
  1569. void DAC960_PG_AcknowledgeHardwareMailboxStatus(void *ControllerBaseAddress)
  1570. {
  1571.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1572.   InboundDoorBellRegister.All = 0;
  1573.   InboundDoorBellRegister.Write.AcknowledgeHardwareMailboxStatus = true;
  1574.   writel(InboundDoorBellRegister.All,
  1575.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1576. }
  1578. static inline
  1579. void DAC960_PG_GenerateInterrupt(void *ControllerBaseAddress)
  1580. {
  1581.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1582.   InboundDoorBellRegister.All = 0;
  1583.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1584.   writel(InboundDoorBellRegister.All,
  1585.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1586. }
  1588. static inline
  1589. void DAC960_PG_ControllerReset(void *ControllerBaseAddress)
  1590. {
  1591.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1592.   InboundDoorBellRegister.All = 0;
  1593.   InboundDoorBellRegister.Write.ControllerReset = true;
  1594.   writel(InboundDoorBellRegister.All,
  1595.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1596. }
  1598. static inline
  1599. void DAC960_PG_MemoryMailboxNewCommand(void *ControllerBaseAddress)
  1600. {
  1601.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1602.   InboundDoorBellRegister.All = 0;
  1603.   InboundDoorBellRegister.Write.MemoryMailboxNewCommand = true;
  1604.   writel(InboundDoorBellRegister.All,
  1605.  ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1606. }
  1608. static inline
  1609. boolean DAC960_PG_HardwareMailboxFullP(void *ControllerBaseAddress)
  1610. {
  1611.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1612.   InboundDoorBellRegister.All =
  1613.     readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1614.   return InboundDoorBellRegister.Read.HardwareMailboxFull;
  1615. }
  1617. static inline
  1618. boolean DAC960_PG_InitializationInProgressP(void *ControllerBaseAddress)
  1619. {
  1620.   DAC960_PG_InboundDoorBellRegister_T InboundDoorBellRegister;
  1621.   InboundDoorBellRegister.All =
  1622.     readl(ControllerBaseAddress + DAC960_PG_InboundDoorBellRegisterOffset);
  1623.   return InboundDoorBellRegister.Read.InitializationInProgress;
  1624. }
  1626. static inline
  1627. void DAC960_PG_AcknowledgeHardwareMailboxInterrupt(void *ControllerBaseAddress)
  1628. {
  1629.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1630.   OutboundDoorBellRegister.All = 0;
  1631.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1632.   writel(OutboundDoorBellRegister.All,
  1633.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1634. }
  1636. static inline
  1637. void DAC960_PG_AcknowledgeMemoryMailboxInterrupt(void *ControllerBaseAddress)
  1638. {
  1639.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1640.   OutboundDoorBellRegister.All = 0;
  1641.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1642.   writel(OutboundDoorBellRegister.All,
  1643.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1644. }
  1646. static inline
  1647. void DAC960_PG_AcknowledgeInterrupt(void *ControllerBaseAddress)
  1648. {
  1649.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1650.   OutboundDoorBellRegister.All = 0;
  1651.   OutboundDoorBellRegister.Write.AcknowledgeHardwareMailboxInterrupt = true;
  1652.   OutboundDoorBellRegister.Write.AcknowledgeMemoryMailboxInterrupt = true;
  1653.   writel(OutboundDoorBellRegister.All,
  1654.  ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1655. }
  1657. static inline
  1658. boolean DAC960_PG_HardwareMailboxStatusAvailableP(void *ControllerBaseAddress)
  1659. {
  1660.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1661.   OutboundDoorBellRegister.All =
  1662.     readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1663.   return OutboundDoorBellRegister.Read.HardwareMailboxStatusAvailable;
  1664. }
  1666. static inline
  1667. boolean DAC960_PG_MemoryMailboxStatusAvailableP(void *ControllerBaseAddress)
  1668. {
  1669.   DAC960_PG_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1670.   OutboundDoorBellRegister.All =
  1671.     readl(ControllerBaseAddress + DAC960_PG_OutboundDoorBellRegisterOffset);
  1672.   return OutboundDoorBellRegister.Read.MemoryMailboxStatusAvailable;
  1673. }
  1675. static inline
  1676. void DAC960_PG_EnableInterrupts(void *ControllerBaseAddress)
  1677. {
  1678.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1679.   InterruptMaskRegister.All = 0;
  1680.   InterruptMaskRegister.Bits.MessageUnitInterruptMask1 = 0x3;
  1681.   InterruptMaskRegister.Bits.DisableInterrupts = false;
  1682.   InterruptMaskRegister.Bits.MessageUnitInterruptMask2 = 0x1F;
  1683.   writel(InterruptMaskRegister.All,
  1684.  ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1685. }
  1687. static inline
  1688. void DAC960_PG_DisableInterrupts(void *ControllerBaseAddress)
  1689. {
  1690.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1691.   InterruptMaskRegister.All = 0;
  1692.   InterruptMaskRegister.Bits.MessageUnitInterruptMask1 = 0x3;
  1693.   InterruptMaskRegister.Bits.DisableInterrupts = true;
  1694.   InterruptMaskRegister.Bits.MessageUnitInterruptMask2 = 0x1F;
  1695.   writel(InterruptMaskRegister.All,
  1696.  ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1697. }
  1699. static inline
  1700. boolean DAC960_PG_InterruptsEnabledP(void *ControllerBaseAddress)
  1701. {
  1702.   DAC960_PG_InterruptMaskRegister_T InterruptMaskRegister;
  1703.   InterruptMaskRegister.All =
  1704.     readl(ControllerBaseAddress + DAC960_PG_InterruptMaskRegisterOffset);
  1705.   return !InterruptMaskRegister.Bits.DisableInterrupts;
  1706. }
  1708. static inline
  1709. void DAC960_PG_WriteCommandMailbox(DAC960_V1_CommandMailbox_T
  1710.      *MemoryCommandMailbox,
  1711.    DAC960_V1_CommandMailbox_T
  1712.      *CommandMailbox)
  1713. {
  1714.   MemoryCommandMailbox->Words[1] = CommandMailbox->Words[1];
  1715.   MemoryCommandMailbox->Words[2] = CommandMailbox->Words[2];
  1716.   MemoryCommandMailbox->Words[3] = CommandMailbox->Words[3];
  1717.   wmb();
  1718.   MemoryCommandMailbox->Words[0] = CommandMailbox->Words[0];
  1719.   mb();
  1720. }
  1722. static inline
  1723. void DAC960_PG_WriteHardwareMailbox(void *ControllerBaseAddress,
  1724.     DAC960_V1_CommandMailbox_T *CommandMailbox)
  1725. {
  1726.   writel(CommandMailbox->Words[0],
  1727.  ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset);
  1728.   writel(CommandMailbox->Words[1],
  1729.  ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset);
  1730.   writel(CommandMailbox->Words[2],
  1731.  ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset);
  1732.   writeb(CommandMailbox->Bytes[12],
  1733.  ControllerBaseAddress + DAC960_PG_MailboxRegister12Offset);
  1734. }
  1736. static inline DAC960_V1_CommandIdentifier_T
  1737. DAC960_PG_ReadStatusCommandIdentifier(void *ControllerBaseAddress)
  1738. {
  1739.   return readb(ControllerBaseAddress
  1740.        + DAC960_PG_StatusCommandIdentifierRegOffset);
  1741. }
  1743. static inline DAC960_V1_CommandStatus_T
  1744. DAC960_PG_ReadStatusRegister(void *ControllerBaseAddress)
  1745. {
  1746.   return readw(ControllerBaseAddress + DAC960_PG_StatusRegisterOffset);
  1747. }
  1749. static inline boolean
  1750. DAC960_PG_ReadErrorStatus(void *ControllerBaseAddress,
  1751.   unsigned char *ErrorStatus,
  1752.   unsigned char *Parameter0,
  1753.   unsigned char *Parameter1)
  1754. {
  1755.   DAC960_PG_ErrorStatusRegister_T ErrorStatusRegister;
  1756.   ErrorStatusRegister.All =
  1757.     readb(ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset);
  1758.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  1759.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  1760.   *ErrorStatus = ErrorStatusRegister.All;
  1761.   *Parameter0 =
  1762.     readb(ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset);
  1763.   *Parameter1 =
  1764.     readb(ControllerBaseAddress + DAC960_PG_CommandIdentifierRegisterOffset);
  1765.   writeb(0, ControllerBaseAddress + DAC960_PG_ErrorStatusRegisterOffset);
  1766.   return true;
  1767. }
  1769. static inline
  1770. void DAC960_PG_SaveMemoryMailboxInfo(DAC960_Controller_T *Controller)
  1771. {
  1772. #ifdef __i386__
  1773.   void *ControllerBaseAddress = Controller->BaseAddress;
  1774.   writel(0x743C485E,
  1775.  ControllerBaseAddress + DAC960_PG_CommandOpcodeRegisterOffset);
  1776.   writel((unsigned long) Controller->V1.FirstCommandMailbox,
  1777.  ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset);
  1778.   writew(Controller->V1.NextCommandMailbox - Controller->V1.FirstCommandMailbox,
  1779.  ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset);
  1780.   writew(Controller->V1.NextStatusMailbox - Controller->V1.FirstStatusMailbox,
  1781.  ControllerBaseAddress + DAC960_PG_MailboxRegister10Offset);
  1782. #endif
  1783. }
  1785. static inline
  1786. void DAC960_PG_RestoreMemoryMailboxInfo(DAC960_Controller_T *Controller,
  1787. void **MemoryMailboxAddress,
  1788. short *NextCommandMailboxIndex,
  1789. short *NextStatusMailboxIndex)
  1790. {
  1791. #ifdef __i386__
  1792.   void *ControllerBaseAddress = Controller->BaseAddress;
  1793.   if (readl(ControllerBaseAddress
  1794.     + DAC960_PG_CommandOpcodeRegisterOffset) != 0x743C485E)
  1795.     return;
  1796.   *MemoryMailboxAddress =
  1797.     (void *) readl(ControllerBaseAddress + DAC960_PG_MailboxRegister4Offset);
  1798.   *NextCommandMailboxIndex =
  1799.     readw(ControllerBaseAddress + DAC960_PG_MailboxRegister8Offset);
  1800.   *NextStatusMailboxIndex =
  1801.     readw(ControllerBaseAddress + DAC960_PG_MailboxRegister10Offset);
  1802. #endif
  1803. }
  1806. /*
  1807.   Define the DAC960 PD Series Controller Interface Register Offsets.
  1808. */
  1810. #define DAC960_PD_RegisterWindowSize 0x80
  1812. typedef enum
  1813. {
  1814.   DAC960_PD_CommandOpcodeRegisterOffset = 0x00,
  1815.   DAC960_PD_CommandIdentifierRegisterOffset = 0x01,
  1816.   DAC960_PD_MailboxRegister2Offset = 0x02,
  1817.   DAC960_PD_MailboxRegister3Offset = 0x03,
  1818.   DAC960_PD_MailboxRegister4Offset = 0x04,
  1819.   DAC960_PD_MailboxRegister5Offset = 0x05,
  1820.   DAC960_PD_MailboxRegister6Offset = 0x06,
  1821.   DAC960_PD_MailboxRegister7Offset = 0x07,
  1822.   DAC960_PD_MailboxRegister8Offset = 0x08,
  1823.   DAC960_PD_MailboxRegister9Offset = 0x09,
  1824.   DAC960_PD_MailboxRegister10Offset = 0x0A,
  1825.   DAC960_PD_MailboxRegister11Offset = 0x0B,
  1826.   DAC960_PD_MailboxRegister12Offset = 0x0C,
  1827.   DAC960_PD_StatusCommandIdentifierRegOffset = 0x0D,
  1828.   DAC960_PD_StatusRegisterOffset = 0x0E,
  1829.   DAC960_PD_ErrorStatusRegisterOffset = 0x3F,
  1830.   DAC960_PD_InboundDoorBellRegisterOffset = 0x40,
  1831.   DAC960_PD_OutboundDoorBellRegisterOffset = 0x41,
  1832.   DAC960_PD_InterruptEnableRegisterOffset = 0x43
  1833. }
  1834. DAC960_PD_RegisterOffsets_T;
  1837. /*
  1838.   Define the structure of the DAC960 PD Series Inbound Door Bell Register.
  1839. */
  1841. typedef union DAC960_PD_InboundDoorBellRegister
  1842. {
  1843.   unsigned char All;
  1844.   struct {
  1845.     boolean NewCommand:1; /* Bit 0 */
  1846.     boolean AcknowledgeStatus:1; /* Bit 1 */
  1847.     boolean GenerateInterrupt:1; /* Bit 2 */
  1848.     boolean ControllerReset:1; /* Bit 3 */
  1849.     unsigned char :4; /* Bits 4-7 */
  1850.   } Write;
  1851.   struct {
  1852.     boolean MailboxFull:1; /* Bit 0 */
  1853.     boolean InitializationInProgress:1; /* Bit 1 */
  1854.     unsigned char :6; /* Bits 2-7 */
  1855.   } Read;
  1856. }
  1857. DAC960_PD_InboundDoorBellRegister_T;
  1860. /*
  1861.   Define the structure of the DAC960 PD Series Outbound Door Bell Register.
  1862. */
  1864. typedef union DAC960_PD_OutboundDoorBellRegister
  1865. {
  1866.   unsigned char All;
  1867.   struct {
  1868.     boolean AcknowledgeInterrupt:1; /* Bit 0 */
  1869.     unsigned char :7; /* Bits 1-7 */
  1870.   } Write;
  1871.   struct {
  1872.     boolean StatusAvailable:1; /* Bit 0 */
  1873.     unsigned char :7; /* Bits 1-7 */
  1874.   } Read;
  1875. }
  1876. DAC960_PD_OutboundDoorBellRegister_T;
  1879. /*
  1880.   Define the structure of the DAC960 PD Series Interrupt Enable Register.
  1881. */
  1883. typedef union DAC960_PD_InterruptEnableRegister
  1884. {
  1885.   unsigned char All;
  1886.   struct {
  1887.     boolean EnableInterrupts:1; /* Bit 0 */
  1888.     unsigned char :7; /* Bits 1-7 */
  1889.   } Bits;
  1890. }
  1891. DAC960_PD_InterruptEnableRegister_T;
  1894. /*
  1895.   Define the structure of the DAC960 PD Series Error Status Register.
  1896. */
  1898. typedef union DAC960_PD_ErrorStatusRegister
  1899. {
  1900.   unsigned char All;
  1901.   struct {
  1902.     unsigned int :2; /* Bits 0-1 */
  1903.     boolean ErrorStatusPending:1; /* Bit 2 */
  1904.     unsigned int :5; /* Bits 3-7 */
  1905.   } Bits;
  1906. }
  1907. DAC960_PD_ErrorStatusRegister_T;
  1910. /*
  1911.   Define inline functions to provide an abstraction for reading and writing the
  1912.   DAC960 PD Series Controller Interface Registers.
  1913. */
  1915. static inline
  1916. void DAC960_PD_NewCommand(void *ControllerBaseAddress)
  1917. {
  1918.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1919.   InboundDoorBellRegister.All = 0;
  1920.   InboundDoorBellRegister.Write.NewCommand = true;
  1921.   writeb(InboundDoorBellRegister.All,
  1922.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1923. }
  1925. static inline
  1926. void DAC960_PD_AcknowledgeStatus(void *ControllerBaseAddress)
  1927. {
  1928.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1929.   InboundDoorBellRegister.All = 0;
  1930.   InboundDoorBellRegister.Write.AcknowledgeStatus = true;
  1931.   writeb(InboundDoorBellRegister.All,
  1932.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1933. }
  1935. static inline
  1936. void DAC960_PD_GenerateInterrupt(void *ControllerBaseAddress)
  1937. {
  1938.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1939.   InboundDoorBellRegister.All = 0;
  1940.   InboundDoorBellRegister.Write.GenerateInterrupt = true;
  1941.   writeb(InboundDoorBellRegister.All,
  1942.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1943. }
  1945. static inline
  1946. void DAC960_PD_ControllerReset(void *ControllerBaseAddress)
  1947. {
  1948.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1949.   InboundDoorBellRegister.All = 0;
  1950.   InboundDoorBellRegister.Write.ControllerReset = true;
  1951.   writeb(InboundDoorBellRegister.All,
  1952.  ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1953. }
  1955. static inline
  1956. boolean DAC960_PD_MailboxFullP(void *ControllerBaseAddress)
  1957. {
  1958.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1959.   InboundDoorBellRegister.All =
  1960.     readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1961.   return InboundDoorBellRegister.Read.MailboxFull;
  1962. }
  1964. static inline
  1965. boolean DAC960_PD_InitializationInProgressP(void *ControllerBaseAddress)
  1966. {
  1967.   DAC960_PD_InboundDoorBellRegister_T InboundDoorBellRegister;
  1968.   InboundDoorBellRegister.All =
  1969.     readb(ControllerBaseAddress + DAC960_PD_InboundDoorBellRegisterOffset);
  1970.   return InboundDoorBellRegister.Read.InitializationInProgress;
  1971. }
  1973. static inline
  1974. void DAC960_PD_AcknowledgeInterrupt(void *ControllerBaseAddress)
  1975. {
  1976.   DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1977.   OutboundDoorBellRegister.All = 0;
  1978.   OutboundDoorBellRegister.Write.AcknowledgeInterrupt = true;
  1979.   writeb(OutboundDoorBellRegister.All,
  1980.  ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset);
  1981. }
  1983. static inline
  1984. boolean DAC960_PD_StatusAvailableP(void *ControllerBaseAddress)
  1985. {
  1986.   DAC960_PD_OutboundDoorBellRegister_T OutboundDoorBellRegister;
  1987.   OutboundDoorBellRegister.All =
  1988.     readb(ControllerBaseAddress + DAC960_PD_OutboundDoorBellRegisterOffset);
  1989.   return OutboundDoorBellRegister.Read.StatusAvailable;
  1990. }
  1992. static inline
  1993. void DAC960_PD_EnableInterrupts(void *ControllerBaseAddress)
  1994. {
  1995.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  1996.   InterruptEnableRegister.All = 0;
  1997.   InterruptEnableRegister.Bits.EnableInterrupts = true;
  1998.   writeb(InterruptEnableRegister.All,
  1999.  ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2000. }
  2002. static inline
  2003. void DAC960_PD_DisableInterrupts(void *ControllerBaseAddress)
  2004. {
  2005.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  2006.   InterruptEnableRegister.All = 0;
  2007.   InterruptEnableRegister.Bits.EnableInterrupts = false;
  2008.   writeb(InterruptEnableRegister.All,
  2009.  ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2010. }
  2012. static inline
  2013. boolean DAC960_PD_InterruptsEnabledP(void *ControllerBaseAddress)
  2014. {
  2015.   DAC960_PD_InterruptEnableRegister_T InterruptEnableRegister;
  2016.   InterruptEnableRegister.All =
  2017.     readb(ControllerBaseAddress + DAC960_PD_InterruptEnableRegisterOffset);
  2018.   return InterruptEnableRegister.Bits.EnableInterrupts;
  2019. }
  2021. static inline
  2022. void DAC960_PD_WriteCommandMailbox(void *ControllerBaseAddress,
  2023.    DAC960_V1_CommandMailbox_T *CommandMailbox)
  2024. {
  2025.   writel(CommandMailbox->Words[0],
  2026.  ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset);
  2027.   writel(CommandMailbox->Words[1],
  2028.  ControllerBaseAddress + DAC960_PD_MailboxRegister4Offset);
  2029.   writel(CommandMailbox->Words[2],
  2030.  ControllerBaseAddress + DAC960_PD_MailboxRegister8Offset);
  2031.   writeb(CommandMailbox->Bytes[12],
  2032.  ControllerBaseAddress + DAC960_PD_MailboxRegister12Offset);
  2033. }
  2035. static inline DAC960_V1_CommandIdentifier_T
  2036. DAC960_PD_ReadStatusCommandIdentifier(void *ControllerBaseAddress)
  2037. {
  2038.   return readb(ControllerBaseAddress
  2039.        + DAC960_PD_StatusCommandIdentifierRegOffset);
  2040. }
  2042. static inline DAC960_V1_CommandStatus_T
  2043. DAC960_PD_ReadStatusRegister(void *ControllerBaseAddress)
  2044. {
  2045.   return readw(ControllerBaseAddress + DAC960_PD_StatusRegisterOffset);
  2046. }
  2048. static inline boolean
  2049. DAC960_PD_ReadErrorStatus(void *ControllerBaseAddress,
  2050.   unsigned char *ErrorStatus,
  2051.   unsigned char *Parameter0,
  2052.   unsigned char *Parameter1)
  2053. {
  2054.   DAC960_PD_ErrorStatusRegister_T ErrorStatusRegister;
  2055.   ErrorStatusRegister.All =
  2056.     readb(ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset);
  2057.   if (!ErrorStatusRegister.Bits.ErrorStatusPending) return false;
  2058.   ErrorStatusRegister.Bits.ErrorStatusPending = false;
  2059.   *ErrorStatus = ErrorStatusRegister.All;
  2060.   *Parameter0 =
  2061.     readb(ControllerBaseAddress + DAC960_PD_CommandOpcodeRegisterOffset);
  2062.   *Parameter1 =
  2063.     readb(ControllerBaseAddress + DAC960_PD_CommandIdentifierRegisterOffset);
  2064.   writeb(0, ControllerBaseAddress + DAC960_PD_ErrorStatusRegisterOffset);
  2065.   return true;
  2066. }
  2068. static inline void DAC960_P_To_PD_TranslateEnquiry(void *Enquiry)
  2069. {
  2070.   memcpy(Enquiry + 132, Enquiry + 36, 64);
  2071.   memset(Enquiry + 36, 0, 96);
  2072. }
  2074. static inline void DAC960_P_To_PD_TranslateDeviceState(void *DeviceState)
  2075. {
  2076.   memcpy(DeviceState + 2, DeviceState + 3, 1);
  2077.   memcpy(DeviceState + 4, DeviceState + 5, 2);
  2078.   memcpy(DeviceState + 6, DeviceState + 8, 4);
  2079. }
  2081. static inline
  2082. void DAC960_PD_To_P_TranslateReadWriteCommand(DAC960_V1_CommandMailbox_T
  2083.       *CommandMailbox)
  2084. {
  2085.   int LogicalDriveNumber = CommandMailbox->Type5.LD.LogicalDriveNumber;
  2086.   CommandMailbox->Bytes[3] &= 0x7;
  2087.   CommandMailbox->Bytes[3] |= CommandMailbox->Bytes[7] << 6;
  2088.   CommandMailbox->Bytes[7] = LogicalDriveNumber;
  2089. }
  2091. static inline
  2092. void DAC960_P_To_PD_TranslateReadWriteCommand(DAC960_V1_CommandMailbox_T
  2093.       *CommandMailbox)
  2094. {
  2095.   int LogicalDriveNumber = CommandMailbox->Bytes[7];
  2096.   CommandMailbox->Bytes[7] = CommandMailbox->Bytes[3] >> 6;
  2097.   CommandMailbox->Bytes[3] &= 0x7;
  2098.   CommandMailbox->Bytes[3] |= LogicalDriveNumber << 3;
  2099. }
  2102. /*
  2103.   Define prototypes for the forward referenced DAC960 Driver Internal Functions.
  2104. */
  2106. static void DAC960_FinalizeController(DAC960_Controller_T *);
  2107. static int DAC960_Notifier(NotifierBlock_T *, unsigned long, void *);
  2108. static void DAC960_V1_QueueReadWriteCommand(DAC960_Command_T *);
  2109. static void DAC960_V2_QueueReadWriteCommand(DAC960_Command_T *);
  2110. static void DAC960_RequestFunction(RequestQueue_T *);
  2111. static void DAC960_BA_InterruptHandler(int, void *, Registers_T *);
  2112. static void DAC960_LP_InterruptHandler(int, void *, Registers_T *);
  2113. static void DAC960_LA_InterruptHandler(int, void *, Registers_T *);
  2114. static void DAC960_PG_InterruptHandler(int, void *, Registers_T *);
  2115. static void DAC960_PD_InterruptHandler(int, void *, Registers_T *);
  2116. static void DAC960_P_InterruptHandler(int, void *, Registers_T *);
  2117. static void DAC960_V1_QueueMonitoringCommand(DAC960_Command_T *);
  2118. static void DAC960_V2_QueueMonitoringCommand(DAC960_Command_T *);
  2119. static void DAC960_MonitoringTimerFunction(unsigned long);
  2120. static int DAC960_Open(Inode_T *, File_T *);
  2121. static int DAC960_Release(Inode_T *, File_T *);
  2122. static int DAC960_IOCTL(Inode_T *, File_T *, unsigned int, unsigned long);
  2123. static int DAC960_UserIOCTL(Inode_T *, File_T *, unsigned int, unsigned long);
  2124. static void DAC960_Message(DAC960_MessageLevel_T, unsigned char *,
  2125.    DAC960_Controller_T *, ...);
  2126. static void DAC960_CreateProcEntries(void);
  2127. static void DAC960_DestroyProcEntries(void);
  2130. /*
  2131.   Export the Kernel Mode IOCTL interface.
  2132. */
  2134. EXPORT_SYMBOL(DAC960_KernelIOCTL);
  2137. #endif /* DAC960_DriverVersion */