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Mode_Detect.lst：源码内容

C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE MODE_DETECT
OBJECT MODULE PLACED IN .OutputMode_Detect.obj
COMPILER INVOKED BY: C:KeilC51BINC51.EXE CodeMode_Detect.c OPTIMIZE(9,SPEED) BROWSE DEBUG OBJECTEXTEND CODE SYMBOLS
- PRINT(.OutputMode_Detect.lst) PREPRINT(.OutputMode_Detect.i) OBJECT(.OutputMode_Detect.obj)
stmt level source
1
2 #define __MODEDETECT__
3
4 #include "HeaderLcd_func.h"
5 #include "HeaderLcd_Main.h"
6 #include "HeaderAccess.h"
7 #include "Headerconfig.h"
8 #include "HeaderOSD.h"
9 #include "HeaderLcd_Auto.h"
10 #include "HeaderFrame_Sync.h"
11 #include "HeaderSrc_Ctrl.h"
12 #include "HeaderLCD_OSD.h"
13
14
15 /////////////////////////////////////////////////////////
16 //------------------- Mode Detector -----------------//
17 /////////////////////////////////////////////////////////
18 void Mode_Detector(void)
19 {
20 1
21 1 switch (stGUD1.INPUT_SOURCE & 0x07)
22 1 {
23 2 case SOURCE_VGA :
24 2 case SOURCE_DVI :
25 2 // Save previous values of ucMode_Curr, bHpole_Curr and bVpole_Curr
26 2 bHpole_Prev = bHpole_Curr;
27 2 bVpole_Prev = bVpole_Curr;
28 2
29 2 if ((MODE_NOSIGNAL == ucMode_Curr) || (MODE_NOSUPPORT == ucMode_Curr))
30 2 Detect_Input_Mode();
31 2 else
32 2 Check_Input_Mode();
33 2 break;
34 2
35 2 default :
36 2 if ((MODE_NOSIGNAL == ucMode_Curr) || (MODE_NOSUPPORT == ucMode_Curr))
37 2 Detect_Video_Mode(); // Set default polarity
38 2 else
39 2 Check_Video_Mode(); // Set polarity after measure
40 2 break;
41 2 }
42 1
43 1 Measure_Mode(); // Measure mode-timing
44 1 }
45
46 void Measure_Mode(void)
47 {
48 1
49 1
50 1 switch (stGUD1.INPUT_SOURCE & 0x07)
51 1 {
52 2 RTDSetByte(SYNC_CTRL_4A,0x00);
53 2 case SOURCE_VGA :
54 2 RTDSetByte(SYNC_POR_4C, (SYNC_SS == ucSync_Type) ? 0x02 : 0x32);
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 2
55 2 break;
56 2
57 2 case SOURCE_DVI :
58 2 /*//eric 0729 test issue:DVI source change
59 2 #if (TMDS_ENABLE)
60 2 if (0 == ucTMDS_SEARCH_COUNTER && MODE_NOSIGNAL == ucMode_Curr) // V101C modified
61 2 {
62 2 RTDCodeW(TMDS_MANUAL_ON);
63 2
64 2 ucTMDS_SEARCH_COUNTER = 0x08;
65 2 }
66 2 ucTMDS_SEARCH_COUNTER -= 0x01;
67 2 #endif
68 2 */
69 2 RTDSetByte(SYNC_POR_4C, 0x02);
70 2 break;
71 2
72 2 default :
73 2 RTDSetByte(SYNC_POR_4C, 0x02);
74 2 break;
75 2 }
76 1
77 1 }
78
79 #if(SOURCE_AUTO_SCAN)
80 /////////////////////////////////////////////////////////
81 //---Detect which source with valid signal-------------//
82 /////////////////////////////////////////////////////////
83 void Measure_Source(unsigned char SOURCE)
84 {
85 1 switch(SOURCE)
86 1 {
87 2 case SOURCE_VGA:
88 2 RTDSetByte(SYNC_CTRL_4A,0x01);
89 2 break;
90 2 case SOURCE_DVI:
91 2 RTDSetByte(SYNC_CTRL_4A,0x03);
92 2 break;
93 2 case SOURCE_AV:
94 2 I2CWrite(V_ENABLE);
95 2 I2CWrite(AV_DETECT);
96 2 break;
97 2 case SOURCE_SV:
98 2 I2CWrite(V_ENABLE);
99 2 I2CWrite(SV_DETECT);
100 2 break;
101 2 }
102 1 //RTDSetByte(SYNC_POR_4C, 0x32);
103 1 //RTDSetByte(SYNC_POR_4C, 0x02);
104 1 //RTDSetByte(SYNC_POR_4C, (stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA ? 0x32 : 0x02);
105 1
106 1 if(((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) && (SYNC_SS != ucSync_Type))
107 1 RTDSetByte(SYNC_POR_4C,0x32);
108 1 else
109 1 RTDSetByte(SYNC_POR_4C,0x02);
110 1
111 1 Delay_Xms(35);
112 1 //Delay_Xms(24);
113 1
114 1
115 1 }
116 #endif
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 3
117
118 unsigned char VGA_Mode_Search(unsigned int HS_Pulse)
119 {
120 1 unsigned char ucMode_Temp,m;
121 1 Data[0] = HS_Pulse * 12 / usHsync; // 0 : 720x350; 1 : 640x350;
122 1
123 1 ucMode_Temp = MODE_NOSUPPORT;
124 1
125 1 // Search for Standard Mode
126 1 m = MODE_1280x1024x75HZ; //anson
127 1 // m = MODE_1600x1200x60HZ;
128 1 do
129 1 {
130 2 if ((usHsync > VGA_Mode[m][0]) && (usHsync < VGA_Mode[m][1]))
131 2 {
132 3 if ((usVsync >= VGA_Mode[m][2]) && (usVsync <= VGA_Mode[m][3]))
133 3 {
134 4 if (MODE_1280x1024x75HZ == m)
135 4 {
136 5 if (0 == (bVpole_Curr | bHpole_Curr)) m = MODE_1280x1024x76HZ; // SUN 1024-76
137 5 }
138 4 else if (MODE_1024x0768x75HZ == m)
139 4 {
140 5 if (0 == (bVpole_Curr | bHpole_Curr)) m = MODE_1024x0768x74HZ; // MAC768-75
141 5 }
142 4 else if (MODE_0640x0480x60HZ == m && bVpole_Curr != bHpole_Curr)
143 4 {
144 5 // MODE_VGA350x60Hz : 640x350 60Hz
145 5 // MODE_VGA350x60Hz | 0x40 : 720x350 60Hz
146 5 // MODE_VGA400x60Hz : 640x400 60Hz
147 5 // MODE_VGA400x60Hz | 0x40 : 720x400 60Hz
148 5 if (bHpole_Curr)
149 5 m = Data[0] ? MODE_VGA350x60Hz : MODE_VGA350x60Hz | 0x40;
150 5 else
151 5 m = (stGUD1.FUNCTION & 0x10) ? MODE_VGA400x60Hz : MODE_VGA400x60Hz | 0x40;
152 5 //m = (stGUD1.INPUT_SOURCE & 0x80) ? MODE_VGA400x60Hz : MODE_VGA400x60Hz | 0x40;
153 5 }
154 4 else if (MODE_0640x0480x50HZ == m && bVpole_Curr != bHpole_Curr)
155 4 {
156 5 // MODE_VGA350x50Hz : 640x350 50Hz
157 5 // MODE_VGA350x50Hz | 0x40 : 720x350 50Hz
158 5 // MODE_VGA400x50Hz : 640x400 50Hz
159 5 // MODE_VGA400x50Hz | 0x40 : 720x400 50Hz
160 5 if (bHpole_Curr)
161 5 m = Data[0] ? MODE_VGA350x50Hz : MODE_VGA350x50Hz | 0x40;
162 5 else
163 5 m = (stGUD1.FUNCTION & 0x10) ? MODE_VGA400x50Hz : MODE_VGA400x50Hz | 0x40;
164 5 //m = (stGUD1.INPUT_SOURCE & 0x80) ? MODE_VGA400x50Hz : MODE_VGA400x50Hz | 0x40;
165 5 }
166 4 else if (MODE_0720x0400x85HZ == m)
167 4 {
168 5 if (1 == bHpole_Curr && 0 == bVpole_Curr)
169 5 m = MODE_0640x0350x85HZ;
170 5 else if (stGUD1.FUNCTION & 0x10) //else if (stGUD1.INPUT_SOURCE & 0x80)
171 5 m = MODE_0640x0400x85HZ;
172 5 }
173 4 else if (MODE_0720x0400x70HZ == m)
174 4 {
175 5 if (1 == bHpole_Curr && 0 == bVpole_Curr)
176 5 m = Data[0] ? MODE_0640x0350x70HZ : MODE_0720x0350x70HZ;
177 5 else if ((stGUD1.FUNCTION & 0x10)==0) //else if (stGUD1.INPUT_SOURCE & 0x80) //anson
178 5 // else if (stGUD1.FUNCTION & 0x10) //else if (stGUD1.INPUT_SOURCE & 0x80)
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 4
179 5 m = MODE_0640x0400x70HZ;
180 5 }
181 4 else if (MODE_1024x0768x59HZ == m)
182 4 {
183 5 if(HS_Pulse > 45)
184 5 m = MODE_1024x0768x60HZ;
185 5 }
186 4 else if (MODE_1024x0768x60HZ == m)
187 4 {
188 5 if(HS_Pulse <= 45)
189 5 m = MODE_1024x0768x59HZ;
190 5 }
191 4 else if(MODE_1024x0768x72HZ == m) //anson 05_0321
192 4 {
193 5 if(ucRefresh <= 71)
194 5 m = MODE_1024x0768x70HZ;
195 5 }
196 4
197 4 ucMode_Temp = m;
198 4 }
199 3 }
200 2 }
201 1 while ((0 != --m) && (MODE_NOSUPPORT == ucMode_Temp));
202 1
203 1 // Search for User Mode
204 1 if (MODE_NOSUPPORT == ucMode_Temp)
205 1 {
206 2 usIPV_ACT_LEN = 0;
207 2
208 2 m = MODE_USER1280x1024; //anson
209 2 // m = MODE_USER1600x1200;
210 2 do
211 2 {
212 3 if ((usVsync >= VGA_Mode[m][2]) && (usVsync <= VGA_Mode[m][3]))
213 3 {
214 4 usIPV_ACT_LEN = CAP_WIN[m][4];
215 4
216 4 if ((usHsync >= VGA_Mode[m][0]) && (usHsync <= VGA_Mode[m][1]))
217 4 {
218 5 ucMode_Temp = m; // Support User Mode
219 5 }
220 4 }
221 3 }
222 2 while ((MODE_USER720x400 <= --m) && (MODE_NOSUPPORT == ucMode_Temp));
223 2 }
224 1
225 1 return ucMode_Temp;
226 1
227 1 }
228
229 unsigned char Partial_Display(void)
230 {
231 1 unsigned char ucMode_Temp;
232 1
233 1 if (DISP_LEN < usIPV_ACT_LEN) // V Scale-down
234 1 {
235 2 // Estimate display clock rate for full screen
236 2 // DCLK = (24.576MHz / usHsync) * DCLK per display line * (display image lines / input image lines)
237 2 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED1][0] * DISP_LEN
238 2 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
239 2
240 2 if (MAX_DCLK < ((unsigned int *)Data)[0])
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 5
241 2 {
242 3 // If clock rate for full-screen display is too high, we can try partial-V display.
243 3 // Estimate clock for partial-V display
244 3 // DCLK = (24.576MHz / usHsync) * DCLK per display line * (min. display total lines / input total lines
-)
245 3 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED1][0] * MIN_DV_TOTAL
246 3 / ((unsigned long)100 * (usVsync - 1) * usHsync);
247 3
248 3 if (MAX_DCLK < ((unsigned int *)Data)[1])
249 3 {
250 4 // Decrease usIPV_ACT_LEN to DISP_LEN and go further to check if it can be displayed.
251 4 usIPV_ACT_LEN = DISP_LEN;
252 4 }
253 3 else
254 3 {
255 4 ucMode_Temp = MODE_UNDEFINED1 | 0x80; // Scale-down and partial-V display
256 4 }
257 3 }
258 2 else
259 2 ucMode_Temp = MODE_UNDEFINED1; // Scale-down and full-V display
260 2 }
261 1
262 1 if (DISP_LEN >= usIPV_ACT_LEN) // V Scale-up
263 1 {
264 2 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0] * DISP_LEN
265 2 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
266 2
267 2 if (MAX_DCLK < ((unsigned int *)Data)[0])
268 2 {
269 3 if (MIN_DV_TOTAL >= (usVsync - 1))
270 3 {
271 4 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0] * MIN_DV_TOTAL
272 4 / ((unsigned long)100 * (usVsync - 1) * usHsync);
273 4 }
274 3 else
275 3 {
276 4 ((unsigned int *)Data)[1] = (unsigned long)2458 * Mode_Preset[MODE_UNDEFINED0][0]
277 4 / ((unsigned long)100 * usHsync);
278 4 }
279 3
280 3 if (MAX_DCLK < ((unsigned int *)Data)[1])
281 3 ucMode_Temp = MODE_NOSUPPORT; // Cannot display
282 3 else
283 3 ucMode_Temp = MODE_UNDEFINED0 | 0x80; // Scale-up and partial-V display
284 3 }
285 2 else
286 2 ucMode_Temp = MODE_UNDEFINED0; // Scale-up and full-V display
287 2 }
288 1
289 1 return ucMode_Temp;
290 1
291 1 }
292
293 void Sync_Type_Switch(void)
294 {
295 1 if (MODE_NOSIGNAL == ucMode_Curr)
296 1 {
297 2 if (SYNC_CS == ucSync_Type) // CS->SS
298 2 {
299 3 RTDCodeW(VGA_SET_SS);
300 3
301 3 bVpole_Curr = 1;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 6
302 3 bHpole_Curr = 1;
303 3 ucSync_Type = SYNC_SS;
304 3
305 3 }
306 2 else if (SYNC_SS == ucSync_Type) // SS->SOG
307 2 {
308 3 RTDCodeW(VGA_SET_SOG);
309 3
310 3 bVpole_Curr = 1;
311 3 bHpole_Curr = 1;
312 3 ucSync_Type = SYNC_SOG;
313 3
314 3
315 3
316 3 }
317 2 else // SOG->CS
318 2 {
319 3 RTDCodeW(VGA_SET_CS);
320 3
321 3 bVpole_Curr = 1;
322 3 bHpole_Curr = 1;
323 3 ucSync_Type = SYNC_CS;
324 3
325 3
326 3
327 3 }
328 2 }
329 1 }
330
331 void Sync_Type_Confirm(void)
332 {
333 1
334 1 #if(SOURCE_AUTO_SCAN == _FALSE)
unsigned char m;
// To prevent from mistaking CS (with VS) for SS, we check SYNC type once when finding a mode in SS.
if (SYNC_SS == ucSync_Type)
{
RTDSetByte(SYNC_CTRL_4B, 0x55);
RTDSetByte(SYNC_POR_4C, 0x22);
m = (MODE_DETECT_FREQ + 1) * 20;
do
{
Delay_Xms(1);
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
}
while ((Data[0] & 0x02) && (--m));
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
(0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
(0 == m))
{
ucSync_Type = SYNC_SS;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 7
RTDSetByte(SYNC_CTRL_4B, 0x14);
}
else
{
ucSync_Type = SYNC_CS;
RTDCodeW(VGA_SET_CS);
bVpole_Curr = 1;
bHpole_Curr = 1;
}
}
else if (SYNC_SOG == ucSync_Type)
{
RTDSetByte(SYNC_CTRL_4B, 0x14);
Delay_Xms(8);
RTDSetByte(SYNC_POR_4C, 0x00);
RTDSetByte(SYNC_POR_4C, 0x02);
m = (MODE_DETECT_FREQ + 1) * 20;
do
{
Delay_Xms(1);
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
}
while ((Data[0] & 0x02) && (--m));
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
(0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
(0 == m))
{
ucSync_Type = SYNC_SOG;
RTDSetByte(SYNC_CTRL_4B, 0x57);
//RTDSetByte(VGIP_SIGINV_05, 0x40);
Delay_Xms(8);
RTDSetByte(SYNC_POR_4C,0x32);
Delay_Xms(20);
RTDSetByte(SYNC_POR_4C, 0x00);
}
else
{
ucSync_Type = SYNC_SS;
RTDCodeW(VGA_SET_SS);
bVpole_Curr = 1;
bHpole_Curr = 1;
}
}
#endif
425 1
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 8
426 1 }
427 /////////////////////////////////////////////////////////
428 //------------ Detect VGA & DVI Mode ----------------//
429 /////////////////////////////////////////////////////////
430 void Detect_Input_Mode(void)
431 {
432 1 unsigned char ucMode_Temp;
433 1 unsigned int usHS_Pulse;
434 1
435 1 RTDRead(SYNC_POR_4C, 0x09, Y_INC);
436 1
437 1 if (Data[0] & 0x02)
438 1 {
439 2 // Reset Sync Processor when sync signal timeout
440 2 RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00);
441 2
442 2 // Treat sync signal timeout as no signal
443 2 ucMode_Temp = MODE_NOSIGNAL;
444 2 }
445 1 else
446 1 {
447 2
448 2 // ucMode_Temp = (Data[8] & 0xe0 ) >> 5;
449 2
450 2 // if(ucMode_Temp == 0 || ucMode_Temp >=4) //Test which edge of Hsync to latch Vsync will be safe
451 2 // {
452 2 // RTDSetBit(MEAS_VS_HI_54,0xf7,0x08); //Use positive edge of Hsync to latch Vsync
453 2 // ucDebug_Value0 = 0x08;
454 2 // }
455 2 // else
456 2 // {
457 2 // RTDSetBit(MEAS_VS_HI_54,0xf7,0x00); //Use negtive edge of Hsync to latch Vsync
458 2 // ucDebug_Value0 = 0x18;
459 2 // }
460 2
461 2
462 2 usStdHS = usHsync; // Save previous usHsync in usStdHS
463 2 usStdVS = usVsync; // Save previous usVsync in usStdVS
464 2
465 2 bVpole_Curr = (bit)(Data[0] & 0x08); // Save current usVsync polarity
466 2 bHpole_Curr = (bit)(Data[0] & 0x04); // Save current usHsync polarity
467 2
468 2 Data[7] = Data[5];
469 2 Data[6] = Data[6] & 0x0f;
470 2 Data[5] = Data[3];
471 2 Data[4] = Data[4] & 0x87;
472 2 Data[3] = Data[1];
473 2 Data[2] = Data[2] & 0x8f;
474 2
475 2 usHsync = ((unsigned int *)Data)[1]; // Current HSYNC timing
476 2 usVsync = ((unsigned int *)Data)[2]; // Current VSYNC timing
477 2
478 2 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
479 2 usHS_Pulse = ((unsigned int *)Data)[3]; // Current HSYNC pulse width
480 2
481 2 // Calculate Vertical Refresh Rate
482 2 // Original Formula :
483 2 // ucRefresh = 24.576M / (usHsync * usVsync)
484 2 // Use Data[0~3] as a temporary long variable
485 2 ((unsigned long *)Data)[0] = (unsigned long)usHsync * usVsync;
486 2 ucRefresh = (unsigned long)49152000 / ((unsigned long *)Data)[0];
487 2 ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 9
488 2
489 2 // Treat small change of usHsync/usVsync as no change
490 2 if (usStdHS <= usHsync && (usStdHS + 2) >= usHsync) usHsync = usStdHS;
491 2 if (usStdVS <= usVsync && (usStdVS + 2) >= usVsync) usVsync = usStdVS;
492 2
493 2 // Polarity must be correct
494 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
495 2 {
496 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
497 3
498 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
499 3 {
500 4 Data[0] &= 0xd7; // HS_RAW & VS positive
501 4
502 4 if (!bHpole_Curr) Data[0] |= 0x20;
503 4
504 4 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
505 4
506 4 ucMode_Temp = MODE_NOSUPPORT;
507 4 }
508 3 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
509 3 {
510 4 Data[0] &= 0xf3; // VS & HS positive
511 4
512 4 if (!bVpole_Curr) Data[0] |= 0x08;
513 4 if (!bHpole_Curr) Data[0] |= 0x04;
514 4 }
515 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
516 3
517 3
518 3 }
519 2 else
520 2 {
521 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
522 3 {
523 4 ucMode_Temp = MODE_NOSIGNAL; // Treat overflow as no signal
524 4 }
525 3 else
526 3 {
527 4 ucMode_Temp = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_Mode_Search(usHS_Pulse) :
- MODE_NOSUPPORT;
528 4
529 4
530 4 if (48 > ucRefresh || MAX_RATE < ucRefresh)
531 4 {
532 5 ucMode_Temp = MODE_NOSUPPORT; // We don't support vertical refresh rate lower than 5
-0Hz
533 5 }
534 4 else if (MODE_NOSUPPORT == ucMode_Temp && (0 != usIPV_ACT_LEN) && ((stGUD1.INPUT_SOURCE &
-0x07) == SOURCE_VGA))
535 4 {
536 5 ucMode_Temp = Partial_Display();
537 5 }
538 4 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
539 4 ucMode_Temp = Seek_DVI_Mode(ucMode_Temp);
540 4
541 4 // ucDebug_Value0 = ucMode_Temp;
542 4 }
543 3 }
544 2 }
545 1
546 1 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 10
547 1 {
548 2 if (SYNC_SOG == ucSync_Type && 0 != (usHS_Pulse * 7 / usHsync))
549 2 {
550 3 // To prevent from SOG mode mistake
551 3 // HSYNC pulse width will never longer than 1/7*HSYNC period
552 3 ucMode_Temp = MODE_NOSIGNAL;
553 3 }
554 2 }
555 1
556 1 //-------------Check result-----------------------------------------
557 1 if (MODE_NOSUPPORT == ucMode_Temp || MODE_NOSIGNAL == ucMode_Temp)
558 1 {
559 2 // Treat illegal signal as no signal when SOG
560 2 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
561 2 {
562 3 if (SYNC_SOG == ucSync_Type)
563 3 ucMode_Temp = MODE_NOSIGNAL;
564 3 }
565 2
566 2 if (MODE_NOSUPPORT != ucMode_Found && MODE_NOSIGNAL != ucMode_Found) ucMode_Times = 0;
567 2
568 2 ucMode_Found = ucMode_Temp;
569 2
570 2 if (NO_MODE_TIMES > ucMode_Times)
571 2 {
572 3 // Wait for signal stable
573 3 ucMode_Times ++;
574 3
575 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
576 3 {
577 4 //Enable the TMDS Hsync & Vsync error correction to improve the long cable image quality
578 4 RTDSetByte(TMDS_CORRECTION_FF,0x03);
579 4 }
580 3 }
581 2 else
582 2 {
583 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
584 3 {
585 4 //Disable the TMDS Hsync & Vsync error correction
586 4 RTDSetByte(TMDS_CORRECTION_FF,0x00);
587 4 }
588 3
589 3 bStable = (ucMode_Curr == ucMode_Found) ? 1 : 0; // bStable must be cleared when mo
-de changed
590 3 ucMode_Curr = ucMode_Found;
591 3 ucMode_Times = NO_MODE_TIMES - 2;
592 3
593 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
594 3 Sync_Type_Switch();
595 3
596 3 }
597 2 }
598 1 else
599 1 {
600 2 if (ucMode_Found != ucMode_Temp)
601 2 {
602 3 ucMode_Times = 1;
603 3 ucMode_Found = ucMode_Temp;
604 3
605 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
606 3 Sync_Type_Confirm();
607 3 }
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 11
608 2 else
609 2 {
610 3 Data[0] = ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? VGA_SEARCH_TIMES : DVI_SEARCH_TIMES;
611 3 //if (VGA_SEARCH_TIMES > ucMode_Times)
612 3 if (Data[0] > ucMode_Times)
613 3 {
614 4 ucMode_Times ++;
615 4 }
616 3 else
617 3 {
618 4
619 4 bLIGHT_PWR = LIGHT_OFF; // Turn off BackLight for reset display
620 4
621 4 RTDSetByte(HOSTCTRL_02, 0x40); // Wake RTD up
622 4 RTDOSDW(OSD_Reset); // Clear OSD
623 4
624 4 ucMode_Curr = ucMode_Found; // Supported mode found
625 4 ucMode_Times = 0; // Reset mode timer
626 4 bStable = 0; // bStable must be cleared when mode changed
627 4
628 4 if((stGUD1.INPUT_SOURCE & 0x07)== SOURCE_VGA)
629 4 Display_VGA_Set(); // Set VGA Mode registers
630 4 else
631 4 Display_DVI_Set();
632 4
633 4
634 4 #if (RTDDEBUG)
if (ucMode_PrevAct == ucMode_Curr)
{
if (0xff > ucMode_QuitCnt) ucMode_QuitCnt += 1;
}
else
{
ucMode_PrevAct = ucMode_Curr;
ucMode_QuitCnt = 0;
ucDebug = 0;
}
#endif
646 4 }
647 3 }
648 2 }
649 1 }
650
651 //------------------- Check VGA & DVI Mode -------------------//
652 void Check_Input_Mode(void)
653 {
654 1 RTDRead(SYNC_POR_4C, 0x05, Y_INC);
655 1
656 1 if (Data[0] & 0x02)
657 1 {
658 2 RTDSetByte(SYNC_POR_4C, ((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA) ? 0x20 : 0x00); // I
-nput signal time-out. Reset sync-processor
659 2
660 2 ucMode_Found = MODE_NOSUPPORT;
661 2 }
662 1 else
663 1 {
664 2 bVpole_Curr = (bit)(Data[0] & 0x08); // Current usVsync polarity
665 2 bHpole_Curr = (bit)(Data[0] & 0x04); // Current usHsync polarity
666 2
667 2 Data[5] = Data[3];
668 2 Data[4] = Data[4] & 0x87;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 12
669 2 Data[3] = Data[1];
670 2 Data[2] = Data[2] & 0x8f;
671 2 usHsync = ((unsigned int *)Data)[1]; // Current usHsync timing
672 2 usVsync = ((unsigned int *)Data)[2]; // Current usVsync timing
673 2
674 2 // Polarity must be correct
675 2 if ((bVpole_Curr != bVpole_Prev) || (bHpole_Curr != bHpole_Prev))
676 2 {
677 3 RTDRead(VGIP_SIGINV_05, 0x01, N_INC);
678 3 /*
679 3 Data[0] &= 0xd7; // HS_RAW & VS positive
680 3
681 3 if (!bHpole_Curr) Data[0] |= 0x20;
682 3
683 3 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
684 3 */
685 3
686 3
687 3 if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_VGA)
688 3 {
689 4 Data[0] &= 0xd7; // HS_RAW & VS positive
690 4
691 4 if (!bHpole_Curr) Data[0] |= 0x20;
692 4
693 4 if (!bVpole_Curr && SYNC_SS == ucSync_Type) Data[0] |= 0x08; // Seperate sync
694 4 }
695 3 else if((stGUD1.INPUT_SOURCE & 0x07) == SOURCE_DVI)
696 3 {
697 4 Data[0] &= 0xf3; // VS & HS positive
698 4
699 4 if (!bVpole_Curr) Data[0] |= 0x08;
700 4 if (!bHpole_Curr) Data[0] |= 0x04;
701 4 }
702 3
703 3 RTDSetByte(VGIP_SIGINV_05, Data[0]);
704 3
705 3 ucMode_Found = MODE_NOSUPPORT;
706 3 }
707 2 else
708 2 {
709 3 if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync) // Check overf
-low
710 3 {
711 4 ucMode_Found = MODE_NOSUPPORT;
712 4 }
713 3 else
714 3 {
715 4 if ((usHsync < (usStdHS - 1)) || (usHsync > (usStdHS + 3)) ||
716 4 (usVsync < (usStdVS - 1)) || (usVsync > (usStdVS + 3)))
717 4 {
718 5 ucMode_Found = MODE_NOSUPPORT;
719 5 }
720 4 else
721 4 {
722 5 ucMode_Found = ucMode_Curr;
723 5 }
724 4 }
725 3 }
726 2 }
727 1
728 1 if (MODE_NOSUPPORT == ucMode_Found)
729 1 Reset_Mode();
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 13
730 1 else
731 1 {
732 2 bStable = 1; // Set bStable to 1 when signal timing is stable.
733 2 #if(AS_NON_FRAMESYNC)
RTDSetByte(STATUS0_01, 0x00); // Clear status
RTDSetByte(STATUS1_1F, 0x00); // Clear status
if(bFrameSync)
RTDSetBit(ODD_CTRL_8E,0xef,0x10);
#endif
740 2 }
741 1
742 1 }
743
744
745
746
747 unsigned char Seek_DVI_Mode(unsigned char mode)
748 {
749 1 #if(TMDS_ENABLE)
750 1 unsigned char Wait_Time_Cnt;
751 1
752 1 RTDSetByte(SYNC_POR_4C, 0x03); // Measure data enable width and height
753 1
754 1 Wait_Time_Cnt = 60;
755 1 do
756 1 {
757 2 Delay_Xms(1);
758 2 RTDRead(SYNC_POR_4C, 0x07, Y_INC);
759 2 }
760 1 while ((Data[0] & 0x02) && (--Wait_Time_Cnt));
761 1
762 1 Data[7] = Data[5];
763 1 Data[6] = Data[6] & 0x0f;
764 1 Data[5] = Data[3];
765 1 Data[4] = Data[4] & 0x87;
766 1 Data[3] = Data[1];
767 1 Data[2] = Data[2] & 0x8f;
768 1
769 1 // Measure Failed !!!
770 1 if ((0 == ((unsigned int *)Data)[1]) || (0x07ff <= ((unsigned int *)Data)[1]) ||
771 1 (0 == ((unsigned int *)Data)[2]) || (0x07ff <= ((unsigned int *)Data)[2]) ||
772 1 (0 == Wait_Time_Cnt))
773 1 {
774 2 RTDSetByte(SYNC_POR_4C, 0x00);
775 2
776 2 return MODE_NOSUPPORT;
777 2 }
778 1
779 1 // Save IH_TOTAL in usADC_Clock
780 1 usADC_Clock = ((unsigned int *)Data)[1] * 2;
781 1
782 1 // Save input data enable width and height
783 1 usIPV_ACT_LEN = ((unsigned int *)Data)[2];
784 1 usIPH_ACT_WID = ((unsigned int *)Data)[3] * 2;
785 1
786 1 // We don't support input image less than 350 active lines
787 1 if (350 > usIPV_ACT_LEN) return MODE_NOSUPPORT;
788 1
789 1 // We only support 8N active width
790 1 usIPH_ACT_WID = (2 < (usIPH_ACT_WID & 0x0007)) ? ((usIPH_ACT_WID + 8) & 0xfff8) : (usIPH_ACT_WID & 0
-xfff8);
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 14
791 1
792 1 // We only support active width not larger than 1280
793 1 if (1280 < usIPH_ACT_WID) usIPH_ACT_WID = 1280;
794 1
795 1 // Calculate maximum usIPV_ACT_LEN limitation
796 1 ((unsigned int *)Data)[0] = (unsigned long)(usVsync - 1) * DISP_LEN / MIN_DV_TOTAL;
797 1
798 1 if (((unsigned int *)Data)[0] < usIPV_ACT_LEN) usIPV_ACT_LEN = ((unsigned int *)Data)[0];
799 1
800 1 mode = MODE_UNDEFINED0;
801 1
802 1 if (MODE_UNDEFINED0 == mode)
803 1 {
804 2 // First, we try user-mode to fit the undefined mode for full-screen display.
805 2 Wait_Time_Cnt = MODE_USER720x400;
806 2 do
807 2 {
808 3 if (Mode_Preset[Wait_Time_Cnt][2] < CAP_WIN[Wait_Time_Cnt][4]) // V scale-down
809 3 {
810 4 // Larger scale-down ratio may need a larger DH_TOTAL.
811 4 // So usIPV_ACT_LEN should not be too larger than pre-set capture window length
812 4 if (Mode_Preset[Wait_Time_Cnt][2] > usIPV_ACT_LEN || (CAP_WIN[Wait_Time_Cnt][4] + 24) < us
-IPV_ACT_LEN) continue;
813 4 }
814 3 else
815 3 {
816 4 if (Mode_Preset[Wait_Time_Cnt][2] < usIPV_ACT_LEN) continue;
817 4 }
818 3
819 3 ((unsigned int *)Data)[0] = (unsigned long)2458 * Mode_Preset[Wait_Time_Cnt][0] * Mode_Prese
-t[Wait_Time_Cnt][2]
820 3 / ((unsigned long)100 * usIPV_ACT_LEN * usHsync);
821 3
822 3 // Return if we find out a suitable user-mode.
823 3 if (MAX_DCLK > ((unsigned int *)Data)[0]) return Wait_Time_Cnt;
824 3 }
825 2 while (MODE_USER1600x1200 >= ++Wait_Time_Cnt);
826 2
827 2 mode = Partial_Display();
828 2 // If failed, we try partial-screen display.
829 2
830 2 }
831 1
832 1
833 1 return mode;
834 1 #else
mode = MODE_UNDEFINED0;
return 0;
#endif
838 1 }
839
840 /////////////////////////////////////////////////////////
841 //------------------ Detect VIDEO Mode ----------------//
842 /////////////////////////////////////////////////////////
843 void Detect_Video_Mode(void)
844 {
845 1 #if(VIDEO_CHIP != VDC_NONE)
I2CRead(ADDR_VIDEO, 0x1f, 0x01);
//------ Check Horizontal Lock & Frequency ------
if (0 == (Data[0] & 0x40))
{
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 15
if ((Data[0] & 0x20) && (0x01 != (ucAV_Mode & 0x0f)))
{
// Field rate changed to 60Hz
ucAV_Mode = 0x01;
ucMode_Found = MODE_NOSUPPORT;
ucMode_Times = 0;
Data[0] = 4;
Data[1] = ADDR_VIDEO;
Data[2] = 0x0e;
Data[3] = 0x08; // Start color search from NTSC-M
I2CWrite(Data);
}
else if ((0 == (Data[0] & 0x20)) && (0x02 != (ucAV_Mode & 0x02)))
{
// Field rate changed to 50Hz
ucAV_Mode = 0x02;
ucMode_Found = MODE_NOSUPPORT;
ucMode_Times = 0;
Data[0] = 4;
Data[1] = ADDR_VIDEO;
Data[2] = 0x0e;
Data[3] = 0x08; // Start color search from PAL-BDGHI
I2CWrite(Data);
}
else
{
//------ Check Lock Color ------
if (0x01 == (Data[0] & 0x01))
{
// Lock Color
if (ucAV_Mode & 0x01)
{
if (MODE_VIDEO60HZ == ucMode_Found)
{
ucMode_Times ++;
}
else
{
ucMode_Found = MODE_VIDEO60HZ;
ucMode_Times = 0;
}
}
else
{
if (MODE_VIDEO50HZ == ucMode_Found)
{
ucMode_Times ++;
}
else
{
ucMode_Found = MODE_VIDEO50HZ;
ucMode_Times = 0;
}
}
}
else
{
// Non Lock Color
if (MODE_NOSUPPORT != ucMode_Found)
{
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 16
ucMode_Found = MODE_NOSUPPORT;
ucMode_Times = 0;
}
Data[0] = 4;
Data[1] = ADDR_VIDEO;
Data[2] = 0x0e;
if (0x03 == (ucAV_Mode & 0x03))
{
// SECAM -> PAL-BDGHI(50Hz)
Data[3] = 0x08;
I2CWrite(Data);
ucAV_Mode = 0x02;
}
else
{
if (ucMode_Times & 0x01) // Every 2-times , change color
{
switch (ucAV_Mode & 0x70)
{
case 0x00:
Data[3] = 0x18; // NTSC-4.43(50Hz) // PAL-4.43(60Hz)
I2CWrite(Data);
ucAV_Mode = (ucAV_Mode & 0x0f) | 0x10;
break;
case 0x10:
Data[3] = 0x28; // PAL-N(50Hz) // NTSC-4.43(60Hz)
I2CWrite(Data);
ucAV_Mode = (ucAV_Mode & 0x0f) | 0x20;
break;
case 0x20:
Data[3] = 0x38; // NTSC-N(50Hz) // PAL-M(60Hz)
I2CWrite(Data);
ucAV_Mode = (ucAV_Mode & 0x0f) | 0x30;
break;
case 0x30:
if (ucAV_Mode & 0x02)
{
// NTSC-N -> SECAM (50Hz)
Data[3] = 0x5c;
I2CWrite(Data);
ucAV_Mode = 0x03;
}
else
{
// PAL-M -> NTSC_M (60Hz)
Data[3] = 0x08;
I2CWrite(Data);
ucAV_Mode = ucAV_Mode & 0x0f | 0x00;
}
default:
break;
}//end of "switch (ucAV_Mode & 0x70)"
}//end of "if (ucMode_Times & 0x01)"
}//end of "if (0x03 == (ucAV_Mode & 0x03)) else"
}//end of "Non Lock color
}//end of "Check Lock Color"
}//end of "if (0==(Data[0] & 0x40))"
else
{
// Non Horizontal Lock
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 17
ucAV_Mode = 0;
if (ucMode_Found != MODE_NOSUPPORT)
{
ucMode_Found = MODE_NOSUPPORT;
ucMode_Times = 0;
}
}
//-------------Check result--------------
if (MODE_NOSUPPORT != ucMode_Found)
{
if (VIDEO_SEARCH_TIMES < ucMode_Times)
{
bLIGHT_PWR = LIGHT_OFF; // Turn off BackLight for reset display
RTDSetByte(HOSTCTRL_02, 0x40); // Wake RTD up
RTDOSDW(OSD_Reset); // Clear OSD
if (SOURCE_YUV == (stGUD1.INPUT_SOURCE & 0x07))
ucMode_Curr = (ucAV_Mode & 0x02) ? MODE_YUV50HZ : MODE_YUV60HZ;
else
ucMode_Curr = ucMode_Found;
ucMode_Times = 0;
bStable = 0; // bStable must be cleared when mode changed
Display_Video_Set();
}
}
else
{
ucMode_Times ++;
if (ucAV_Mode)
{
// Force to display although we cannot lock color
if (VIDEO_SEARCH_TIMES < ucMode_Times
&& (NO_COLOR_TIMES < ucMode_Times || SOURCE_YUV == (stGUD1.INPUT_SOURCE & 0x07)))
{
bLIGHT_PWR = LIGHT_OFF; // Turn off BackLight for reset display
RTDSetByte(HOSTCTRL_02, 0x40); // Wake RTD up
RTDOSDW(OSD_Reset); // Clear OSD
ucAV_Mode = (ucAV_Mode & 0x02) ? 0x82 : 0x81;
if (SOURCE_YUV != (stGUD1.INPUT_SOURCE & 0x07))
ucMode_Curr = (ucAV_Mode & 0x02) ? MODE_VIDEO50HZ : MODE_VIDEO60HZ;
else
ucMode_Curr = (ucAV_Mode & 0x02) ? MODE_YUV50HZ : MODE_YUV60HZ;
ucMode_Times = 0;
bStable = 0; // bStable must be cleared when mode changed
Display_Video_Set();
}
}
else
{
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 18
if (NO_MODE_TIMES < ucMode_Times)
{
bStable = 1; // Set bStable to 1 when signal timing is stable.
ucMode_Times = NO_MODE_TIMES - 1;
}
}
}
#else
1046 1 Display_Video_Set();
1047 1 #endif
1048 1 }
1049
1050
1051 //------------------- Check AV Mode -------------------//
1052 void Check_Video_Mode(void)
1053 {
1054 1 #if(VIDEO_CHIP != VDC_NONE)
I2CRead(ADDR_VIDEO, 0x1f, 0x01);
// Check color
if (0 == (ucAV_Mode & 0x80))
{
if (0 == (Data[0] & 0x01)) ucMode_Curr = MODE_NOSIGNAL; // Color standard changed
}
else
{
if (0 == (Data[0] & 0x01))
{
ucMode_Times = 0;
}
else
{
// When we cannot lock color, we set color standard to PAL-BDGHI if field rate is 50Hz,
// and to NTSC-M if it is 60Hz.
// If we find color is locked, we should update ucAV_Mode to indicate we now get color.
if (VIDEO_SEARCH_TIMES < ++ucMode_Times) ucAV_Mode = ucAV_Mode & 0x0f;
}
}
// Check field rate
if (Data[0] & 0x40)
{
ucMode_Curr = MODE_NOSIGNAL;
}
else
{
if (ucAV_Mode & 0x02) // 50Hz
{
if (0x00 != (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
else // 60Hz
{
if (0x00 == (Data[0] & 0x20)) ucMode_Curr = MODE_NOSIGNAL;
}
}
// Check result
if (MODE_NOSIGNAL == ucMode_Curr)
Reset_Mode();
else
bStable = 1; // Set bStable to 1 when signal timing is stable.
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 19
#endif
1100 1 }
1101
1102
1103 void Calculate_IVS2DVS_Delay(unsigned char integer, unsigned char fraction, unsigned int DVStart)
1104 {
1105 1 if ((usIPV_ACT_STA + integer) < (DVStart >> 6))
1106 1 {
1107 2 // You should never get into this code ....
1108 2 usIPV_ACT_STA = ( DVStart >> 6) - integer;
1109 2
1110 2 RTDSetByte(IPV_ACT_STA_0A, (unsigned char)usIPV_ACT_STA);
1111 2 RTDSetByte(IPV_ACT_STA_0A + 1, (unsigned char)(usIPV_ACT_STA >> 8));
1112 2 }
1113 1
1114 1 ((unsigned int*)Data)[0] = ((usIPV_ACT_STA + integer) << 6) + ((unsigned int)fraction << 6)/10 - D
-VStart;
1115 1
1116 1
1117 1 ucDV_Delay = (unsigned char)(((unsigned int*)Data)[0] >> 6);
1118 1
1119 1 Data[6] = ((unsigned int*)Data)[0] - (ucDV_Delay << 6);
1120 1
1121 1 Data[6] = (unsigned long)usADC_Clock * Data[6] / 1024;//512;
1122 1
1123 1 RTDSetByte(FS_FT_DELAY_1E, Data[6]);
1124 1
1125 1
1126 1 }
1127
1128 void Set_Dclk(unsigned int DispLen)
1129 {
1130 1 if (Mode_Preset[ucMode_Curr][3])
1131 1 {
1132 2 // Use preset DCLK M/N code
1133 2 Data[0] = 6;
1134 2 Data[1] = Y_INC;
1135 2 Data[2] = DPLL_CTRL_D0;
1136 2 Data[3] = 0x11;
1137 2 Data[4] = (unsigned char)(Mode_Preset[ucMode_Curr][3] >> 8);
1138 2 Data[5] = (unsigned char)Mode_Preset[ucMode_Curr][3];
1139 2 Data[6] = 0;
1140 2 RTDWrite(Data);
1141 2 }
1142 1 else
1143 1 {
1144 2
1145 2 // if (VGA_Mode[ucMode_Curr][4])
1146 2 // {
1147 2 // ((unsigned int *)Data)[0] = (unsigned long)8 * usDH_Total * USER_MODE_NCODE * usDispLen
1148 2 // / ((unsigned long)usIPV_ACT_LEN * VGA_Mode[ucMode_Curr][4]);
1149 2 // }
1150 2 // else
1151 2 // {
1152 2
1153 2 ((unsigned int *)Data)[0] = (unsigned long)8 * usDH_Total * USER_MODE_NCODE * DispLen
1154 2 / ((unsigned long)usIPV_ACT_LEN * usHsync);
1155 2 // }
1156 2
1157 2
1158 2 //Original Formula : DPM/Ich = 17.6 must be constant
1159 2 //Ich = DPM * 10 / 176
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 20
1160 2 //2*Ich = DPM * 20 / 176 , set D0[0] to 0, then I = 2 * Ich
1161 2 //I = 2 * Ich = 2.5u + D0[3]*2.5u + D0[4]*5u + D0[5]*10u + D0[6]*20u + D0[7]*30u(A)
1162 2 //2I = 4 * Ich = 5u + D0[3]*5u + D0[4]*10u + D0[5]*20u + D0[6]*40u + D0[7]*60u(A)
1163 2 Data[15] = ((unsigned int *)Data)[0] >> 2;
1164 2 Data[5] = (unsigned int)Data[15] * 40 / 176 - 5; //Calculate the 4*Ich,
1165 2 Data[6] = 0x00;
1166 2 if(Data[5] > 60)
1167 2 {
1168 3 Data[5] -= 60;
1169 3 Data[6] |= 0x80;
1170 3 }
1171 2
1172 2 if(Data[5] > 40)
1173 2 {
1174 3 Data[5] -= 40;
1175 3 Data[6] |= 0x40;
1176 3 }
1177 2
1178 2 if(Data[5] > 20)
1179 2 {
1180 3 Data[5] -= 20;
1181 3 Data[6] |= 0x20;
1182 3 }
1183 2
1184 2 if(Data[5] > 10)
1185 2 {
1186 3 Data[5] -= 10;
1187 3 Data[6] |= 0x10;
1188 3 }
1189 2
1190 2 if(Data[5] > 5)
1191 2 {
1192 3 Data[5] -= 5;
1193 3 Data[6] |= 0x08;
1194 3 }
1195 2
1196 2
1197 2 Data[0] = 7;
1198 2 Data[1] = Y_INC;
1199 2 Data[2] = DPLL_CTRL_D0;
1200 2 Data[3] = Data[6];
1201 2 Data[4] = Data[15] - 2;
1202 2 Data[5] = 0x10 | (USER_MODE_NCODE - 2);//Offset Frequency Direction set to Downward
1203 2 //Data[5] = (USER_MODE_NCODE - 2);//Offset Frequency Direction set to Downward
1204 2 Data[6] = 0x04;
1205 2 Data[7] = 0;
1206 2 RTDWrite(Data);
1207 2
1208 2
1209 2 // ucDebug_Value0 = Data[4];
1210 2 // ucDebug_Value1 = Data[5];
1211 2
1212 2 //More precise Dclk in KHz
1213 2 ((unsigned long*)Data)[0] = (unsigned long)24576000 / usIPV_ACT_LEN * DispLen / usHsync * usDH_Total ;
1214 2 //((unsigned long*)Data)[0] = (unsigned long)49152000 / usIPV_ACT_LEN * usDispLen / usHsync * usDH
-_Total ;
1215 2 //set M/N code Dclk
1216 2 ((unsigned long*)Data)[1] = (unsigned long)12288000 * (Data[15] + 1) / USER_MODE_NCODE;
1217 2 //((unsigned long*)Data)[1] = (unsigned long)24576000 * (Data[15] + 1) / USER_MODE_NCODE;
1218 2 ((unsigned long*)Data)[2] = ((unsigned long*)Data)[1] - ((unsigned long*)Data)[0]; //Dclk offset
1219 2 ((unsigned long*)Data)[3] = ((unsigned long*)Data)[1] >> 15; //Offset resolution equal to (Dclk / 2^15)
1220 2
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 21
1221 2 ((unsigned long*)Data)[3] = ((((unsigned long*)Data)[2] << 1)/ ((unsigned long*)Data)[3]) & 0x00000fff;
-//Calculate the Dclk offset
1222 2 //((unsigned long*)Data)[3] = (((unsigned long*)Data)[2] / ((unsigned long*)Data)[3]) & 0x00000fff
-; //Calculate the Dclk offset
1223 2
1224 2 RTDSetByte(DCLK_OFFSET_LSB_9A,(unsigned char)((unsigned long*)Data)[3]); //Set the Dclk offset
1225 2 // ucDebug_Value0 = (unsigned char)(((unsigned long*)Data)[3]);
1226 2 //RTDSetBit(DCLK_OFFSET_MSB_9B,0xf0,(unsigned char)(((unsigned long*)Data)[3] >> 8) | 0x20);
1227 2 RTDSetBit(DCLK_OFFSET_MSB_9B,0xf0,(unsigned char)(((unsigned long*)Data)[3] >> 8) | 0x20);
1228 2 // ucDebug_Value1 = (unsigned char)((((unsigned long*)Data)[3] >> 8) | 0x20);
1229 2 RTDSetBit(FX_LST_LEN_H_5A,0xff,0x08); //Enable DDS Spread Spectrum Output Function
1230 2 RTDSetBit(DPLL_N_D2,0xff,0x20); //DPLL Spread Spectrum Enable
1231 2 RTDSetBit(DPLL_FILTER_D3,0x7f,0x00); //Enable DPll output
1232 2 }
1233 1 }
1234
1235 void Initial_Mode(void)
1236 {
1237 1 unsigned char ucOption;
1238 1 unsigned int usDispLen;
1239 1
1240 1 // bit 7 of ucMode_Curr : partial-V display.
1241 1 // bit 6 of ucMode_Curr : select 720x350 or 720x400 for VGA-50Hz and VGA-60Hz
1242 1 ucOption = ucMode_Curr & 0xc0;
1243 1 ucMode_Curr = ucMode_Curr & 0x3f;
1244 1
1245 1
1246 1 RTDSetBit(SD_CTRL_70, 0xf9, VGA_ICLK_DELAY);
1247 1 if (SOURCE_DVI == (stGUD1.INPUT_SOURCE & 0x07))
1248 1 {
1249 2 RTDSetBit(SD_CTRL_70, 0xf9, TMDS_ICLK_DELAY);
1250 2
1251 2 usIPH_ACT_STA = CAP_WIN[ucMode_Curr][1];
1252 2 }
1253 1 else
1254 1 {
1255 2
1256 2 if (ucOption & 0x40)
1257 2 {
1258 3 // Only VGA-50Hz and VGA-60Hz mode will set bit 6 of ucMode_Curr to indicate 720-pixel capture width
1259 3 // In these case, we should use 720 horizontal settings instead of 640 horizontal settings in table.
1260 3 usADC_Clock = CAP_WIN[MODE_0720x0400x70HZ][0];
1261 3 usIPH_ACT_STA = CAP_WIN[MODE_0720x0400x70HZ][1];
1262 3 usIPH_ACT_WID = CAP_WIN[MODE_0720x0400x70HZ][2];
1263 3 }
1264 2 else
1265 2 {
1266 3 usADC_Clock = CAP_WIN[ucMode_Curr][0];
1267 3 usIPH_ACT_STA = CAP_WIN[ucMode_Curr][1];
1268 3 usIPH_ACT_WID = CAP_WIN[ucMode_Curr][2];
1269 3
1270 3 // Calculate pixel clock rate (round to MHz)
1271 3 usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
1272 3 usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
1273 3
1274 3 // Use ADC to do H scale-down if pixel clock rate is over spec.
1275 3 if (MAX_ADC_FREQ < usDispLen && MODE_USER1152x864 <= ucMode_Curr && MODE_USER1600x1200 >= ucMode_Curr)
1276 3 {
1277 4 usADC_Clock = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][0];
1278 4 usIPH_ACT_STA = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][1];
1279 4 usIPH_ACT_WID = ADC_SD_SET[ucMode_Curr - MODE_USER1152x864][2];
1280 4 }
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 22
1281 3
1282 3 } //if (ucOption & 0x40)
1283 2
1284 2 // Calculate pixel clock rate (round to MHz)
1285 2 usDispLen = (unsigned long)24576 * usADC_Clock / ((unsigned long)usHsync * 500);
1286 2 usDispLen = (usDispLen >> 1) + (usDispLen & 0x01);
1287 2
1288 2
1289 2 // To improve ADC performance ,when the data rate is slow, use single channel,otherwise, use dual channel
1290 2 RTDSetBit(ADC_REG_CLK_EA,0xe0,(45 > usDispLen) ? 0x10 | (ADC_RED_PHASE_FT & 0x0c) |( ADC_BLUE_PHASE_FT &
-0x03):
1291 2 0x00 | (ADC_RED_PHASE_FT & 0x0c) |( ADC_BLUE_PHASE_FT &
-0x03));
1292 2
1293 2
1294 2 // To imporve the FIFO efficiency only when input data rate is slow, and display data rate is high.
1295 2 // RTDSetBit(VGIP_CTRL_04, 0xe3, (40 > usDispLen) ? 0x14 : 0x00);
1296 2 RTDSetBit(VGIP_CTRL_04, 0xf3, (60 > usDispLen) ? 0x08 : 0x00);
1297 2
1298 2 RTDSetByte(PE_CONTROL_3C, 0x00); // HSYNC positive/negtive tracking
1299 2
1300 2 RTDSetByte(ADC_FRAME_MODULE_EB,0x06);
1301 2 // RTDSetByte(ADC_FRAME_MODULE_EB,(usIPH_ACT_WID == 1280) ? 0x04 : 0x00);
1302 2
1303 2
1304 2 // Set ADC bandwidth to reduce high frequency noise
1305 2 // RTDSetByte(ADC_REG_TEST_E9, (35 > usDispLen) ? 0x08 : (150 > usDispLen) ? 0x10 : 0x18);
1306 2
1307 2
1308 2
1309 2 #if(ADC_DEFFERENTIAL)
1310 2 RTDSetBit(ADC_DIFF_MODE_EC,0xff,0x40); //Differential mode
1311 2 #else
RTDSetBit(ADC_DIFF_MODE_EC,0xbf,0x00); //Single endded mode
#endif
1314 2
1315 2
1316 2
1317 2
1318 2 RTDSetByte(ADC_REG_CUR_H_E8, 0x0d | (ADC_GREEN_PHASE_FT & 0x30));
1319 2
1320 2
1321 2
1322 2 RTDSetBit(ADC_FRAME_MODULE_EB,0xc7, ((ADC_RED_PHASE_FT & 0x10) << 1) | ((ADC_GREEN_PHASE_FT & 0x40) <<
- 2)
1323 2 |((ADC_BLUE_PHASE_FT & 0x04) << 1));
1324 2
1325 2
1326 2
1327 2 RTDSetBit(TMDS_CORRECTION_FF,0xff,0x04); //Enable the ADC digital filter
1328 2
1329 2
1330 2 if(ucMode_Curr < MODE_1024x0768x70HZ)
1331 2 RTDSetByte(ADC_REG_TEST_E9, 0x08);
1332 2 else
1333 2 RTDSetByte(ADC_REG_TEST_E9, 0x10);
1334 2
1335 2
1336 2 // Get usIPV_ACT_LEN
1337 2 if (MODE_UNDEFINED0 > ucMode_Curr)
1338 2 {
1339 3 // We've already decided usIPV_ACT_LEN in Detect_VGA_Mode() for undefined SU/SD mode.
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 23
1340 3 // Only defined modes need to decide usIPV_ACT_LEN here.
1341 3 usIPV_ACT_LEN = CAP_WIN[ucMode_Curr][4];
1342 3 }
1343 2
1344 2 } //if (SOURCE_DVI == (stGUD1.INPUT_SOURCE & 0x07))
1345 1
1346 1 // Get standard usIPV_ACT_STA
1347 1
1348 1 RTDSetByte(IVS_DELAY_8C, PROGRAM_VDELAY);
1349 1
1350 1 usIPV_ACT_STA = CAP_WIN[ucMode_Curr][3] - PROGRAM_VDELAY - 1;
1351 1
1352 1
1353 1 RTDSetByte(IHS_DELAY_8D, PROGRAM_HDELAY);
1354 1
1355 1 // usIPH_ACT_STA = usIPH_ACT_STA + CAPTURE_HDELAY - PROGRAM_HDELAY;
1356 1 if(ucMode_Curr < MODE_0800x0600x75HZ)
1357 1 Data[0] = 2;
1358 1 else if(ucMode_Curr < MODE_1280x1024x75HZ)
1359 1 Data[0] = 5;
1360 1 else
1361 1 Data[0] = 3;
1362 1
1363 1 // Data[0] = 5;
1364 1 usIPH_ACT_STA = usIPH_ACT_STA + Data[0] - PROGRAM_HDELAY;
1365 1
1366 1 // Decide display length (height) and store to usDispLen
1367 1
1368 1 usDispLen = Mode_Preset[ucMode_Curr][2];
1369 1
1370 1 if (MODE_UNDEFINED0 == ucMode_Curr) // partical-screen scale-up mode
1371 1 {
1372 2 if (ucOption & 0x80) // partial-V
1373 2 {
1374 3 if (MIN_DV_TOTAL > (usVsync - 1))
1375 3 usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
1376 3 else
1377 3 usDispLen = usIPV_ACT_LEN; // No V scale-up
1378 3 }
1379 2 }
1380 1 else if (MODE_UNDEFINED1 == ucMode_Curr) // partial-screen scale-down mode
1381 1 {
1382 2 if (ucOption & 0x80) // partial-V
1383 2 {
1384 3 usDispLen = (unsigned long)usIPV_ACT_LEN * MIN_DV_TOTAL / (usVsync - 1);
1385 3 }
1386 2 } //if (MODE_UNDEFINED0 == ucMode_Curr) // partical-screen scale-up mode
1387 1
1388 1 if (Mode_Preset[ucMode_Curr][2] < usDispLen) usDispLen = Mode_Preset[ucMode_Curr][2];
1389 1
1390 1 // This F/W do not support V scale-up(or bypass) and H scale-down simultaneously
1391 1 if (usDispLen >= usIPV_ACT_LEN && Mode_Preset[ucMode_Curr][1] < usIPH_ACT_WID)
1392 1 {
1393 2 usIPH_ACT_WID = Mode_Preset[ucMode_Curr][1];
1394 2 }
1395 1
1396 1 if (usDispLen > usIPV_ACT_LEN) ucOption |= 0x01; // bit 0 : V scale-up
1397 1 if (usDispLen < usIPV_ACT_LEN) ucOption |= 0x02; // bit 1 : V scale-down
1398 1 if (Mode_Preset[ucMode_Curr][1] > usIPH_ACT_WID) ucOption |= 0x04; // bit 2 : H scale-up
1399 1 if (Mode_Preset[ucMode_Curr][1] < usIPH_ACT_WID) ucOption |= 0x08; // bit 3 : H scale-down
1400 1
1401 1 // Set capture window
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 24
1402 1 Data[0] = 11;
1403 1 Data[1] = Y_INC;
1404 1 Data[2] = IPH_ACT_STA_06;
1405 1 Data[3] = (unsigned char)usIPH_ACT_STA;
1406 1 Data[4] = (unsigned char)(usIPH_ACT_STA >> 8);
1407 1 Data[5] = (unsigned char)usIPH_ACT_WID;
1408 1 Data[6] = (unsigned char)(usIPH_ACT_WID >> 8);
1409 1 Data[7] = (unsigned char)usIPV_ACT_STA;
1410 1 Data[8] = (unsigned char)(usIPV_ACT_STA >> 8);
1411 1 Data[9] = (unsigned char)usIPV_ACT_LEN;
1412 1 Data[10] = (unsigned char)(usIPV_ACT_LEN >> 8);
1413 1 Data[11] = 0;
1414 1 RTDWrite(Data);
1415 1
1416 1 // Set window size before scale-up
1417 1 Data[0] = 7;
1418 1 Data[1] = Y_INC;
1419 1 Data[2] = DRW_BSU_40;
1420 1
1421 1 if (ucOption & 0x08)
1422 1 {
1423 2 // H scale-down
1424 2 Data[3] = (unsigned char)Mode_Preset[ucMode_Curr][1];
1425 2 Data[4] = (unsigned char)(Mode_Preset[ucMode_Curr][1] >> 8);
1426 2 }
1427 1 else
1428 1 {
1429 2 // No H scale-down
1430 2 Data[3] = Data[5]; // (unsigned char)usIPH_ACT_WID;
1431 2 Data[4] = Data[6]; // (unsigned char)(usIPH_ACT_WID >> 8);
1432 2 }
1433 1
1434 1 if (ucOption & 0x02)
1435 1 {
1436 2 // V scale-down
1437 2 Data[5] = (unsigned char)usDispLen;
1438 2 Data[6] = (unsigned char)(usDispLen >> 8);
1439 2 }
1440 1 else
1441 1 {
1442 2 // No V scale-down
1443 2 Data[5] = Data[9]; // (unsigned char)usIPV_ACT_LEN;
1444 2 Data[6] = Data[10]; // (unsigned char)(usIPV_ACT_LEN >> 8);
1445 2 }
1446 1 Data[7] = 0;
1447 1 RTDWrite(Data);
1448 1
1449 1 // Config scaling
1450 1 if (ucOption & 0x0a)
1451 1 RTDSetBit(SD_CTRL_70, 0xff, 0x01); // Turn on scale-down
1452 1 else
1453 1 RTDSetBit(SD_CTRL_70, 0xfe, 0x00); // Turn off scale-down
1454 1
1455 1 if (ucOption & 0x01)
1456 1 RTDSetBit(SCALE_CTRL_15, 0xff, 0x02); // Turn on V scale-up
1457 1 else
1458 1 RTDSetBit(SCALE_CTRL_15, 0xfd, 0x00); // Turn off V scale-up
1459 1
1460 1 if (ucOption & 0x04)
1461 1 RTDSetBit(SCALE_CTRL_15, 0xff, 0x01); // Turn on H scale-up
1462 1 else
1463 1 RTDSetBit(SCALE_CTRL_15, 0xfe, 0x00); // Turn off H scale-up
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 25
1464 1
1465 1 // Set scale-down coefficient
1466 1 Data[0] = 7;
1467 1 Data[1] = Y_INC;
1468 1 Data[2] = H_SCALE_DL_71;
1469 1
1470 1 if (ucOption & 0x08) // H scale-down
1471 1 {
1472 2 // Data[12~15]
1473 2 ((unsigned long *)Data)[3] = (unsigned long)256 * 4096 * usIPH_ACT_WID / Mode_Preset[ucMode_Curr]
-[1];
1474 2
1475 2 // Data[4~5]
1476 2 ((unsigned int *)Data)[2] = (((unsigned long *)Data)[3] >> 8) + 2;
1477 2
1478 2 // H scale-down factor is stored in Data[4] (high-byte) and Data[5] (low-byte)
1479 2 Data[3] = Data[5];
1480 2
1481 2 RTDSetBit(VGIP_CTRL_04, 0xff, 0x40); // Enable H scale-down compensation
1482 2 }
1483 1 else
1484 1 {
1485 2 Data[3] = 0x00;
1486 2 Data[4] = 0x10;
1487 2
1488 2 RTDSetBit(VGIP_CTRL_04, 0xbf, 0x00); // Diable H scale-down compensation
1489 2 }
1490 1
1491 1 if (ucOption & 0x02) // V scale-down
1492 1 {
1493 2 // Data[12~15]
1494 2 ((unsigned long *)Data)[3] = (unsigned long)256 * 4096 * usIPV_ACT_LEN / usDispLen;
1495 2
1496 2 // Data[6~7]
1497 2 ((unsigned int *)Data)[3] = (((unsigned long *)Data)[3] >> 8);
1498 2
1499 2 if (0 == Data[15]) ((unsigned int *)Data)[3] = ((unsigned int *)Data)[3] - 1;
1500 2
1501 2 // V scale-down factor is stored in Data[6] (high-byte) and Data[7] (low-byte)
1502 2 Data[5] = Data[7];
1503 2
1504 2 RTDSetBit(VGIP_CTRL_04, 0xff, 0x80); // Enable V scale-down compensation
1505 2 }
1506 1 else
1507 1 {
1508 2 Data[5] = 0x00;
1509 2 Data[6] = 0x10;
1510 2
1511 2 RTDSetBit(VGIP_CTRL_04, 0x7f, 0x00); // Diable V scale-down compensation
1512 2 }
1513 1 Data[7] = 0;
1514 1 RTDWrite(Data);
1515 1
1516 1 // Set scale-up coefficient
1517 1 Data[0] = 8;
1518 1 Data[1] = Y_INC;
1519 1 Data[2] = HOR_SCA_16;
1520 1
1521 1 if (ucOption & 0x04) // H scale-up
1522 1 {
1523 2 // Data[12~15]
1524 2 ((unsigned long *)Data)[3] = (unsigned long)2 * 262144 * usIPH_ACT_WID / Mode_Preset[ucMode_Curr]
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 26
-[1];
1525 2 ((unsigned long *)Data)[3] = ((((unsigned long *)Data)[3] >> 1) + (((unsigned long *)Data)[3] & 0
-x01)) << 6;
1526 2
1527 2 Data[3] = Data[14];
1528 2 Data[4] = Data[13];
1529 2 Data[7] = Data[15];
1530 2 }
1531 1 else
1532 1 {
1533 2 Data[3] = 0xff;
1534 2 Data[4] = 0xff;
1535 2 Data[7] = 0;
1536 2 }
1537 1
1538 1 if (ucOption & 0x01) // V scale-up
1539 1 {
1540 2 // Data[12~15]
1541 2 ((unsigned long *)Data)[3] = (unsigned long)2 * 262144 * usIPV_ACT_LEN / usDispLen;
1542 2 ((unsigned long *)Data)[3] = ((((unsigned long *)Data)[3] >> 1) + (((unsigned long *)Data)[3] & 0
-x01)) << 6;
1543 2
1544 2 Data[5] = Data[14]; //anson 05_0315
1545 2 // Data[5] = 0x90;
1546 2 Data[6] = Data[13];
1547 2 // Data[6] = 0xc0;
1548 2 Data[7] = Data[7] | (Data[15] >> 4);
1549 2 }
1550 1 else
1551 1 {
1552 2 Data[5] = 0xff;
1553 2 Data[6] = 0xff;
1554 2 }
1555 1 Data[8] = 0;
1556 1 RTDWrite(Data);
1557 1
1558 1 // Set RTD display
1559 1
1560 1 // Switch to FrameSync 1 mode and diable display
1561 1 RTDSetByte(VDIS_CTRL_20, 0x28 | DISP_BIT | DISPLAY_PORT);
1562 1
1563 1 Data[0] = 5;
1564 1 Data[1] = Y_INC;
1565 1
1566 1 #if (DISP_ALIGN)
Data[2] = DH_ACT_STA_27;
// DH_ACT_STA store in Data[4~5] (H~L)
((unsigned int *)Data)[2] = (unsigned int)DH_ACT_END_POS - Mode_Preset[ucMode_Curr][1];
Data[3] = Data[5];
#else
1576 1
1577 1 Data[2] = DH_ACT_END_29;
1578 1
1579 1 // DH_ACT_STA store in Data[4~5] (H~L)
1580 1 ((unsigned int *)Data)[2] = (unsigned int)DH_ACT_STA_POS + Mode_Preset[ucMode_Curr][1];
1581 1
1582 1 Data[3] = Data[5];
1583 1
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 27
1584 1 #endif
1585 1
1586 1 Data[5] = 5;
1587 1 Data[6] = Y_INC;
1588 1 Data[7] = DV_ACT_END_34;
1589 1
1590 1 // DV_ACT_END store in Data[10~11] (H~L)
1591 1 ((unsigned int *)Data)[5] = (unsigned int)DV_ACT_STA_POS + usDispLen;
1592 1
1593 1 Data[8] = Data[11];
1594 1 Data[9] = Data[10];
1595 1 Data[10] = 0;
1596 1 RTDWrite(Data);
1597 1
1598 1 // Get standard DH_TOTAL
1599 1 usDH_Total = Mode_Preset[ucMode_Curr][0];
1600 1
1601 1 // Switch to FrameSync 1 mode and enable display
1602 1 // if (PANEL_OFF == bPANEL_PWR)
1603 1 if (_OFF == bPanel_Status)
1604 1 RTDSetByte(VDIS_CTRL_20, 0x29 | DISP_BIT | DISPLAY_PORT);
1605 1 else
1606 1 RTDSetByte(VDIS_CTRL_20, 0x2b | DISP_BIT | DISPLAY_PORT);
1607 1
1608 1 Set_Dclk(usDispLen);
1609 1
1610 1 //usDH_Total = usDH_Total - 2;
1611 1
1612 1 // Set DH_TOTAL
1613 1 Data[0] = 5;
1614 1 Data[1] = Y_INC;
1615 1 Data[2] = DH_TOTAL_22;
1616 1 Data[3] = (unsigned char)(usDH_Total - 2);
1617 1 Data[4] = (unsigned char)((usDH_Total - 2) >> 8);
1618 1 Data[5] = 0;
1619 1 RTDWrite(Data);
1620 1
1621 1
1622 1
1623 1 //Calculate DV_TOTAL
1624 1 if((ucOption & 0x01) || (ucOption & 0x02)) // V scale up or scale down
1625 1 {
1626 2
1627 2 #if(DISP_SIZE == DISP_800x600)
usDV_Total = (unsigned long)usVsync * 600 / (unsigned long)usIPV_ACT_LEN + 64;
#endif
1630 2
1631 2 #if(DISP_SIZE == DISP_1024x768)
usDV_Total = (unsigned long)usVsync * 768 / (unsigned long)usIPV_ACT_LEN + 64;
#endif
1634 2
1635 2 #if(DISP_SIZE == DISP_1280x1024)
1636 2
1637 2 usDV_Total = (unsigned long)usVsync * 1024 / (unsigned long)usIPV_ACT_LEN + 64;
1638 2 #endif
1639 2
1640 2
1641 2 }
1642 1 else
1643 1 usDV_Total = usVsync + 64;
1644 1
1645 1 //Set DV_TOTAL
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 28
1646 1 Data[0] = 5;
1647 1 Data[1] = Y_INC;
1648 1 Data[2] = DV_TOTAL_2D;
1649 1 Data[3] = (unsigned char)usDV_Total;
1650 1 Data[4] = (unsigned char)((usDV_Total >> 8) & 0x07);
1651 1 Data[5] = 0;
1652 1 RTDWrite(Data);
1653 1
1654 1
1655 1
1656 1
1657 1 // Calculate suitable IVS to DVS delay
1658 1 // CR[38] : IVS to DVS delay in IHS lines
1659 1 // CR[1E] : IVS to DVS delay in ICLK * 16
1660 1 //((unsigned int *)Data)[0] = (unsigned long)64 * DV_ACT_STA_POS * usIPV_ACT_LEN / usDispLen;
1661 1 ((unsigned int *)Data)[0] = (unsigned long)64 * DV_ACT_STA_POS * usIPV_ACT_LEN / usDispLen;
1662 1
1663 1 if (ucOption & 0x01)
1664 1 {
1665 2 Calculate_IVS2DVS_Delay(2,5,((unsigned int*)Data)[0]); // V scale-up. Target 2.5~2.6 IHS delay
1666 2
1667 2 }
1668 1 else
1669 1 {
1670 2 #if (FULL_LINE_BUFFER)
Calculate_IVS2DVS_Delay(3,8,((unsigned int*)Data)[0]); // V no scale-up. Target 3.8~4.0 IHS delay
#else
1673 2 if (ucOption & 0x02)
1674 2 {
1675 3 // V scale-down
1676 3 Calculate_IVS2DVS_Delay(2,6,((unsigned int*)Data)[0]); // V scale-down. Target 2.5~2.6 IHS delay
1677 3 }
1678 2 else
1679 2 {
1680 3
1681 3 Calculate_IVS2DVS_Delay(1,9,((unsigned int*)Data)[0]); // V no scale-up. Targ
-et 1.9 IHS delay
1682 3 }
1683 2
1684 2 #endif
1685 2 }
1686 1
1687 1 #if (FULL_LINE_BUFFER)
// Turn on full-line buffer when no V scale-up
RTDSetBit(OP_CRC_CTRL_68, 0xfc, (ucOption & 0x01) ? 0x00 : 0x02);
#else
1691 1 RTDSetBit(OP_CRC_CTRL_68, 0xfc, 0x00);
1692 1 #endif
1693 1
1694 1 // Set ucDV_Delay
1695 1 RTDSetByte(IV_DV_LINES_38, ucDV_Delay);
1696 1
1697 1 RTDSetByte(STATUS0_01, 0x00); // Clear status
1698 1 RTDSetByte(STATUS1_1F, 0x00); // Clear status
1699 1
1700 1 // Switch to FrameSync 1 mode and enable display
1701 1 // if (PANEL_OFF == bPANEL_PWR)
1702 1 // RTDSetByte(VDIS_CTRL_20, 0x29 | DISP_BIT | DISPLAY_PORT);
1703 1 // else
1704 1 // RTDSetByte(VDIS_CTRL_20, 0x2b | DISP_BIT | DISPLAY_PORT);
1705 1
1706 1 // Input Run Enable
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 29
1707 1 RTDSetBit(VGIP_CTRL_04, 0xff, 0x01);
1708 1
1709 1 }
1710
1711 void Display_VGA_Set(void)
1712 {
1713 1 unsigned char Wait_Time_Cnt;
1714 1 // unsigned char ucI_Corr0,ucI_Corr1;
1715 1
1716 1
1717 1 Initial_Mode();
1718 1 Sharpness();
1719 1
1720 1 if((usIPH_ACT_WID == 1280) && (DISP_SIZE == DISP_1280x1024) && (stGUD1.FILTER == 0x02))
1721 1 RTDSetBit(SCALE_CTRL_15, 0xff, 0x01); // Turn on H scale-up
1722 1
1723 1
1724 1 PowerDown_ADC();
1725 1 //Device_Power(ADC_POWER,OFF);
1726 1
1727 1 // Set user's ADC gain and offset settings
1728 1 SetADC_GainOffset();
1729 1
1730 1 Set_Gamma();
1731 1 Set_Dithering();
1732 1 Set_Bright_Contrast();
1733 1 // Sharpness();
1734 1
1735 1 Load_MUD(ucMode_Curr); // Read mode default settings from 24C04
1736 1
1737 1 // For jitter adjust
1738 1 ucPE_Level = 0;
1739 1 // ucPE_Count = 0;
1740 1
1741 1 // Check Clock
1742 1 if (28 > stMUD.CLOCK || 228 < stMUD.CLOCK) stMUD.CLOCK = 128;
1743 1
1744 1
1745 1 // Update Clock Twice
1746 1 Set_Clock();
1747 1 // Calculate the P correction and I correction according to the CE value
1748 1 Delay_Xms(6);
1749 1
1750 1 if(ucCE_Value == 0)
1751 1 {
1752 2 RTDRead(I_CODE_MB_CA,1,N_INC);
1753 2 RTDSetByte(I_CODE_MB_CA, 0x0d);
1754 2 Delay_Xms(4);
1755 2 RTDRead(PLL_CALIBRATION_CE,1,N_INC);
1756 2 ucP_Corr = (unsigned char)((unsigned int)(Data[0] * 200) >> (29 - P_Code));
1757 2 ucCE_Value = Data[0]; //CE value
1758 2
1759 2 }
1760 1
1761 1 if(ucI_Code == 0)
1762 1 Adjust_I_Code();
1763 1
1764 1
1765 1 Set_Clock();
1766 1
1767 1
1768 1 // Check Phase
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 30
1769 1 // stMUD.PHASE &= 0x7c; // Phase 0~31
1770 1
1771 1 // Update Phase
1772 1 // Set_Phase(stMUD.PHASE);
1773 1
1774 1 ucH_Max_Margin = 128 + 50;
1775 1 ucH_Min_Margin = 128 - 50;
1776 1
1777 1 //Read the usIPH_ACT_STA offset
1778 1 I2CRead(ADDR_EROM1,(ucMode_Curr - 1),0x01);
1779 1 if(Data[0] > 228)
1780 1 Data[0] = 0;
1781 1
1782 1 usIPH_ACT_STA = (Data[0] & 0x80) ? usIPH_ACT_STA - 50 - (Data[0] - 0x80) : usIPH_ACT_STA + Data[0] -
- 50;
1783 1
1784 1 Data[0] = 5;
1785 1 Data[1] = Y_INC;
1786 1 Data[2] = IPH_ACT_STA_06;
1787 1 Data[3] = (unsigned char)usIPH_ACT_STA;
1788 1 Data[4] = (unsigned char)(usIPH_ACT_STA >> 8);
1789 1 Data[5] = 0;
1790 1 RTDWrite(Data);
1791 1
1792 1 // Check H-Position
1793 1 if (ucH_Max_Margin < stMUD.H_POSITION)
1794 1 stMUD.H_POSITION = ucH_Max_Margin;
1795 1 else if (ucH_Min_Margin > stMUD.H_POSITION)
1796 1 stMUD.H_POSITION = ucH_Min_Margin;
1797 1
1798 1 // Update H-Position
1799 1 Set_H_Position();
1800 1
1801 1 // Check Phase
1802 1 stMUD.PHASE &= 0x7c; // Phase 0~31
1803 1
1804 1 // Update Phase
1805 1 Set_Phase(stMUD.PHASE);
1806 1
1807 1 // Start auto-tracking function once
1808 1 RTDSetByte(AUTO_ADJ_CTRL_7F, 0x01);
1809 1 Delay_Xms(40);
1810 1
1811 1 // Force to stop auto-tracking function
1812 1 RTDSetByte(AUTO_ADJ_CTRL_7F, 0x00);
1813 1 Delay_Xms(40);
1814 1
1815 1 // Measure actual number of scan line in each frame
1816 1 Data[0] = 14;
1817 1 Data[1] = Y_INC;
1818 1 Data[2] = H_BND_STA_L_75;
1819 1 Data[3] = 0x00;
1820 1 Data[4] = 0xff;
1821 1 Data[5] = 0x07;
1822 1 Data[6] = 0x00;
1823 1 Data[7] = 0x00;
1824 1 Data[8] = 0x00;
1825 1 Data[9] = 0x00;
1826 1 Data[10] = 0x00;
1827 1 Data[11] = 0x00;
1828 1 Data[12] = 0x00;
1829 1 Data[13] = 0x01;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 31
1830 1 Data[14] = 0;
1831 1 RTDWrite(Data);
1832 1
1833 1 Wait_Time_Cnt = 60; // Tracking timeout 60ms
1834 1 do
1835 1 {
1836 2 Delay_Xms(1);
1837 2 RTDRead(AUTO_ADJ_CTRL_7F, 0x01, N_INC);
1838 2 }
1839 1 while ((Data[0] & 0x01) && (--Wait_Time_Cnt));
1840 1
1841 1 RTDSetByte(AUTO_ADJ_CTRL_7F, 0x00);
1842 1
1843 1 if (Wait_Time_Cnt)
1844 1 {
1845 2 RTDRead(VER_START_80, 0x04, Y_INC);
1846 2 Data[0] = Data[3] & 0x0f;
1847 2 Data[1] = Data[2];
1848 2
1849 2 usVer_End = (usVsync < ((unsigned int *)Data)[0]) ? ((unsigned int *)Data)[0] : usVsync;
1850 2 }
1851 1 else
1852 1 {
1853 2 usVer_End = usVsync;
1854 2 }
1855 1
1856 1 // Update to reasonable usIPV_ACT_STA for user mode
1857 1 if (MODE_USER720x400 <= ucMode_Curr)
1858 1 {
1859 2 ((unsigned int *)Data)[0] = usVer_End - VGA_Mode[ucMode_Curr][2];
1860 2
1861 2 if (254 < ((unsigned int *)Data)[0] + ucDV_Delay) ((unsigned int *)Data)[0] = 254 - ucDV_Delay
-;
1862 2
1863 2 usIPV_ACT_STA += ((unsigned int *)Data)[0];
1864 2 ucDV_Delay += ((unsigned int *)Data)[0];
1865 2 }
1866 1
1867 1 // Set the ucV_Min_Margin/ucV_Max_Margin
1868 1 ucV_Min_Margin = (128 < usIPV_ACT_STA) ? 0 : 128 - usIPV_ACT_STA + 1;
1869 1
1870 1 if ((128 - 50) > ucV_Min_Margin) ucV_Min_Margin = 128 - 50;
1871 1
1872 1 ((unsigned int *)Data)[0] = (usVer_End + 128 - 2) - (usIPV_ACT_STA + usIPV_ACT_LEN);
1873 1
1874 1 ucV_Max_Margin = (((unsigned int *)Data)[0] > 0x00ff) ? 0xff : ((unsigned int *)Data)[0];
1875 1
1876 1 // Check ucV_Min_Margin/ucV_Max_Margin :
1877 1 // ucDV_Delay can only range from 0 to 254
1878 1 // Original Formula :
1879 1 // 128 - ucV_Min_Margin >= ucDV_Delay
1880 1 // ucV_Max_Margin - 128 >= 254 - ucDV_Delay
1881 1
1882 1 if ((unsigned int)128 > ((unsigned int)ucV_Min_Margin + ucDV_Delay)) ucV_Min_Margin = 128 - ucDV_D
-elay;
1883 1 if ((unsigned int)382 < ((unsigned int)ucV_Max_Margin + ucDV_Delay)) ucV_Max_Margin = 382 - ucDV_D
-elay;
1884 1
1885 1 if ((128 + 50) < ucV_Max_Margin) ucV_Max_Margin = 128 + 50;
1886 1
1887 1 // Check V-Position
1888 1 if (ucV_Min_Margin > stMUD.V_POSITION)
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 32
1889 1 stMUD.V_POSITION = ucV_Min_Margin;
1890 1 else if ((unsigned int)256 - ucV_Min_Margin < stMUD.V_POSITION)
1891 1 stMUD.V_POSITION = (unsigned int)256 - ucV_Min_Margin;
1892 1
1893 1 // Update V-Position
1894 1 Set_V_Position();
1895 1
1896 1 // Re-calculate actual refresh rate
1897 1 ((unsigned long *)Data)[0] = (unsigned long)usHsync * usVer_End;
1898 1 ucRefresh = (unsigned long)49152000 / ((unsigned long *)Data)[0];
1899 1 ucRefresh = (ucRefresh & 0x01) ? ((ucRefresh + 1) >> 1) : (ucRefresh >> 1);
1900 1
1901 1 if(ucRefresh > V_OVERSPEC_FREQ)
1902 1 bOverSpec = _TRUE;
1903 1
1904 1 if((unsigned int)24576/usHsync > H_OVERSPEC_FREQ)
1905 1 bOverSpec = _TRUE;
1906 1
1907 1 Data[0] = Frame_Sync();
1908 1
1909 1 if (1 == Data[0])
1910 1 {
1911 2 Delay_Xms(10);
1912 2 Data[0] = Frame_Sync(); // Fail. Try again
1913 2 }
1914 1
1915 1 bFrameSync = Data[0] ? 0 : 1; // 0 : fail, 1 : pass
1916 1 ucSyncErrorCnt = 0;
1917 1
1918 1 RTDSetBit(OVL_CTRL_6D,0x3f,0x00);
1919 1 RTDSetByte(BGCOLOR_CONTROL_6C,0x00);
1920 1 RTDSetBit(OVL_CTRL_6D,0x3f,0x40);
1921 1 RTDSetByte(BGCOLOR_CONTROL_6C,0x00);
1922 1 RTDSetBit(OVL_CTRL_6D,0x3f,0x80);
1923 1 RTDSetByte(BGCOLOR_CONTROL_6C,0x00);
1924 1
1925 1 // RTDSetBit(VDIS_CTRL_20, 0x5f, DHS_MASK); // Normal display
1926 1 RTDSetBit(VDIS_CTRL_20, 0x7f, 0x20 | DHS_MASK); // Normal display
1927 1
1928 1 #if(AS_PLL_NONLOCK)
1929 1 if(bFrameSync)
1930 1 RTDSetBit(ODD_CTRL_8E,0xdf,0x20);
1931 1 #endif
1932 1
1933 1 //anson 05_0314
1934 1 ucfrist = (ucMode_Curr - 1 ) / 8 ;
1935 1 I2CRead(ADDR_EROM1, ucfrist , 1);
1936 1 ucfrist = ucMode_Curr - (ucfrist*8) ;
1937 1 ucfrist = Data[0] >> (ucfrist-1) ;
1938 1 ucfrist = ucfrist & 0x01;
1939 1 stGUD1.OSD_INPUT = stGUD1.OSD_INPUT | 0x20; //First Time Into This Mode
1940 1
1941 1
1942 1 }
1943
1944 void Display_DVI_Set(void)
1945 {
1946 1 #if(TMDS_ENABLE)
1947 1 unsigned char Wait_Time_Cnt;
1948 1
1949 1 Initial_Mode();
1950 1
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 33
1951 1 // Set the ucV_Min_Margin/ucV_Max_Margin
1952 1 ucV_Min_Margin = (128 < usIPV_ACT_STA) ? 0 : 128 - usIPV_ACT_STA + 1;
1953 1
1954 1 // Use Data[8],Data[9] as a temporary 16-bit variable.
1955 1 ((unsigned int *)Data)[4] = (usVsync + 128 - 2) - (usIPV_ACT_STA + usIPV_ACT_LEN);
1956 1
1957 1 ucV_Max_Margin = (0x00ff < ((unsigned int *)Data)[4]) ? 0xff : ((unsigned int *)Data)[4];
1958 1
1959 1 // Check ucV_Min_Margin/ucV_Max_Margin :
1960 1 // ucDV_Delay can only range from 0 to 254
1961 1 // Original Formula :
1962 1 // 128 - ucV_Min_Margin <= ucDV_Delay
1963 1 // ucV_Max_Margin - 128 <= 254 - ucDV_Delay
1964 1
1965 1 if ((unsigned int)128 > ((unsigned int)ucV_Min_Margin + ucDV_Delay)) ucV_Min_Margin = 128 - ucDV_D
-elay;
1966 1 if ((unsigned int)382 < ((unsigned int)ucV_Max_Margin + ucDV_Delay)) ucV_Max_Margin = 382 - ucDV_D
-elay;
1967 1
1968 1 // Read mode default settings from 24C04
1969 1 Load_MUD(ucMode_Curr);
1970 1
1971 1 Set_Gamma();
1972 1 Set_Dithering();
1973 1 Set_Bright_Contrast();
1974 1 Sharpness();
1975 1
1976 1 // Issac :
1977 1 // RTD controller can support both digital mode and analog mode to capture input image data.
1978 1 // In digital mode, input image data is captured according to input data enable (IDEN) signal;
1979 1 // In analog mode, input image data is captured according to capture window settings;
1980 1 // Although can support both of them, I always use analog mode to capture input image in this F/W.
1981 1 // Because RTD controller can measure the position and size of IDEN signal, we can just set our
1982 1 // capture window to be the same size and position as IDEN.
1983 1
1984 1 Data[0] = 14;
1985 1 Data[1] = Y_INC;
1986 1 Data[2] = H_BND_STA_L_75;
1987 1 Data[3] = 0x02;
1988 1 Data[4] = usADC_Clock - 2;
1989 1 Data[5] = (usADC_Clock - 2) >> 8;
1990 1 Data[6] = 0x02;
1991 1 Data[7] = usVsync - 2;
1992 1 Data[8] = (usVsync - 2) >> 8;
1993 1 Data[9] = 0;
1994 1 Data[10] = 0;
1995 1 Data[11] = 0;
1996 1 Data[12] = 0;
1997 1 Data[13] = 0x81; // Measure IDEN position
1998 1 Data[14] = 0;
1999 1
2000 1
2001 1 RTDWrite(Data);
2002 1
2003 1 Wait_Time_Cnt = 60; // Tracking timeout 60ms
2004 1 do
2005 1 {
2006 2 Delay_Xms(1);
2007 2 RTDRead(AUTO_ADJ_CTRL_7F, 0x01, N_INC);
2008 2 }
2009 1 while ((Data[0] & 0x01) && (--Wait_Time_Cnt));
2010 1
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 34
2011 1 if (0 == Wait_Time_Cnt)
2012 1 {
2013 2 RTDSetByte(AUTO_ADJ_CTRL_7F, 0x00);
2014 2 Reset_Mode();
2015 2 }
2016 1 else
2017 1 {
2018 2 // Read IDEN position information
2019 2 RTDRead(VER_START_80, 0x08, Y_INC);
2020 2
2021 2 // IDEN horizontal Start
2022 2 usIPH_ACT_STA = (unsigned int)Data[4] + ((unsigned int)Data[5] << 8) - 2;
2023 2
2024 2 // IDEN vertical Start
2025 2 ((unsigned int *)Data)[0] = (unsigned int)Data[0] + ((unsigned int)Data[1] << 8) - 1;
2026 2
2027 2 if (((unsigned int *)Data)[0] > (usIPV_ACT_STA + ucV_Max_Margin - 0x80))
2028 2 {
2029 3 ((unsigned int *)Data)[1] = (usVsync + 128 - 2) - (usIPV_ACT_STA + usIPV_ACT_LEN); // Act
-ual V max. Margin
2030 3
2031 3 ucDV_Delay = (unsigned char)((unsigned int)ucDV_Delay + ucV_Max_Margin - 0x80);
2032 3 usIPV_ACT_STA = usIPV_ACT_STA + ucV_Max_Margin - 0x80;
2033 3
2034 3 if (ucV_Max_Margin < ((unsigned int *)Data)[1])
2035 3 {
2036 4 // We have to increase IVS delay to fix ucV_Max_Margin
2037 4 if ((((unsigned int *)Data)[1] - ucV_Max_Margin) >= (((unsigned int *)Data)[0] - usIPV_ACT
-_STA))
2038 4 ((unsigned int *)Data)[1] = ((unsigned int *)Data)[0] - usIPV_ACT_STA + PROGRAM_VDEL
-AY;
2039 4 else
2040 4 ((unsigned int *)Data)[1] = usIPV_ACT_STA + ((unsigned int *)Data)[1] - ucV_Max_Marg
-in + PROGRAM_VDELAY;
2041 4
2042 4 if (126 < ((unsigned int *)Data)[1]) ((unsigned int *)Data)[1] = 126;
2043 4
2044 4 RTDSetByte(IVS_DELAY_8C, 0x80 | ((unsigned int *)Data)[1]);
2045 4 }
2046 3 }
2047 2 else if (((unsigned int *)Data)[0] < (usIPV_ACT_STA + ucV_Min_Margin - 0x80))
2048 2 {
2049 3 ucDV_Delay = (unsigned char)((unsigned int)ucDV_Delay + ucV_Min_Margin - 0x80);
2050 3 usIPV_ACT_STA = usIPV_ACT_STA + ucV_Min_Margin - 0x80;
2051 3
2052 3 ((unsigned int *)Data)[1] = usIPV_ACT_STA - ((unsigned int *)Data)[0];
2053 3
2054 3 // We have to decrease IVS delay to fix ucV_Min_Margin
2055 3 if (PROGRAM_VDELAY <= ((unsigned int *)Data)[1])
2056 3 RTDSetByte(IVS_DELAY_8C, 0x00);
2057 3 else
2058 3 RTDSetByte(IVS_DELAY_8C, 0x80 | (PROGRAM_VDELAY - ((unsigned int *)Data)[1]));
2059 3 }
2060 2 else
2061 2 {
2062 3 ucDV_Delay = ((unsigned int *)Data)[0] + ucDV_Delay - usIPV_ACT_STA ;
2063 3 usIPV_ACT_STA = ((unsigned int *)Data)[0];
2064 3 }
2065 2
2066 2 RTDRead(TMDS_CORRECTION_FF,0x01,N_INC);
2067 2
2068 2 if(Data[0] & 0x03)
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 35
2069 2 usIPH_ACT_STA -= 14;//if TMDS error correction enable, then compensate the IPH_ACT_STA offset.
2070 2
2071 2 Data[0] = 5;
2072 2 Data[1] = Y_INC;
2073 2 Data[2] = IPH_ACT_STA_06;
2074 2 Data[3] = (unsigned char)(usIPH_ACT_STA & 0x00ff);
2075 2 Data[4] = (unsigned char)((usIPH_ACT_STA >> 8) & 0x00ff);
2076 2 Data[5] = 5;
2077 2 Data[6] = Y_INC;
2078 2 Data[7] = IPV_ACT_STA_0A;
2079 2 Data[8] = (unsigned char)(usIPV_ACT_STA & 0x00ff);
2080 2 Data[9] = (unsigned char)((usIPV_ACT_STA >> 8) & 0x00ff);
2081 2 Data[10] = 4;
2082 2 Data[11] = N_INC;
2083 2 Data[12] = IV_DV_LINES_38;
2084 2 Data[13] = ucDV_Delay;
2085 2 Data[14] = 0;
2086 2 RTDWrite(Data);
2087 2
2088 2 Wait_For_Event(EVENT_DVS);
2089 2
2090 2 Data[0] = Frame_Sync();
2091 2
2092 2 if (1 == Data[0]) Data[0] = Frame_Sync(); // Fail. Try again
2093 2
2094 2 bFrameSync = Data[0] ? 0 : 1; // 0 : fail, 1 : pass
2095 2 ucSyncErrorCnt = 0;
2096 2
2097 2 //RTDSetBit(VDIS_CTRL_20, 0x5f, DHS_MASK); // Normal display
2098 2 RTDSetBit(VDIS_CTRL_20, 0x7f, 0x20 | DHS_MASK); // Normal display
2099 2 }
2100 1 #else
Seek_DVI_Mode(0);
#endif
2103 1 }
2104
2105 void Set_Video_Mode(void)
2106 {
2107 1 #if(VIDEO_CHIP != VDC_NONE)
#if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 || VIDEO_CHIP == VDC_SAA7118)
I2CWrite(V_DISABLE);
I2CWrite(VIDEO_ALL);
I2CWrite((ucAV_Mode & 0x02) ? VIDEO_50 : VIDEO_60);
#endif
RTDCodeW((ucAV_Mode & 0x02) ? RTD_VIDEO_50 : RTD_VIDEO_60);
// if (PANEL_OFF == MCU_ReadPanelPower())
if (OFF == bPanel_Status)
{
RTDSetByte(VDIS_SIGINV_21, 0x00 | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP); // DHS, DVS,
-DEN, DCLK MUST NOT be inverted.
RTDSetBit(VDIS_CTRL_20, 0xfd, 0x01); // DHS, DVS, DEN, DCLK and data are clamped to 0
}
#if (VIDEO_CHIP == VDC_SAA7118)
if (SOURCE_YUV == (stGUD1.INPUT_SOURCE & 0x07))
{
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 36
I2CWrite(VIDEO_YUV);
}
else
#endif
{
Data[0] = (SOURCE_SV == (stGUD1.INPUT_SOURCE & 0x07)) ? 0 : 1;
switch (ucAV_Mode)
{
case 0x01: //(60Hz) NTSC-M, JAPAN(7111A)
case 0x81: //(60Hz) Default
I2CWrite(Data[0] ? AV_60_0 : SV_60_0);
break;
case 0x11: //(60Hz) PAL-4.43
I2CWrite(Data[0] ? AV_60_1 : SV_60_1);
break;
case 0x21: //(60Hz) NTSC-4.43
I2CWrite(Data[0] ? AV_60_2 : SV_60_2);
break;
case 0x31: //(60Hz) PAL-M
I2CWrite(Data[0] ? AV_60_3 : SV_60_3);
break;
case 0x41: //(60Hz) NTSC-JAPAN(7114)
I2CWrite(Data[0] ? AV_60_4 : SV_60_4);
break;
case 0x02: //(50Hz) PAL-BGHI
case 0x82: //(50Hz) Default
I2CWrite(Data[0] ? AV_50_0 : SV_50_0);
RTDSetBit(VGIP_SIGINV_05,0xff,0x10);
break;
case 0x12: //(50Hz) NTSC-4.43
I2CWrite(Data[0] ? AV_50_1 : SV_50_1);
break;
case 0x22: //(50Hz) PAL-N
I2CWrite(Data[0] ? AV_50_2 : SV_50_2);
break;
case 0x32: //(50Hz) NTSC-N
I2CWrite(Data[0] ? AV_50_3 : SV_50_3);
break;
case 0x42: //Reserved
I2CWrite(Data[0] ? AV_50_4 : SV_50_4);
break;
case 0x03: //(50Hz) SECAM
I2CWrite(Data[0] ? AV_SECAM : SV_SECAM);
RTDSetBit(VGIP_SIGINV_05,0xff,0x10);
break;
default:
break;
}
}
#endif
2181 1 }
2182
2183 void Display_Video_Set(void)
2184 {
2185 1 #if(VIDEO_CHIP != VDC_NONE)
unsigned char ucCounter;
Load_MUD(ucMode_Curr); // Read mode default settings from 24C04
Set_Video_Mode();
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 37
if (SOURCE_TV == (stGUD1.INPUT_SOURCE & 0x07)) I2CWrite(TV_SOURCE_SEL);
// Read H,V Standard Start Position and H Width
RTDRead(IPH_ACT_STA_06, 0x08, Y_INC);
usIPH_ACT_STA = (unsigned int)Data[0] + ((unsigned int)Data[1] << 8);
usIPH_ACT_STA = usIPH_ACT_STA & 0x07ff;
usIPH_ACT_WID = (unsigned int)Data[2] + ((unsigned int)Data[3] << 8);
usIPH_ACT_WID = usIPH_ACT_WID & 0x07ff;
usIPV_ACT_STA = (unsigned int)Data[4] + ((unsigned int)Data[5] << 8);
usIPV_ACT_STA = usIPV_ACT_STA & 0x07ff;
usIPV_ACT_LEN = (unsigned int)Data[6] + ((unsigned int)Data[7] << 8);
usIPV_ACT_LEN = usIPV_ACT_LEN & 0x07ff;
// Read ucDH_TOTAL
RTDRead(DH_TOTAL_22, 2, Y_INC);
usDH_Total = ((unsigned int)(Data[1] & 0x07) << 8) + Data[0];
// Read ucDV_Delay
RTDRead(IV_DV_LINES_38, 1, N_INC);
ucDV_Delay = Data[0];
ucV_Max_Margin = 0x80;
ucV_Min_Margin = 0x80;
Set_Gamma();
Set_Dithering();
Set_Bright_Contrast();
Sharpness();
// Update VDC's Contrast/Brightness/Hue/Saturation
SetVDC_Color();
ucCounter = 28;
do
{
RTDSetByte(SYNC_POR_4C, 0x00); // Reset Sync Processor
Measure_Mode();
Delay_Xms(80);
RTDRead(SYNC_POR_4C, 0x05, Y_INC);
if (Data[0] & 0x02)
{
usHsync = 0;
usVsync = 0;
}
else
{
Data[5] = Data[3];
Data[4] = Data[4] & 0x87;
Data[3] = Data[1];
Data[2] = Data[2] & 0x8f;
usHsync = ((unsigned int *)Data)[1]; // Current usHsync timing
usVsync = ((unsigned int *)Data)[2]; // Current usVsync timing
if (0x07ff <= usHsync || 0x07ff <= usVsync || 0 == usHsync || 0 == usVsync)
{
usHsync = 0;
usVsync = 0;
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 38
}
else
{
break;
}
}
}
while (--ucCounter);
RTDSetByte(STATUS0_01, 0x00); // Clear status
RTDSetByte(STATUS1_1F, 0x00); // Clear status
Data[0] = Frame_Sync();
if (1 == Data[0]) Data[0] = Frame_Sync(); // Fail. Try again
bFrameSync = Data[0] ? 0 : 1; // 0 : fail, 1 : pass
ucSyncErrorCnt = 0;
// RTDSetBit(VDIS_CTRL_20, 0x5f, DHS_MASK); // Normal display
RTDSetBit(VDIS_CTRL_20, 0x7f, 0x20 | DHS_MASK); // Normal display
#else
2278 1 Set_Video_Mode();
2279 1 #endif
2280 1 }
2281
2282 void Input_Mode_Detector(void)
2283 {
2284 1 RTDRead(SYNC_POR_4C, 0x01, N_INC);
2285 1
2286 1 if (0 == (Data[0] & 0x02)) ucModeCnt = 0;
2287 1
2288 1 if (ucModeCnt)
2289 1 {
2290 2 ucModeCnt -= 1;
2291 2 }
2292 1 else
2293 1 {
2294 2 ucModeCnt = MODE_DETECT_FREQ;
2295 2
2296 2 #if(SOURCE_AUTO_SCAN)
2297 2 Source_Auto_Scan();
2298 2 #else
Mode_Detector();
#endif
2301 2
2302 2 if (!bStable)
2303 2 {
2304 3 bReload = 1; // Reload user's font
2305 3
2306 3 Set_Task(STATE_MODECHANGE); // Notify Task State Machine
2307 3 }
2308 2 }
2309 1 }
2310
2311 ///////////////////////////////////////////////////////////////////////////////////
2312 //anson 05_0314
2313 ///////////////////////////////////////////////////////////////////////////////////
2314 void New_Mode_Auto(void)
2315 {
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 39
2316 1
2317 1 if (bStable &&
2318 1 bFrameSync &&
2319 1 ((stGUD1.OSD_INPUT & 0x20) == 0x20) &&
2320 1 (MODE_NOSIGNAL != ucMode_Curr) &&
2321 1 (MODE_NOSUPPORT != ucMode_Curr) &&
2322 1 ucfrist
2323 1 )
2324 1 {
2325 2 OSD_Position(OSD_ENABLE);
2326 2 OSD_Position(OSD_ENABLE);
2327 2 RTDSetBit(OVL_CTRL_6D, 0xfe, 0x00);
2328 2 RTDOSDW(OSD_Reset);
2329 2 RTDSetBit(OVL_CTRL_6D, 0xfe, 0x01);
2330 2 RTDOSDW(OSD_AUTO);
2331 2 RTDOSDW(strTabAuto_Atb[stGUD1.FUNCTION & 0x07]); //anson
*** WARNING C214 IN LINE 2331 OF CODEMODE_DETECT.C: 'Argument': conversion: non-pointer to pointer
2332 2 Auto_Config();
2333 2 RTDSetBit(OVL_CTRL_6D, 0xfe, 0x00);
2334 2 RTDOSDW(OSD_Reset);
2335 2
2336 2 stGUD1.OSD_INPUT &= 0xdf;//Clear "First Time Into Mode" Bit
2337 2 Save_GUD1();
2338 2 ucfrist = (ucMode_Curr - 1 ) / 8 ;
2339 2 I2CRead(ADDR_EROM1, ucfrist , 1);
2340 2 Data[1] = 0x01;
2341 2 Data[1] = Data[1] << (ucMode_Curr - 1 - (ucfrist*8)) ;
2342 2 Data[3] = Data[0] & ~Data[1];
2343 2
2344 2 Data[0] = 4;
2345 2 Data[1] = ADDR_EROM1;
2346 2 Data[2] = ucfrist;
2347 2 I2CWrite(Data);
2348 2 Delay_Xms(SET_2404_DELAY);
2349 2 ucfrist = 0;
2350 2 }
2351 1
2352 1 }
2353
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 40
ASSEMBLY LISTING OF GENERATED OBJECT CODE
; FUNCTION Com0188 (BEGIN)
0000 L?0393:
0000 L?0394:
0000 7800 R MOV R0,#LOW ucMode_Curr
0002 E6 MOV A,@R0
0003 75F00A MOV B,#0AH
0006 A4 MUL AB
0007 2400 E ADD A,#LOW Mode_Preset+02H
0009 F582 MOV DPL,A
000B E5F0 MOV A,B
000D 3400 E ADDC A,#HIGH Mode_Preset+02H
000F L?0395:
000F F583 MOV DPH,A
0011 L?0396:
0011 E4 CLR A
0012 93 MOVC A,@A+DPTR
0013 FE MOV R6,A
0014 7401 MOV A,#01H
0016 93 MOVC A,@A+DPTR
0017 22 RET
0018 L?0397:
0018 L?0398:
0018 7800 R MOV R0,#LOW usHsync
001A L?0399:
001A A905 MOV R1,AR5
001C AA06 MOV R2,AR6
001E AB07 MOV R3,AR7
0020 L?0400:
0020 E6 MOV A,@R0
0021 L?0401:
0021 FE MOV R6,A
0022 08 INC R0
0023 E6 MOV A,@R0
0024 FF MOV R7,A
0025 E4 CLR A
0026 FC MOV R4,A
0027 FD MOV R5,A
0028 22 RET
0029 L?0402:
0029 75F00C MOV B,#0CH
002C EE MOV A,R6
002D A4 MUL AB
002E 2400 E ADD A,#LOW VGA_Mode+04H
0030 F582 MOV DPL,A
0032 E5F0 MOV A,B
0034 3400 E ADDC A,#HIGH VGA_Mode+04H
0036 F583 MOV DPH,A
0038 7800 R MOV R0,#LOW usVsync
003A L?0403:
003A E6 MOV A,@R0
003B FC MOV R4,A
003C 08 INC R0
003D D3 SETB C
003E L?0404:
003E E6 MOV A,@R0
003F FD MOV R5,A
0040 L?0405:
0040 7401 MOV A,#01H
0042 93 MOVC A,@A+DPTR
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 41
0043 9D SUBB A,R5
0044 E4 CLR A
0045 93 MOVC A,@A+DPTR
0046 9C SUBB A,R4
0047 22 RET
0048 L?0406:
0048 EF MOV A,R7
0049 2B ADD A,R3
004A FF MOV R7,A
004B EE MOV A,R6
004C 3A ADDC A,R2
004D FE MOV R6,A
004E ED MOV A,R5
004F 39 ADDC A,R1
0050 FD MOV R5,A
0051 EC MOV A,R4
0052 38 ADDC A,R0
0053 FC MOV R4,A
0054 7806 MOV R0,#06H
0056 120000 E LCALL ?C?LSHL
0059 L?0407:
0059 8F00 E MOV Data+0FH,R7
005B 8E00 E MOV Data+0EH,R6
005D 8D00 E MOV Data+0DH,R5
005F 8C00 E MOV Data+0CH,R4
0061 22 RET
0062 L?0408:
0062 F9 MOV R1,A
0063 F8 MOV R0,A
0064 L?0409:
0064 120000 E LCALL ?C?LMUL
0067 L?0410:
0067 A804 MOV R0,AR4
0069 L?0411:
0069 A905 MOV R1,AR5
006B AA06 MOV R2,AR6
006D AB07 MOV R3,AR7
006F 22 RET
0070 L?0412:
0070 L?0413:
0070 E4 CLR A
0071 FC MOV R4,A
0072 FD MOV R5,A
0073 L?0414:
0073 7B64 MOV R3,#064H
0075 FA MOV R2,A
0076 F9 MOV R1,A
0077 F8 MOV R0,A
0078 020000 E LJMP ?C?LMUL
007B L?0415:
007B L?0416:
007B 75F00A MOV B,#0AH
007E E500 R MOV A,Wait_Time_Cnt
0080 L?0417:
0080 A4 MUL AB
0081 2400 E ADD A,#LOW Mode_Preset+04H
0083 F582 MOV DPL,A
0085 E5F0 MOV A,B
0087 3400 E ADDC A,#HIGH Mode_Preset+04H
0089 22 RET
008A L?0418:
008A 120000 E LCALL ?C?LMUL
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 42
008D 8F00 E MOV Data+03H,R7
008F 8E00 E MOV Data+02H,R6
0091 8D00 E MOV Data+01H,R5
0093 8C00 E MOV Data,R4
0095 AB00 E MOV R3,Data+03H
0097 AA00 E MOV R2,Data+02H
0099 A900 E MOV R1,Data+01H
009B A800 E MOV R0,Data
009D E4 CLR A
009E FF MOV R7,A
009F FE MOV R6,A
00A0 7DEE MOV R5,#0EEH
00A2 7C02 MOV R4,#02H
00A4 120000 E LCALL ?C?ULDIV
00A7 7800 R MOV R0,#LOW ucRefresh
00A9 EF MOV A,R7
00AA F6 MOV @R0,A
00AB 22 RET
00AC L?0419:
00AC E500 R MOV A,Wait_Time_Cnt
00AE L?0420:
00AE 75F00A MOV B,#0AH
00B1 L?0421:
00B1 A4 MUL AB
00B2 2400 E ADD A,#LOW CAP_WIN+08H
00B4 F582 MOV DPL,A
00B6 E5F0 MOV A,B
00B8 3400 E ADDC A,#HIGH CAP_WIN+08H
00BA 22 RET
00BB L?0422:
00BB 7800 E MOV R0,#LOW usIPV_ACT_LEN
00BD L?0423:
00BD E6 MOV A,@R0
00BE FE MOV R6,A
00BF 08 INC R0
00C0 E6 MOV A,@R0
00C1 L?0424:
00C1 FB MOV R3,A
00C2 AA06 MOV R2,AR6
00C4 E4 CLR A
00C5 F9 MOV R1,A
00C6 F8 MOV R0,A
00C7 22 RET
00C8 L?0425:
00C8 L?0426:
00C8 7800 R MOV R0,#LOW usVsync+01H
00CA E6 MOV A,@R0
00CB 24FF ADD A,#0FFH
00CD FF MOV R7,A
00CE 18 DEC R0
00CF E6 MOV A,@R0
00D0 34FF ADDC A,#0FFH
00D2 22 RET
00D3 L?0427:
00D3 120000 E LCALL ?C?ULDIV
00D6 8E00 R MOV usDispLen,R6
00D8 8F00 R MOV usDispLen+01H,R7
00DA E500 R MOV A,usDispLen
00DC C3 CLR C
00DD 13 RRC A
00DE FE MOV R6,A
00DF E500 R MOV A,usDispLen+01H
C51 COMPILER V7.06 MODE_DETECT 11/21/2005 13:47:38 PAGE 43
00E1 13 RRC A
00E2 FF MOV R7,A
00E3 7C00 MOV R4,#00H
00E5 E500 R MOV A,usDispLen+01H
00E7 5401 ANL A,#01H
00E9 2F ADD A,R7
00EA F500 R MOV usDispLen+01H,A
00EC EC MOV A,R4
00ED 3E ADDC A,R6
00EE F500 R MOV usDispLen,A
00F0 22 RET
00F1 L?0428:
00F1 850000 E MOV Data+07H,Data+05H
00F4 53000F E ANL Data+06H,#0FH
00F7 L?0429:
00F7 850000 E MOV Data+05H,Data+03H
00FA 530087 E ANL Data+04H,#087H
00FD 850000 E MOV Data+03H,Data+01H
0100 53008F E ANL Data+02H,#08FH
0103 22 RET
0104 L?0430:
0104 7800 E MOV R0,#LOW ucV_Max_Margin
0106 A607 MOV @R0,AR7
0108 7800 E MOV R0,#LOW ucV_Min_Margin
010A E6 MOV A,@R0
010B FF MOV R7,A
010C 7800 E MOV R0,#LOW ucDV_Delay
010E E6 MOV A,@R0
010F FD MOV R5,A
0110 FB MOV R3,A
0111 7A00 MOV R2,#00H
0113 2F ADD A,R7
0114 FF MOV R7,A
0115 E4 CLR A
0116 33 RLC A
0117 FE MOV R6,A
0118 D3 SETB C
0119 7480 MOV A,#080H
011B 9F SUBB A,R7
011C E4 CLR A
011D 9E SUBB A,R6
011E 22 RET
011F L?0432:
011F L?0433:
011F F583 MOV DPH,A
0121 E4 CLR A
0122 93 MOVC A,@A+DPTR
0123 FC MOV R4,A
0124 7401 MOV A,#01H
0126 93 MOVC A,@A+DPTR
0127 22 RET
0128 L?0434: