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Disp_B5.h
资源名称：RTD2523_MTV512.rar　[点击查看]
上传用户：xmyjxjd
上传日期：2013-05-04
资源大小：1517k
文件大小：27k
源码类别：

其他嵌入式/单片机内容

开发平台：

C/C++

Disp_B5.h：源码内容
  2. ///////////////////////////////////////////////////////////////////
  3. // Definitions for Display Port
  4. #define SINGLE_PORT         0x00    // Single port (Single pixel output)
  5. #define DOUBLE_PORT         0x04    // Double port (Double pixel output)
  7. #define DISPLAY_PORT        DOUBLE_PORT
  9. ///////////////////////////////////////////////////////////////////
  10. // Definitions for Display Color
  11. #define DISP_18BIT          0x10    // 18-bit RGB output
  12. #define DISP_24BIT          0x00    // 24-bit RGB output 
  14. #define DISP_BIT            DISP_24BIT
  16. ///////////////////////////////////////////////////////////////////
  17. // Definitions for Display Timing Feature
  18. #define MASK_FIRST_DHS      0x80    // Mask 1st DHS
  19. #define NO_MASKING          0x00    // No masking 
  21. #define DHS_MASK            NO_MASKING    
  23. ///////////////////////////////////////////////////////////////////
  24. // Definitions for Display Signal
  25. #define DISP_INV            0x0C    // DVS : neg , DHS : neg , DEN : pos
  26. #define DCLK_INV            0x08    // DCLK : pos
  27. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  29. ///////////////////////////////////////////////////////////////////
  30. // Definitions for Display Settings
  32. #define MAX_DCLK            138     // Maximum display clock(MHz) that panel can support
  33. #define MAX_RATE            76      // Maximum display refresh rate in Hz that panel can support
  35. #define DH_ACT_STA_POS      0x0020  // DH_ACT_STA_POS should be as small as possible !!!
  36. #define DH_ACT_END_POS      0x0520
  38. #define DV_ACT_STA_POS      0x000c  // DV_ACT_STA_POS should be as small as possible !!!
  39. #define DV_ACT_END_POS      0x040c
  41. #define DISP_WID            (DH_ACT_END_POS - DH_ACT_STA_POS)   // 0x0500 = 1280 pixels
  42. #define DISP_LEN            (DV_ACT_END_POS - DV_ACT_STA_POS)   // 0x0400 = 1024 lines
  44. #define STD_DH_TOTAL        0x0580  // Standard display clock number in one display horizontal line
  45. #define STD_DV_TOTAL        0x0480  // Standard display horizontal line in one display frame
  46. #define STD_HSYNC_WIDTH     0x10    // Display HSYNC clock width
  47. #define STD_VSYNC_LENGTH    0x03    // Display VSYNC line length
  49. #define MIN_DV_TOTAL        0x0410  // Minimum VSYNC that panel can support
  52. #define FIX_LAST_DHT        0//0x1f4
  54. #define MIN_LAST_DHT        0       // Must set to 0 if you don't care last-line length
  55. #define MAX_LAST_DHT        0       // Set it to 0 if you don't care the maximum last-line length
  56. #define VIDEO_ML_DHT        0       // Minimum last-line length for video
  59. #define USER_MODE_NCODE     16      // NEVER change this setting !!!
  61. #define DISP_ALIGN          0       // 0-Left alignment, 1-Right alignment
  64. #define AUTO_SWITCH        0x60      // Auto Switch to freerun mode
  66. #define DISP_EO_SWAP       0x00//0x80      // Display Even/Odd Data Swap
  67. #define DISP_RB_SWAP       0x00//0x40      // Display Red/Blue Data Swap
  68. #define DISP_ML_SWAP       0x00//0x20      // Display MSB/LSB Data Swap
  71. /*
  72. ///////////////////////////////////////////////////////////////////
  73. // Definitions for RTD3001
  74. #define All_LINE_BUF        0x02    // Turn on all line buffers
  75. #define REQ_DELAY           0x40    // 0.5ns delay for request
  76. #define V_MAC_DELAY         0x10    // 0.5ns delay for Vertical MAC
  77. #define H_MAC_DELAY         0x04    // 0.5ns delay for Horizontal MAC
  78. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  80. #define HINIT_COEFF         0x00    // Horizontal initial coefficient = 0xc000
  81. #define REQMODE_00B         0x00    // Imporved mode 1 : REG[28]-bit3 = 0
  82. #define REQMODE_01B         0x80    // Imporved mode 1 : REG[31]-bit7 = 1
  83. #define ODDCTRL_VGA         0x38    // REG[31]-bit5  : Odd signal for V inital toggle. (0 : inverse)
  84.                                     // REG[31]-bit4  : Odd signal to control FS_DELAY_FINE_TUNING. (0 : enable)
  85.                                     // REG[31]-bit3  : Odd signal to enable FS_DELAY_FINE_TUNING. (1 : inverse)
  86. #define ODDCTRL_VIDEO       0x28
  87. */
  89. //---------------------------------- 1280x1024 ---------------------------------
  90. ///////////////////////////////////////////////////////////////////////////
  91. #ifdef __MAIN__
  93. unsigned char code RTD_PWUP_INI[]   =
  94. { 
  95.     5,      Y_INC,  HOSTCTRL_02,        0x42,0x00,
  97.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  98.     8,      N_INC,  TC_DATA_PORT_96,    0x42,0x10,0x11,0x80,0xf8, //anson  MTV 512
  99. //    8,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,0xfc, //anson  TP2804
  100.     9,      Y_INC,  GP1_ODOCTRL_F6,     0x00,0x00,0x00,0x00,0x00,0x00,
  102.     6,      Y_INC,  IRQ_CTRL1_0E,       0x00,0x80,0x00,
  104.     4,      N_INC,  INT_FLD_DETECT_14,  0x00,
  106.     25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
  107. 0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
  109.     6,      Y_INC,  YUV2RGB_39,         0x00,0x00,0x00,
  110.     
  111.     5,      Y_INC,  DUTY_FINE_TUNE_3E,  0xc0,0x0e,          // For improving display speed
  112.     
  113.     4,      N_INC,  MEAS_HS_LATCH_4E,   0x00,
  115.     5,      Y_INC,  CLAMP_55,           0x04,0x10,
  117.     4,      N_INC,  COLOR_CTRL_5D,      0x03,
  119.     4,      N_INC,  OP_CRC_CTRL_68,     0x88,               // For improving display speed
  121.     6,      Y_INC,  PATTERN_GEN_6C,     0x00,0x83,0x00,
  123.     4,      N_INC,  SD_CTRL_70,         0x00,
  125. 4,      N_INC,  FX_LST_LEN_H_5A,     0x00,              // Disable fix last line function
  127.     6,      Y_INC,  IVS_DELAY_8C,       0x00,0x00,0x00,
  129.     7,      Y_INC,  PLL_DIV_CTRL0_C8,   0x04,0x00,0x20,0x18,
  132.     4,      N_INC,  HS_SCHMITT_TRIG_ED, 0xe3,                       //Set the Schmitt Trigger threshold voltage from 1.0 ~ 1.6V
  133.     4,      N_INC,  SPREAD_SPECTRUM_99, 0x00,                       //Disable Spread Spectrum
  134.     7,      Y_INC,  DPLL_CTRL_D0,       0x28,0x37,0x35,0x04,        //DCLK = 100MHz
  136.     13,     Y_INC,  PLL1_CTRL_D6,       0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
  138.     //4,      N_INC,  ADC_CTRL_E6,        0xb0,
  139.     4,      N_INC,  ADC_CTRL_E6,        0x40,
  141.     4,      N_INC,  DV_BKGD_STA_31,     0x60,
  143.     4,      N_INC,  ADC_FRAME_MODULE_EB, 0x06,
  145.     4,      N_INC,  TMDS_CORRECTION_FF, 0x00,
  147.     9,      Y_INC,  TMDS_OUTPUT_ENA_A0, 0x0f, 0xef,0x8b,0x26,0x35,0x2f,
  150.     0
  151. };
  153. unsigned char code RTD_DDC_TABLE[]  =
  154. {
  155.     5,      Y_INC,  DDC_ENABLE_FC,      0x00,0x00,  // Disable the DDC channel of VGA
  157.     131,    N_INC,  DDC_ACCESS_P_FE,    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  158.                                         0x4a,0x8b,0x00,0x00,0x01,0x01,0x01,0x01,
  159.                                         0x1e,0x0c,0x01,0x01,0x0e,0x24,0x1b,0x78,
  160.                                         0xe8,0x8a,0x01,0x9a,0x58,0x52,0x8b,0x28,
  161.                                         0x1e,0x50,0x54,0xff,0xff,0x80,0x61,0x40,
  162.                                         0x61,0x4f,0x61,0x59,0x71,0x4f,0x81,0x40,
  163.                                         0x81,0x59,0x81,0x99,0xa9,0x40,0x00,0x00,
  164.                                         0x00,0xfc,0x00,0x31,0x37,0x27,0x27,0x20,
  165.                                         0x4c,0x43,0x44,0x0a,0x20,0x20,0x20,0x20,
  166.                                         0x00,0x00,0x00,0xfc,0x00,0x4d,0x6f,0x6e,
  167.                                         0x69,0x74,0x6f,0x72,0x0a,0x20,0x20,0x20,
  168.                                         0x20,0x20,0x00,0x00,0x00,0xfd,0x00,0x2b,
  169.                                         0x55,0x14,0x5c,0x0e,0x00,0x0a,0x20,0x20,
  170.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xff,
  171.                                         0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0a,
  172.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xbd,
  174.     4,  N_INC,  DDC_ENABLE_FC,          0x05,       // Enable the DDC channel of VGA
  175.     
  176. #if(TMDS_ENABLE)
  177.     5,      Y_INC,  DDC_ENABLE_BC,      0x00,0x00,  // Disable the DDC channel  of DVI
  179.     131,    N_INC,  DDC_ACCESS_PORT_BE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  180.                                         0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
  181.                                         0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,
  182.                                         0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,                                        
  183.                                         0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,
  184.                                         0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
  185.                                         0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,
  186.                                         0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
  188.                                         0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,
  189.                                         0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
  190.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  191.                                         0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
  192.                                         0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,
  193.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
  194.                                         0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,
  195.    0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
  197.     4,  N_INC,  DDC_ENABLE_BC,          0x05,       // Enable the DDC channel of DVI
  198. #endif
  200.     0
  201. };
  203. unsigned char code RTD_IO_INI[]  =
  204. {
  205.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  207. #if(OUTPUT_BUS == LVDS_TYPE)
  209. #if(BOARD_TYPE == DEMO1_PCB)
  210.     8,      N_INC,  TC_DATA_PORT_96,    0x42,0x10,0x11,0x80,0xfc, //anson  MTV 512
  211. //    8,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,0xfc, //anson  TP2804
  212. #else
  213.     7,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,
  214. #endif
  215. //    7,      N_INC,  TC_DATA_PORT_96,    0x40,0x10,0x11,0x08,
  216. #endif
  219. #if(OUTPUT_BUS == LVDS_TYPE)
  221. #if(LVDS_MAP1 == LVDS_MAP)
  222.    9,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x22,0x80,0x80,0x68,
  223. #else
  224.    9,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x23,0x80,0x80,0x68,
  225. #endif
  227. #endif
  230.     0
  231. };
  233. // Be Careful !!
  234. // Display window setting in FreeV[] MUST follow the definition of
  235. // 1. DISP_WID and DISP_LEN
  236. // 2. DH_ACT_STA_POS and DH_ACT_END_POS
  237. // 3. DV_ACT_STA_POS and DV_ACT_END_POS
  238. // 4. Background window must be the same as active window.
  240. unsigned char code FreeV[]  =
  241. {
  243.     27, Y_INC,  VDIS_CTRL_20,       0x20 | DISP_BIT | DISPLAY_PORT,                 // Disable display timing
  245.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  246.                                     (STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8),     // DH_TOTAL
  247.                                     STD_HSYNC_WIDTH,                                // DH_HS_END
  248.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
  249.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
  250.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
  251.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
  252.                                     (STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8),     // DV_TOTAL
  253.                                     STD_VSYNC_LENGTH,                               // DV_VS_END
  254.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
  255.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
  256.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
  257.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
  259.     4,  N_INC,  VDIS_CTRL_20,       0x23 | DISP_BIT | DISPLAY_PORT,                 // Enable free-run background
  261.     // Force display timing start
  262.     6,  Y_INC,  YUV2RGB_39,         0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
  263.     4,  N_INC,  DIS_TIMING0_3A,     0x00 | DCLK_DELAY,
  265.     4,  N_INC,  INT_FLD_DETECT_14,  0x00,
  266.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  268. 4,  N_INC,  SCALE_CTRL_15,      0x00,
  270.     4,  N_INC,  FILTER_CTRL0_1B,    0xc4,
  273.     0
  274. };
  276. unsigned char code OSD_PWUP_INI[]   =
  277. {
  279.     5,  Y_INC,  OSD_ADDR_MSB_90, 0xc0,0x02,
  280. 6,  N_INC,  OSD_DATA_92,     0x03,0x08,0x00,
  282.     0
  283. };
  286. ///////////////////////////////////////////////////////////////////////////
  287. //VGA mode detect range
  288. unsigned int code VGA_Mode[][6] =
  289. {
  290. //      HF_min, HF_max, VL_min, VL_max, HF_std, VS+1
  291.     {   0,      0,      0,      0,      0,      0       }, //00:No Signal
  293.     {   764,    806,    620,    636,    781,    2+1     }, //01:VGA [640/720]*350*50Hz
  294.     {   764,    806,    620,    636,    781,    2+1     }, //02:VGA [640/720]*400*50Hz
  295.     {   764,    806,    516,    532,    781,    2+1     }, //03:VGA [640/720]*350*60Hz
  296.     {   764,    806,    516,    532,    781,    2+1     }, //04:VGA [640/720]*400*60Hz
  298.     {   969,    1021,   431,    447,    990,    8+1     }, //05:640*400*56hz
  299.     {   768,    810,    440,    456,    785,    2+1     }, //06:640*350*70hz
  300.     {   764,    806,    440,    456,    781,    2+1     }, //07:720*350*70hz
  301.     {   764,    806,    440,    456,    781,    2+1     }, //08:640*400*70hz
  302.     {   764,    806,    440,    456,    781,    2+1     }, //09:700*400*70hz
  303.     {   635,    670,    436,    452,    649,    3+1     }, //10:640*350*85hz
  304.     {   635,    670,    436,    452,    649,    3+1     }, //11:640*400*85hz
  305.     {   634,    669,    437,    453,    648,    3+1     }, //12:720*400*85hz
  306.     {   764,    806,    620,    636,    781,    2+1     }, //13:640*480*50hz
  307.     {   764,    806,    516,    532,    781,    2+1     }, //14:640*480*60hz
  308.     {   687,    724,    516,    532,    702,    3+1     }, //15:640*480*66hz
  309.     {   635,    670,    511,    527,    649,    3+1     }, //16:640*480*72hz
  310.     {   641,    676,    495,    507,    655,    3+1     }, //17:640*480*75hz
  311.     {   556,    586,    500,    516,    568,    3+1     }, //18:640*480*85hz
  312.     {   684,    721,    616,    632,    699,    2+1     }, //19:800*600*56hz
  313.     {   635,    670,    619,    635,    649,    4+1     }, //20:800*600*60hz
  314.     {   492,    519,    721,    737,    503,    6+1     }, //21:800*600*66hz
  315.     {   500,    527,    657,    673,    511,    6+1     }, //22:800*600*72hz
  316.     {   513,    541,    616,    632,    524,    3+1     }, //23:800*600*75hz
  317.     {   448,    473,    622,    638,    458,    3+1     }, //24:800*600*85hz
  318.     {   483,    510,    658,    674,    494,    3+1     }, //25:832*624*75hz
  319.     {   497,    524,    797,    813,    508,    6+1     }, //26:1024*768*60hz
  320.     {   493,    520,    810,    826,    504,    6+1     }, //27:1024*768*59hz
  321.     {   445,    470,    807,    823,    455,    4+1     }, //28:1024*768*66hz
  322.     {   428,    449,    797,    813,    435,    6+1     }, //29:1024*768*70hz
  323. //      HF_min, HF_max, VL_min, VL_max, HF_std, VS+1
  324.     {   414,    436,    798,    814,    423,    3+1     }, //30:1024*768*72hz //anson 05_0321 add
  325.     {   399,    421,    795,    811,    408,    3+1     }, //31:1024*768*74hz
  326. //      HF_min, HF_max, VL_min, VL_max, HF_std, VS+1
  327.     {   400,    422,    791,    807,    409,    3+1     }, //32:1024*768*75hz
  328.     {   350,    370,    799,    815,    358,    3+1     }, //33:1024*768*85hz
  329.     {   339,    358,    834,    850,    347,    8+1     }, //34:1024*800*84hz
  330.     {   356,    376,    891,    907,    364,    3+1     }, //35:1152*864*75hz
  331.     {   350,    370,    906,    922,    358,    3+1     }, //36:1152*870*75hz
  332.     {   389,    411,    928,    944,    398,    4+1     }, //37:1152*900*66hz
  333.     {   335,    354,    934,    950,    343,    8+1     }, //38:1152*900*76hz
  334.     {   401,    423,    991,    1007,   410,    3+1     }, //39:1280*960*60hz
  335.     {   280,    295,    1002,   1018,   286,    3+1     }, //40:1280*960*85hz
  336.     {   376,    396,    1057,   1073,   384,    3+1     }, //41:1280*1024*60hz
  337.     {   312,    329,    1060,   1076,   319,    3+1     }, //42:1280*1024*72hz
  338.     {   296,    313,    1057,   1073,   303,    8+1     }, //43:1280*1024*76hz
  339.     {   300,    317,    1057,   1073,   307,    3+1     }, //44:1280*1024*75hz
  340.     {   264,    279,    1063,   1079,   270,    3+1     }, //45:1280*1024*85hz
  341.     {   321,    339,    1241,   1257,   328,    3+1     }, //46:1600*1200*60hz
  343.     {   0,      0,      0,      0,      0,      0       }, //47:Mode reserved 00
  344.     {   0,      0,      0,      0,      0,      0       }, //48:Mode reserved 01
  345.     {   0,      0,      0,      0,      0,      0       }, //49:Mode reserved 02
  346.     {   0,      0,      0,      0,      0,      0       }, //50:Mode reserved 03
  348.     {   642,    1230,   418,    497,    0,      2+1     }, //51:NewMode720x400
  349.     {   535,    1025,   498,    637,    0,      2+1     }, //52:NewMode640x480
  350.     {   428,    820,    618,    785,    0,      2+1     }, //53:NewMode800x600
  351.     {   334,    641,    786,    881,    0,      2+1     }, //54:NewMode1024x768
  352.     {   297,    570,    882,    917,    0,      2+1     }, //55:NewMode1152x864
  353.     {   285,    547,    918,    977,    0,      2+1     }, //56:NewMode1152x900
  354.     {   267,    513,    978,    1041,   0,      2+1     }, //57:NewMode1280x960
  355.     {   251,    481,    1042,   1217,   0,      2+1     }, //58:NewMode1280x1024
  356.     {   292,    559,    1218,   1328,   0,      2+1     }, //59:NewMode1600x1200
  357. };
  359. unsigned int code Mode_Preset[][5]   =
  360. {
  361.     //  DH_TOTAL    DH_ACT_WID  DV_ACT_LEN      DCLK_M/N    IVS_DELAY
  362.     {   1408,       1280,       1024,           0,          0       }, //00:No Signal
  364.     //  VGA confused mode
  365.     {   1408,       1280,       1024,           0,          63      }, //01:VGA [640/720]*350*50Hz
  366.     {   1408,       1280,       1024,           0,          31      }, //02:VGA [640/720]*400*50Hz
  367.     {   1408,       1280,       1024,           0,          63      }, //03:VGA [640/720]*350*60Hz
  368.     {   1408,       1280,       1024,           0,          31      }, //04:VGA [640/720]*400*60Hz
  370.     //  Standard mode
  371.     {   1568,       1280,       1024,           0,          7       }, //05:640*400*56hz
  372.     {   1408,       1280,       1024,           0,          7       }, //06:640*350*70hz
  373.     {   1408,       1280,       1024,           0,          7       }, //07:720*350*70hz
  374.     {   1408,       1280,       1024,           0,          7       }, //08:640*400*70hz
  375.     {   1408,       1280,       1024,           0,          7       }, //09:700*400*70hz
  376.     {   1408,       1280,        896,            0,          7       }, //10:640*350*85hz
  377.     {   1408,       1280,       1024,           0,          7       }, //11:640*400*85hz
  378.     {   1376,       1280,       1024,           0,          7       }, //12:720*400*85hz
  379.     {   1408,       1280,       1024,           0,          31      }, //13:640*480*50hz
  380.     {   1408,       1280,       1024,           0,          7       }, //14:640*480*60hz
  381.     {   1504,       1280,       1024,           0,          7       }, //15:640*480*66hz
  382.     {   1456,       1280,       1024,           0,          7       }, //16:640*480*72hz
  383.     {   1472,       1280,       1024,           0,          3       }, //17:640*480*75hz
  384.     {   1408,       1280,       1024,           0,          7       }, //18:640*480*85hz
  385.     {   1632,       1280,       1024,           0,          3       }, //19:800*600*56hz
  386.     {   1640,       1280,       1024,           0,          7       }, //20:800*600*60hz
  387.     {   1408,       1280,       1024,           0,          7       }, //21:800*600*66hz
  388.     {   1408,       1280,       1024,           0,          7       }, //22:800*600*72hz
  389.     {   1408,       1280,       1024,           0,          3       }, //23:800*600*75hz
  390.     {   1408,       1280,       1024,           0,          7       }, //24:800*600*85hz
  391.     {   1568,       1280,       1024,           0,          7       }, //25:832*624*75hz
  392.     {   1408,       1280,       1024,           0,          7       }, //26:1024*768*60hz
  393.     {   1408,       1280,       1024,           0,          7       }, //27:1024*768*59hz
  394.     {   1408,       1280,       1024,           0,          7       }, //28:1024*768*66hz
  395.     {   1632,       1280,       1024,           0,          7       }, //29:1024*768*70hz
  396.     //  DH_TOTAL    DH_ACT_WID  DV_ACT_LEN      DCLK_M/N    IVS_DELAY
  397.     {   1408,       1280,       1024,           0,          7       }, //30:1024*768*72hz //anson 05_0321 add
  398.     {   1408,       1280,       1024,           0,          7       }, //31:1024*768*74hz
  399.     //  DH_TOTAL    DH_ACT_WID  DV_ACT_LEN      DCLK_M/N    IVS_DELAY
  400.     {   1408,       1280,       1024,           0,          7       }, //32:1024*768*75hz
  401.     {   1408,       1280,       1024,           0,          7       }, //33:1024*768*85hz
  402.     {   1408,       1280,       1024,           0,          7       }, //34:1024*800*84hz
  403.     {   1408,       1280,       1024,           0,          7       }, //35:1152*864*75hz
  404.     {   1408,       1280,       1024,           0,          7       }, //36:1152*870*75hz
  405.     {   1408,       1280,       1024,           0,          7       }, //37:1152*900*66hz
  406.     {   1408,       1280,       1024,           0,          7       }, //38:1152*900*76hz
  407.     {   1408,       1280,       1024,           0,          7       }, //39:1280*960*60hz
  408.     {   1408,       1280,       1024,           0,          7       }, //40:1280*960*85hz
  409.     {   1408,       1280,       1024,           0,          7       }, //41:1280*1024*60hz
  410.     {   1408,       1280,       1024,           0,          7       }, //42:1280*1024*72hz
  411.     {   1408,       1280,       1024,           0,          7       }, //43:1280*1024*76hz
  412.     {   1408,       1280,       1024,           0,          7       }, //44:1280*1024*75hz
  413.     {   1408,       1280,       1024,           0,          7       }, //45:1280*1024*85hz
  414.     {   1408,       1280,       1024,           0,          7       }, //46:1600*1200*60hz
  416.     //  Reserved mode
  417.     {   1408,       1280,       1024,           0,          0       }, //47:Mode reserved 00
  418.     {   1408,       1280,       1024,           0,          0       }, //48:Mode reserved 01
  419.     {   1408,       1280,       1024,           0,          0       }, //49:Mode reserved 02
  420.     {   1408,       1280,       1024,           0,          0       }, //50:Mode reserved 03
  422.     //  Unknown user mode
  423.     {   1408,       1280,       1024,           0,          3       }, //51:NewMode720x400
  424.     {   1408,       1280,       1024,           0,          3       }, //52:NewMode640x480
  425.     {   1408,       1280,       1024,           0,          3       }, //53:NewMode800x600
  426.     {   1408,       1280,       1024,           0,          3       }, //54:NewMode1024x768
  427.     {   1408,       1280,       1024,           0,          3       }, //55:NewMode1152x864
  428.     {   1408,       1280,       1024,           0,          3       }, //56:NewMode1152x900
  429.     {   1408,       1280,       1024,           0,          3       }, //57:NewMode1280x960
  430.     {   1408,       1280,       1024,           0,          3       }, //58:NewMode1280x1024
  431.     {   1408,       1280,       1024,           0,          3       }, //59:NewMode1600x1200
  432.     
  433.     //  Safe display mode
  434.     {   1408,       1280,       1024,           0,          3       }, //60:Undefined SU mode
  435.     {   1408,       1280,       1024,           0,          3       }, //61:Undefined SD mode
  436. };
  438. ///////////////////////////////////////////////////////////////////////////////
  439. //Video Setting
  440. #if (VIDEO_CHIP == VDC_NONE)
  441. // No Video Decoder
  442. unsigned char code RTD_VIDEO_60[]   = { 0 };
  443. unsigned char code RTD_VIDEO_50[]   = { 0 };
  445. #else
  447. #if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 || VIDEO_CHIP == VDC_SAA7118)
  449. #define H_60    0x91//0x70    // For SAA7114/7118
  450. #define H_50    0x97//0x7c    // For SAA7114/7118
  452. #else
  454. #define H_60    0x56    // For SAA7111A
  455. #define H_50    0x5e    // For SAA7111A
  457. #endif
  459. unsigned char code RTD_VIDEO_60[]   =
  460. {
  461.     11, Y_INC,  IPH_ACT_STA_06,     H_60, 0x00, 0xb8, 0x02,
  462.                                     0x14, 0x00, 0xed, 0x00,
  464.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x40, 0x3b, 0x00,
  466.     4,  N_INC,  FS_FT_DELAY_1E,     0x0f,//0x1a,
  467.     
  468.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0xed, 0x00,
  470.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  472.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  474.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  476.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  478.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  479.  
  480.                                     0x7e, 0x05,
  481.                                     0x10,
  482.                                     0x20, 0x00,
  483.                                     0x20, 0x00,
  484.                                     0x20, 0x05,
  485.                                     0x20, 0x05,
  486.                                     0x80, 0x04,
  487.                                     0x03,
  488.                                     0x0f, 0x00,
  489.                                     0x0f, 0x00,
  490.                                     0x0f, 0x04,
  491.                                     0x0f, 0x04,
  492.                                     0x13, 0x20,
  494. 7,  Y_INC,  DPLL_CTRL_D0,       0x18, 0x62, 0x3a,0x07,
  496. 5,  Y_INC, DCLK_OFFSET_LSB_9A,  0x70, 0x29,
  498. 4,  N_INC, FX_LST_LEN_H_5A,     0x08,
  500.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  502.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  504.     0
  505. };
  507. unsigned char code RTD_VIDEO_50[]=
  508. {
  509.     11, Y_INC,  IPH_ACT_STA_06,     H_50, 0x00, 0xb8, 0x02,
  510.                                     0x18, 0x00, 0x1a, 0x01,
  512.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x80, 0x46, 0x00,
  514.     4,  N_INC,  FS_FT_DELAY_1E,     0x13,
  515.     
  516.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0x1a, 0x01,
  518.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  520.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  522.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  526. //  6,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x75, 0x07,
  528.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  529.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  530.                                     0x7e, 0x05,
  531.                                     0x10,
  532.                                     0x20, 0x00,
  533.                                     0x20, 0x00,
  534.                                     0x20, 0x05,
  535.                                     0x20, 0x05,
  536.                                     0x80, 0x04,
  537.                                     0x03,
  538.                                     0x0d, 0x00,
  539.                                     0x0d, 0x00,
  540.                                     0x0d, 0x04,
  541.                                     0x0d, 0x04,
  542.                                     0x17, 0x20,
  544. 7,  Y_INC,  DPLL_CTRL_D0,       0x10, 0x52, 0x3a,0x07,
  546. 5,  Y_INC, DCLK_OFFSET_LSB_9A,  0xc2, 0x29,
  548. 4,  N_INC, FX_LST_LEN_H_5A,     0x08,
  551.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  553.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  555.     0
  556. };
  558. #endif
  560. #else 
  562. extern unsigned char code RTD_PWUP_INI[];
  563. extern unsigned char code RTD_DDC_TABLE[];
  564. extern unsigned char code RTD_IO_INI[];
  566. extern unsigned char code FreeV[];
  567. extern unsigned char code OSD_PWUP_INI[];
  569. extern unsigned int code VGA_Mode[][6];
  570. extern unsigned int code Mode_Preset[][5];
  572. extern unsigned char code RTD_VIDEO_60[];
  573. extern unsigned char code RTD_VIDEO_50[];
  575. #endif