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Disp_B3.h
资源名称：RTD2523_MTV512.rar　[点击查看]
上传用户：xmyjxjd
上传日期：2013-05-04
资源大小：1517k
文件大小：27k
源码类别：

其他嵌入式/单片机内容

开发平台：

C/C++

Disp_B3.h：源码内容
  2. ///////////////////////////////////////////////////////////////////
  3. // Definitions for Display Port
  4. #define SINGLE_PORT         0x00    // Single port (Single pixel output)
  5. #define DOUBLE_PORT         0x04    // Double port (Double pixel output)
  7. #define DISPLAY_PORT        DOUBLE_PORT
  9. ///////////////////////////////////////////////////////////////////
  10. // Definitions for Display Color
  11. #define DISP_18BIT          0x10    // 18-bit RGB output
  12. #define DISP_24BIT          0x00    // 24-bit RGB output 
  14. #define DISP_BIT            DISP_24BIT
  16. ///////////////////////////////////////////////////////////////////
  17. // Definitions for Display Timing Feature
  18. #define MASK_FIRST_DHS      0x80    // Mask 1st DHS
  19. #define NO_MASKING          0x00    // No masking 
  21. #define DHS_MASK            NO_MASKING    
  23. ///////////////////////////////////////////////////////////////////
  24. // Definitions for Display Signal
  25. #define DISP_INV            0x0C    // DVS : neg , DHS : neg , DEN : pos
  26. #define DCLK_INV            0x08    // DCLK : pos
  27. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  29. ///////////////////////////////////////////////////////////////////
  30. // Definitions for Display Settings
  32. #define MAX_DCLK            138     // Maximum display clock(MHz) that panel can support
  33. #define MAX_RATE            76      // Maximum display refresh rate in Hz that panel can support
  35. #define DH_ACT_STA_POS      0x0020  // DH_ACT_STA_POS should be as small as possible !!!
  36. #define DH_ACT_END_POS      0x0520
  38. #define DV_ACT_STA_POS      0x000c  // DV_ACT_STA_POS should be as small as possible !!!
  39. #define DV_ACT_END_POS      0x040c
  41. #define DISP_WID            (DH_ACT_END_POS - DH_ACT_STA_POS)   // 0x0500 = 1280 pixels
  42. #define DISP_LEN            (DV_ACT_END_POS - DV_ACT_STA_POS)   // 0x0400 = 1024 lines
  44. #define STD_DH_TOTAL        0x0580  // Standard display clock number in one display horizontal line
  45. #define STD_DV_TOTAL        0x0480  // Standard display horizontal line in one display frame
  46. #define STD_HSYNC_WIDTH     0x10    // Display HSYNC clock width
  47. #define STD_VSYNC_LENGTH    0x03    // Display VSYNC line length
  49. #define MIN_DV_TOTAL        0x0410  // Minimum VSYNC that panel can support
  52. #define FIX_LAST_DHT        0//0x1f4
  54. #define MIN_LAST_DHT        0       // Must set to 0 if you don't care last-line length
  55. #define MAX_LAST_DHT        0       // Set it to 0 if you don't care the maximum last-line length
  56. #define VIDEO_ML_DHT        0       // Minimum last-line length for video
  59. #define USER_MODE_NCODE     16      // NEVER change this setting !!!
  61. #define DISP_ALIGN          0       // 0-Left alignment, 1-Right alignment
  64. #define AUTO_SWITCH        0x60      // Auto Switch to freerun mode
  66. #define DISP_EO_SWAP       0x00//0x80      // Display Even/Odd Data Swap
  67. #define DISP_RB_SWAP       0x00//0x40      // Display Red/Blue Data Swap
  68. #define DISP_ML_SWAP       0x00//0x20      // Display MSB/LSB Data Swap
  71. /*
  72. ///////////////////////////////////////////////////////////////////
  73. // Definitions for RTD3001
  74. #define All_LINE_BUF        0x02    // Turn on all line buffers
  75. #define REQ_DELAY           0x40    // 0.5ns delay for request
  76. #define V_MAC_DELAY         0x10    // 0.5ns delay for Vertical MAC
  77. #define H_MAC_DELAY         0x04    // 0.5ns delay for Horizontal MAC
  78. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  80. #define HINIT_COEFF         0x00    // Horizontal initial coefficient = 0xc000
  81. #define REQMODE_00B         0x00    // Imporved mode 1 : REG[28]-bit3 = 0
  82. #define REQMODE_01B         0x80    // Imporved mode 1 : REG[31]-bit7 = 1
  83. #define ODDCTRL_VGA         0x38    // REG[31]-bit5  : Odd signal for V inital toggle. (0 : inverse)
  84.                                     // REG[31]-bit4  : Odd signal to control FS_DELAY_FINE_TUNING. (0 : enable)
  85.                                     // REG[31]-bit3  : Odd signal to enable FS_DELAY_FINE_TUNING. (1 : inverse)
  86. #define ODDCTRL_VIDEO       0x28
  87. */
  89. //---------------------------------- 1280x1024 ---------------------------------
  90. ///////////////////////////////////////////////////////////////////////////
  91. #ifdef __MAIN__
  93. unsigned char code RTD_PWUP_INI[]   =
  94. { 
  95.     5,      Y_INC,  HOSTCTRL_02,        0x42,0x00,
  97.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  98.     8,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,0xfc,//0x00,0x00,0x00,0x00,
  99.     9,      Y_INC,  GP1_ODOCTRL_F6,     0x00,0x00,0x00,0x00,0x00,0x00,
  101.     6,      Y_INC,  IRQ_CTRL1_0E,       0x00,0x80,0x00,
  103.     4,      N_INC,  INT_FLD_DETECT_14,  0x00,
  105.     25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
  106. 0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
  108.     6,      Y_INC,  YUV2RGB_39,         0x00,0x00,0x00,
  109.     
  110.     5,      Y_INC,  DUTY_FINE_TUNE_3E,  0xc0,0x0e,          // For improving display speed
  111.     
  112.     4,      N_INC,  MEAS_HS_LATCH_4E,   0x00,
  114.     5,      Y_INC,  CLAMP_55,           0x04,0x10,
  116.     4,      N_INC,  COLOR_CTRL_5D,      0x03,
  118.     4,      N_INC,  OP_CRC_CTRL_68,     0x88,               // For improving display speed
  120.     6,      Y_INC,  PATTERN_GEN_6C,     0x00,0x83,0x00,
  122.     4,      N_INC,  SD_CTRL_70,         0x00,
  124. 4,      N_INC,  FX_LST_LEN_H_5A,     0x00,              // Disable fix last line function
  126.     6,      Y_INC,  IVS_DELAY_8C,       0x00,0x00,0x00,
  128.     7,      Y_INC,  PLL_DIV_CTRL0_C8,   0x04,0x00,0x20,0x18,
  131.     4,      N_INC,  HS_SCHMITT_TRIG_ED, 0xe3,                       //Set the Schmitt Trigger threshold voltage from 1.0 ~ 1.6V
  132.     4,      N_INC,  SPREAD_SPECTRUM_99, 0x00,                       //Disable Spread Spectrum
  133.     7,      Y_INC,  DPLL_CTRL_D0,       0x28,0x37,0x35,0x04,        //DCLK = 100MHz
  135.     13,     Y_INC,  PLL1_CTRL_D6,       0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
  137.     //4,      N_INC,  ADC_CTRL_E6,        0xb0,
  138.     4,      N_INC,  ADC_CTRL_E6,        0x40,
  140.     4,      N_INC,  DV_BKGD_STA_31,     0x60,
  142.     4,      N_INC,  ADC_FRAME_MODULE_EB, 0x06,
  144.     4,      N_INC,  TMDS_CORRECTION_FF, 0x00,
  146.     9,      Y_INC,  TMDS_OUTPUT_ENA_A0, 0x0f, 0xef,0x8b,0x26,0x35,0x2f,
  149.     0
  150. };
  152. unsigned char code RTD_DDC_TABLE[]  =
  153. {
  154.     5,      Y_INC,  DDC_ENABLE_FC,      0x00,0x00,  // Disable the DDC channel of VGA
  156.     131,    N_INC,  DDC_ACCESS_P_FE,    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  157.                                         0x4a,0x8b,0x00,0x00,0x01,0x01,0x01,0x01,
  158.                                         0x1e,0x0c,0x01,0x01,0x0e,0x24,0x1b,0x78,
  159.                                         0xe8,0x8a,0x01,0x9a,0x58,0x52,0x8b,0x28,
  160.                                         0x1e,0x50,0x54,0xff,0xff,0x80,0x61,0x40,
  161.                                         0x61,0x4f,0x61,0x59,0x71,0x4f,0x81,0x40,
  162.                                         0x81,0x59,0x81,0x99,0xa9,0x40,0x00,0x00,
  163.                                         0x00,0xfc,0x00,0x31,0x37,0x27,0x27,0x20,
  164.                                         0x4c,0x43,0x44,0x0a,0x20,0x20,0x20,0x20,
  165.                                         0x00,0x00,0x00,0xfc,0x00,0x4d,0x6f,0x6e,
  166.                                         0x69,0x74,0x6f,0x72,0x0a,0x20,0x20,0x20,
  167.                                         0x20,0x20,0x00,0x00,0x00,0xfd,0x00,0x2b,
  168.                                         0x55,0x14,0x5c,0x0e,0x00,0x0a,0x20,0x20,
  169.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xff,
  170.                                         0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0a,
  171.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xbd,
  173.     4,  N_INC,  DDC_ENABLE_FC,          0x05,       // Enable the DDC channel of VGA
  174.     
  175. #if(TMDS_ENABLE)
  176.     5,      Y_INC,  DDC_ENABLE_BC,      0x00,0x00,  // Disable the DDC channel  of DVI
  178.     131,    N_INC,  DDC_ACCESS_PORT_BE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  179.                                         0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
  180.                                         0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,
  181.                                         0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,                                        
  182.                                         0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,
  183.                                         0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
  184.                                         0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,
  185.                                         0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
  187.                                         0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,
  188.                                         0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
  189.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  190.                                         0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
  191.                                         0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,
  192.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
  193.                                         0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,
  194.    0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
  196.     4,  N_INC,  DDC_ENABLE_BC,          0x05,       // Enable the DDC channel of DVI
  197. #endif
  199.     0
  200. };
  202. unsigned char code RTD_IO_INI[]  =
  203. {
  204.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  206. #if(OUTPUT_BUS == LVDS_TYPE)
  208. #if(BOARD_TYPE == DEMO1_PCB)
  209.     8,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,0xfc,
  210. #else
  211.     7,      N_INC,  TC_DATA_PORT_96,    0x04,0x10,0x11,0x80,
  212. #endif
  213. //    7,      N_INC,  TC_DATA_PORT_96,    0x40,0x10,0x11,0x08,
  214. #endif
  217. #if(OUTPUT_BUS == LVDS_TYPE)
  219. #if(LVDS_MAP1 == LVDS_MAP)
  220.    9,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x22,0x80,0x80,0x68,
  221. #else
  222.    9,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x23,0x80,0x80,0x68,
  223. #endif
  225. #endif
  228.     0
  229. };
  231. // Be Careful !!
  232. // Display window setting in FreeV[] MUST follow the definition of
  233. // 1. DISP_WID and DISP_LEN
  234. // 2. DH_ACT_STA_POS and DH_ACT_END_POS
  235. // 3. DV_ACT_STA_POS and DV_ACT_END_POS
  236. // 4. Background window must be the same as active window.
  238. unsigned char code FreeV[]  =
  239. {
  241.     27, Y_INC,  VDIS_CTRL_20,       0x20 | DISP_BIT | DISPLAY_PORT,                 // Disable display timing
  243.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  244.                                     (STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8),     // DH_TOTAL
  245.                                     STD_HSYNC_WIDTH,                                // DH_HS_END
  246.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
  247.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
  248.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
  249.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
  250.                                     (STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8),     // DV_TOTAL
  251.                                     STD_VSYNC_LENGTH,                               // DV_VS_END
  252.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
  253.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
  254.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
  255.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
  257.     4,  N_INC,  VDIS_CTRL_20,       0x23 | DISP_BIT | DISPLAY_PORT,                 // Enable free-run background
  259.     // Force display timing start
  260.     6,  Y_INC,  YUV2RGB_39,         0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
  261.     4,  N_INC,  DIS_TIMING0_3A,     0x00 | DCLK_DELAY,
  263.     4,  N_INC,  INT_FLD_DETECT_14,  0x00,
  264.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  266. 4,  N_INC,  SCALE_CTRL_15,      0x00,
  268.     4,  N_INC,  FILTER_CTRL0_1B,    0xc4,
  271.     0
  272. };
  274. unsigned char code OSD_PWUP_INI[]   =
  275. {
  277.     5,  Y_INC,  OSD_ADDR_MSB_90, 0xc0,0x02,
  278. 6,  N_INC,  OSD_DATA_92,     0x03,0x08,0x00,
  280.     0
  281. };
  284. ///////////////////////////////////////////////////////////////////////////
  285. //VGA mode detect range
  286. unsigned int code VGA_Mode[][6] =
  287. {
  288. //      HF_min, HF_max, VL_min, VL_max, HF_std, VS+1
  289.     {   0,      0,      0,      0,      0,      0       }, //00:No Signal
  291.     {   764,    806,    620,    636,    781,    2+1     }, //01:VGA [640/720]*350*50Hz
  292.     {   764,    806,    620,    636,    781,    2+1     }, //02:VGA [640/720]*400*50Hz
  293.     {   764,    806,    516,    532,    781,    2+1     }, //03:VGA [640/720]*350*60Hz
  294.     {   764,    806,    516,    532,    781,    2+1     }, //04:VGA [640/720]*400*60Hz
  296.     {   969,    1021,   431,    447,    990,    8+1     }, //05:640*400*56hz
  297.     {   768,    810,    440,    456,    785,    2+1     }, //06:640*350*70hz
  298.     {   764,    806,    440,    456,    781,    2+1     }, //07:720*350*70hz
  299.     {   764,    806,    440,    456,    781,    2+1     }, //08:640*400*70hz
  300.     {   764,    806,    440,    456,    781,    2+1     }, //09:700*400*70hz
  301.     {   635,    670,    436,    452,    649,    3+1     }, //10:640*350*85hz
  302.     {   635,    670,    436,    452,    649,    3+1     }, //11:640*400*85hz
  303.     {   634,    669,    437,    453,    648,    3+1     }, //12:720*400*85hz
  304.     {   764,    806,    620,    636,    781,    2+1     }, //13:640*480*50hz
  305.     {   764,    806,    516,    532,    781,    2+1     }, //14:640*480*60hz
  306.     {   687,    724,    516,    532,    702,    3+1     }, //15:640*480*66hz
  307.     {   635,    670,    511,    527,    649,    3+1     }, //16:640*480*72hz
  308.     {   641,    676,    495,    507,    655,    3+1     }, //17:640*480*75hz
  309.     {   556,    586,    500,    516,    568,    3+1     }, //18:640*480*85hz
  310.     {   684,    721,    616,    632,    699,    2+1     }, //19:800*600*56hz
  311.     {   635,    670,    619,    635,    649,    4+1     }, //20:800*600*60hz
  312.     {   492,    519,    721,    737,    503,    6+1     }, //21:800*600*66hz
  313.     {   500,    527,    657,    673,    511,    6+1     }, //22:800*600*72hz
  314.     {   513,    541,    616,    632,    524,    3+1     }, //23:800*600*75hz
  315.     {   448,    473,    622,    638,    458,    3+1     }, //24:800*600*85hz
  316.     {   483,    510,    658,    674,    494,    3+1     }, //25:832*624*75hz
  317.     {   497,    524,    797,    813,    508,    6+1     }, //26:1024*768*60hz
  318.     {   493,    520,    810,    826,    504,    6+1     }, //27:1024*768*59hz
  319.     {   445,    470,    807,    823,    455,    4+1     }, //28:1024*768*66hz
  320.     {   428,    449,    797,    813,    435,    6+1     }, //29:1024*768*70hz
  321.     {   399,    421,    795,    811,    408,    3+1     }, //30:1024*768*74hz
  322.     {   400,    422,    791,    807,    409,    3+1     }, //31:1024*768*75hz
  323.     {   350,    370,    799,    815,    358,    3+1     }, //32:1024*768*85hz
  324.     {   339,    358,    834,    850,    347,    8+1     }, //33:1024*800*84hz
  325.     {   356,    376,    891,    907,    364,    3+1     }, //34:1152*864*75hz
  326.     {   350,    370,    906,    922,    358,    3+1     }, //35:1152*870*75hz
  327.     {   389,    411,    928,    944,    398,    4+1     }, //36:1152*900*66hz
  328.     {   335,    354,    934,    950,    343,    8+1     }, //37:1152*900*76hz
  329.     {   401,    423,    991,    1007,   410,    3+1     }, //38:1280*960*60hz
  330.     {   280,    295,    1002,   1018,   286,    3+1     }, //39:1280*960*85hz
  331.     {   376,    396,    1057,   1073,   384,    3+1     }, //40:1280*1024*60hz
  332.     {   312,    329,    1060,   1076,   319,    3+1     }, //41:1280*1024*72hz
  333.     {   296,    313,    1057,   1073,   303,    8+1     }, //42:1280*1024*76hz
  334.     {   300,    317,    1057,   1073,   307,    3+1     }, //43:1280*1024*75hz
  335.     {   264,    279,    1063,   1079,   270,    3+1     }, //44:1280*1024*85hz
  336.     {   321,    339,    1241,   1257,   328,    3+1     }, //45:1600*1200*60hz
  338.     {   0,      0,      0,      0,      0,      0       }, //46:Mode reserved 00
  339.     {   0,      0,      0,      0,      0,      0       }, //47:Mode reserved 01
  340.     {   0,      0,      0,      0,      0,      0       }, //48:Mode reserved 02
  341.     {   0,      0,      0,      0,      0,      0       }, //49:Mode reserved 03
  343.     {   642,    1230,   418,    497,    0,      2+1     }, //50:NewMode720x400
  344.     {   535,    1025,   498,    637,    0,      2+1     }, //51:NewMode640x480
  345.     {   428,    820,    618,    785,    0,      2+1     }, //52:NewMode800x600
  346.     {   334,    641,    786,    881,    0,      2+1     }, //53:NewMode1024x768
  347.     {   297,    570,    882,    917,    0,      2+1     }, //54:NewMode1152x864
  348.     {   285,    547,    918,    977,    0,      2+1     }, //55:NewMode1152x900
  349.     {   267,    513,    978,    1041,   0,      2+1     }, //56:NewMode1280x960
  350.     {   251,    481,    1042,   1217,   0,      2+1     }, //57:NewMode1280x1024
  351.     {   292,    559,    1218,   1328,   0,      2+1     }, //58:NewMode1600x1200
  352. };
  354. unsigned int code Mode_Preset[][5]   =
  355. {
  356.     //  DH_TOTAL    DH_ACT_WID  DV_ACT_LEN      DCLK_M/N    IVS_DELAY
  357.     {   1408,       1280,       1024,           0,          0       }, //00:No Signal
  359.     //  VGA confused mode
  360.     {   1408,       1280,       1024,           0,          63      }, //01:VGA [640/720]*350*50Hz
  361.     {   1408,       1280,       1024,           0,          31      }, //02:VGA [640/720]*400*50Hz
  362.     {   1408,       1280,       1024,           0,          63      }, //03:VGA [640/720]*350*60Hz
  363.     {   1408,       1280,       1024,           0,          31      }, //04:VGA [640/720]*400*60Hz
  365.     //  Standard mode
  366.     {   1568,       1280,       1024,           0,          7       }, //05:640*400*56hz
  367.     {   1408,       1280,       1024,           0,          7       }, //06:640*350*70hz
  368.     {   1408,       1280,       1024,           0,          7       }, //07:720*350*70hz
  369.     {   1408,       1280,       1024,           0,          7       }, //08:640*400*70hz
  370.     {   1408,       1280,       1024,           0,          7       }, //09:700*400*70hz
  371.     {   1408,       1280,       896,            0,          7       }, //10:640*350*85hz
  372.     {   1408,       1280,       1024,           0,          7       }, //11:640*400*85hz
  373.     {   1376,       1280,       1024,           0,          7       }, //12:720*400*85hz
  374.     {   1408,       1280,       1024,           0,          31      }, //13:640*480*50hz
  375.     {   1408,       1280,       1024,           0,          7       }, //14:640*480*60hz
  376.     {   1504,       1280,       1024,           0,          7       }, //15:640*480*66hz
  377.     {   1456,       1280,       1024,           0,          7       }, //16:640*480*72hz
  378.     {   1472,       1280,       1024,           0,          3       }, //17:640*480*75hz
  379.     {   1408,       1280,       1024,           0,          7       }, //18:640*480*85hz
  380.     {   1632,       1280,       1024,           0,          3       }, //19:800*600*56hz
  381.     {   1640,       1280,       1024,           0,          7       }, //20:800*600*60hz
  382.     {   1408,       1280,       1024,           0,          7       }, //21:800*600*66hz
  383.     {   1408,       1280,       1024,           0,          7       }, //22:800*600*72hz
  384.     {   1408,       1280,       1024,           0,          3       }, //23:800*600*75hz
  385.     {   1408,       1280,       1024,           0,          7       }, //24:800*600*85hz
  386.     {   1568,       1280,       1024,           0,          7       }, //25:832*624*75hz
  387.     {   1408,       1280,       1024,           0,          7       }, //26:1024*768*60hz
  388.     {   1408,       1280,       1024,           0,          7       }, //27:1024*768*59hz
  389.     {   1408,       1280,       1024,           0,          7       }, //28:1024*768*66hz
  390.     {   1632,       1280,       1024,           0,          7       }, //29:1024*768*70hz
  391.     {   1408,       1280,       1024,           0,          7       }, //30:1024*768*74hz
  392.     {   1408,       1280,       1024,           0,          7       }, //31:1024*768*75hz
  393.     {   1408,       1280,       1024,           0,          7       }, //32:1024*768*85hz
  394.     {   1408,       1280,       1024,           0,          7       }, //33:1024*800*84hz
  395.     {   1408,       1280,       1024,           0,          7       }, //34:1152*864*75hz
  396.     {   1408,       1280,       1024,           0,          7       }, //35:1152*870*75hz
  397.     {   1408,       1280,       1024,           0,          7       }, //36:1152*900*66hz
  398.     {   1408,       1280,       1024,           0,          7       }, //37:1152*900*76hz
  399.     {   1408,       1280,       1024,           0,          7       }, //38:1280*960*60hz
  400.     {   1408,       1280,       1024,           0,          7       }, //39:1280*960*85hz
  401.     {   1408,       1280,       1024,           0,          7       }, //40:1280*1024*60hz
  402.     {   1408,       1280,       1024,           0,          7       }, //41:1280*1024*72hz
  403.     {   1408,       1280,       1024,           0,          7       }, //42:1280*1024*76hz
  404.     {   1408,       1280,       1024,           0,          7       }, //43:1280*1024*75hz
  405.     {   1408,       1280,       1024,           0,          7       }, //44:1280*1024*85hz
  406.     {   1408,       1280,       1024,           0,          7       }, //45:1600*1200*60hz
  408.     //  Reserved mode
  409.     {   1408,       1280,       1024,           0,          0       }, //46:Mode reserved 00
  410.     {   1408,       1280,       1024,           0,          0       }, //47:Mode reserved 01
  411.     {   1408,       1280,       1024,           0,          0       }, //48:Mode reserved 02
  412.     {   1408,       1280,       1024,           0,          0       }, //49:Mode reserved 03
  414.     //  Unknown user mode
  415.     {   1408,       1280,       1024,           0,          3       }, //50:NewMode720x400
  416.     {   1408,       1280,       1024,           0,          3       }, //51:NewMode640x480
  417.     {   1408,       1280,       1024,           0,          3       }, //52:NewMode800x600
  418.     {   1408,       1280,       1024,           0,          3       }, //53:NewMode1024x768
  419.     {   1408,       1280,       1024,           0,          3       }, //54:NewMode1152x864
  420.     {   1408,       1280,       1024,           0,          3       }, //55:NewMode1152x900
  421.     {   1408,       1280,       1024,           0,          3       }, //56:NewMode1280x960
  422.     {   1408,       1280,       1024,           0,          3       }, //57:NewMode1280x1024
  423.     {   1408,       1280,       1024,           0,          3       }, //58:NewMode1600x1200
  424.     
  425.     //  Safe display mode
  426.     {   1408,       1280,       1024,           0,          3       }, //59:Undefined SU mode
  427.     {   1408,       1280,       1024,           0,          3       }, //60:Undefined SD mode
  428. };
  430. ///////////////////////////////////////////////////////////////////////////////
  431. //Video Setting
  432. #if (VIDEO_CHIP == VDC_NONE)
  433. // No Video Decoder
  434. unsigned char code RTD_VIDEO_60[]   = { 0 };
  435. unsigned char code RTD_VIDEO_50[]   = { 0 };
  437. #else
  439. #if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 || VIDEO_CHIP == VDC_SAA7118)
  441. #define H_60    0x91//0x70    // For SAA7114/7118
  442. #define H_50    0x97//0x7c    // For SAA7114/7118
  444. #else
  446. #define H_60    0x56    // For SAA7111A
  447. #define H_50    0x5e    // For SAA7111A
  449. #endif
  451. unsigned char code RTD_VIDEO_60[]   =
  452. {
  453.     11, Y_INC,  IPH_ACT_STA_06,     H_60, 0x00, 0xb8, 0x02,
  454.                                     0x14, 0x00, 0xed, 0x00,
  456.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x40, 0x3b, 0x00,
  458.     4,  N_INC,  FS_FT_DELAY_1E,     0x0f,//0x1a,
  459.     
  460.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0xed, 0x00,
  462.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  464.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  466.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  468.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  470.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  471.  
  472.                                     0x7e, 0x05,
  473.                                     0x10,
  474.                                     0x20, 0x00,
  475.                                     0x20, 0x00,
  476.                                     0x20, 0x05,
  477.                                     0x20, 0x05,
  478.                                     0x80, 0x04,
  479.                                     0x03,
  480.                                     0x0f, 0x00,
  481.                                     0x0f, 0x00,
  482.                                     0x0f, 0x04,
  483.                                     0x0f, 0x04,
  484.                                     0x13, 0x20,
  486. 7,  Y_INC,  DPLL_CTRL_D0,       0x18, 0x62, 0x3a,0x07,
  488. 5,  Y_INC, DCLK_OFFSET_LSB_9A,  0x70, 0x29,
  490. 4,  N_INC, FX_LST_LEN_H_5A,     0x08,
  492.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  494.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  496.     0
  497. };
  499. unsigned char code RTD_VIDEO_50[]=
  500. {
  501.     11, Y_INC,  IPH_ACT_STA_06,     H_50, 0x00, 0xb8, 0x02,
  502.                                     0x18, 0x00, 0x1a, 0x01,
  504.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x80, 0x46, 0x00,
  506.     4,  N_INC,  FS_FT_DELAY_1E,     0x13,
  507.     
  508.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0x1a, 0x01,
  510.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  512.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  514.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  518. //  6,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x75, 0x07,
  520.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  521.                                     DISP_INV | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,
  522.                                     0x7e, 0x05,
  523.                                     0x10,
  524.                                     0x20, 0x00,
  525.                                     0x20, 0x00,
  526.                                     0x20, 0x05,
  527.                                     0x20, 0x05,
  528.                                     0x80, 0x04,
  529.                                     0x03,
  530.                                     0x0d, 0x00,
  531.                                     0x0d, 0x00,
  532.                                     0x0d, 0x04,
  533.                                     0x0d, 0x04,
  534.                                     0x17, 0x20,
  536. 7,  Y_INC,  DPLL_CTRL_D0,       0x10, 0x52, 0x3a,0x07,
  538. 5,  Y_INC, DCLK_OFFSET_LSB_9A,  0xc2, 0x29,
  540. 4,  N_INC, FX_LST_LEN_H_5A,     0x08,
  543.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  545.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  547.     0
  548. };
  550. #endif
  552. #else 
  554. extern unsigned char code RTD_PWUP_INI[];
  555. extern unsigned char code RTD_DDC_TABLE[];
  556. extern unsigned char code RTD_IO_INI[];
  558. extern unsigned char code FreeV[];
  559. extern unsigned char code OSD_PWUP_INI[];
  561. extern unsigned int code VGA_Mode[][6];
  562. extern unsigned int code Mode_Preset[][5];
  564. extern unsigned char code RTD_VIDEO_60[];
  565. extern unsigned char code RTD_VIDEO_50[];
  567. #endif