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Disp_B3.h
资源名称：RTD2523_MTV512.rar　[点击查看]
上传用户：xmyjxjd
上传日期：2013-05-04
资源大小：1517k
文件大小：41k
源码类别：

其他嵌入式/单片机内容

开发平台：

C/C++

Disp_B3.h：源码内容
  2. ///////////////////////////////////////////////////////////////////
  3. // Definitions for Display Port
  4. #define SINGLE_PORT         0x00    // Single port (Single pixel output)
  5. #define DOUBLE_PORT         0x04    // Double port (Double pixel output)
  7. #define DISPLAY_PORT        DOUBLE_PORT
  9. ///////////////////////////////////////////////////////////////////
  10. // Definitions for Display Color
  11. #define DISP_18BIT          0x10    // 18-bit RGB output
  12. #define DISP_24BIT          0x00    // 24-bit RGB output 
  14. #define DISP_BIT            DISP_18BIT
  16. ///////////////////////////////////////////////////////////////////
  17. // Definitions for Display Timing Feature
  18. #define MASK_FIRST_DHS      0x80    // Mask 1st DHS
  19. #define NO_MASKING          0x00    // No masking 
  21. #define DHS_MASK            NO_MASKING    
  23. ///////////////////////////////////////////////////////////////////
  24. // Definitions for Display Signal
  25. #define DISP_INV            0x0C    // DVS : neg , DHS : neg , DEN : pos
  26. #define DCLK_INV            0x08    // DCLK : pos
  27. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  29. ///////////////////////////////////////////////////////////////////
  30. //Definitions for display port control
  31. #define DISP_EO_SWAP        0x20
  32. #define DISP_RB_SWAP        0x00//0x10
  33. #define DISP_ML_SWAP        0x00//0x08
  34. ///////////////////////////////////////////////////////////////////
  35. // Definitions for Display Settings
  37. #define MAX_DCLK            138     // Maximum display clock(MHz) that panel can support
  38. #define MAX_RATE            86      // Maximum display refresh rate in Hz that panel can support
  40. #define DH_ACT_STA_POS      0x0020  // DH_ACT_STA_POS should be as small as possible !!!
  41. #define DH_ACT_END_POS      0x0520
  43. #define DV_ACT_STA_POS      0x000c  // DV_ACT_STA_POS should be as small as possible !!!
  44. #define DV_ACT_END_POS      0x040c
  46. #define DISP_WID            (DH_ACT_END_POS - DH_ACT_STA_POS)   // 0x0500 = 1280 pixels
  47. #define DISP_LEN            (DV_ACT_END_POS - DV_ACT_STA_POS)   // 0x0400 = 1024 lines
  49. #define STD_DH_TOTAL        0x0580  // Standard display clock number in one display horizontal line
  50. #define STD_DV_TOTAL        0x0480  // Standard display horizontal line in one display frame
  51. #define STD_HSYNC_WIDTH     0x10    // Display HSYNC clock width
  52. #define STD_VSYNC_LENGTH    0x03    // Display VSYNC line length
  54. #define MIN_DV_TOTAL        0x0410  // Minimum VSYNC that panel can support
  56. #define MIN_LAST_DHT        0       // Must set to 0 if you don't care last-line length
  57. #define VIDEO_ML_DHT        0       // Minimum last-line length for video
  59. #define USER_MODE_NCODE     20      // NEVER change this setting !!!
  61. #define DISP_ALIGN          0       // 0-Left alignment, 1-Right alignment
  64. #define AUTO_SWITCH        0x60      // Auto Switch to freerun mode
  67. /*
  68. ///////////////////////////////////////////////////////////////////
  69. // Definitions for RTD3001
  70. #define All_LINE_BUF        0x02    // Turn on all line buffers
  71. #define REQ_DELAY           0x40    // 0.5ns delay for request
  72. #define V_MAC_DELAY         0x10    // 0.5ns delay for Vertical MAC
  73. #define H_MAC_DELAY         0x04    // 0.5ns delay for Horizontal MAC
  74. #define DCLK_DELAY          0x01    // 1.0ns delay for DCLK
  76. #define HINIT_COEFF         0x00    // Horizontal initial coefficient = 0xc000
  77. #define REQMODE_00B         0x00    // Imporved mode 1 : REG[28]-bit3 = 0
  78. #define REQMODE_01B         0x80    // Imporved mode 1 : REG[31]-bit7 = 1
  79. #define ODDCTRL_VGA         0x38    // REG[31]-bit5  : Odd signal for V inital toggle. (0 : inverse)
  80.                                     // REG[31]-bit4  : Odd signal to control FS_DELAY_FINE_TUNING. (0 : enable)
  81.                                     // REG[31]-bit3  : Odd signal to enable FS_DELAY_FINE_TUNING. (1 : inverse)
  82. #define ODDCTRL_VIDEO       0x28
  83. */
  85. //---------------------------------- 1280x1024 ---------------------------------
  86. ///////////////////////////////////////////////////////////////////////////
  87. #ifdef __MAIN__
  89. unsigned char code RTD_PWUP_INI[]   =
  90. { 
  91.     5,      Y_INC,  HOSTCTRL_02,        0x42,0x00,
  93.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  94.     7,      N_INC,  TC_DATA_PORT_96,    0x00,0x00,0x00,0x00,
  95.     9,      Y_INC,  GP1_ODOCTRL_F6,     0x00,0x00,0x00,0x00,0x00,0x00,
  97.     6,      Y_INC,  IRQ_CTRL1_0E,       0x00,0x80,0x00,
  99.     4,      N_INC,  INT_FLD_DETECT_14,  0x00,
  101.     25, Y_INC, DH_TOTAL_22, 0x08,0x00,0x02,0x04,0x00,0x04,0x00,0x06,0x00,0x06,0x00,
  102. 0x06,0x00,0x01,0x02,0x00,0x02,0x00,0x04,0x00,0x04,0x00,
  104.     6,      Y_INC,  YUV2RGB_39,         0x00,0x00,0x00,
  105.     
  106.     5,      Y_INC,  DUTY_FINE_TUNE_3E,  0xc0,0x0e,          // For improving display speed
  107.     
  108.     4,      N_INC,  MEAS_HS_LATCH_4E,   0x00,
  110.     5,      Y_INC,  CLAMP_55,           0x04,0x10,
  112.     4,      N_INC,  COLOR_CTRL_5D,      0x03,
  114.     4,      N_INC,  OP_CRC_CTRL_68,     0x88,               // For improving display speed
  116. //    6,      Y_INC,  PATTERN_GEN_6C,     0x00,0x83 | DISP_EO_SWAP | DISP_RB_SWAP | DISP_ML_SWAP,0x00,
  117.     6,      Y_INC,  PATTERN_GEN_6C,     0x00,0x33,0x00,
  119.     4,      N_INC,  SD_CTRL_70,         0x00,
  121.     6,      Y_INC,  IVS_DELAY_8C,       0x00,0x00,0x00,
  122. //--------------------------------------------------------------------
  123. // For RSDS TCON START
  124. //--------------------------------------------------------------------
  125. 5,      Y_INC,  TC_ADDR_PORT_95,    0x20,0x0c,  // FXDIO TCON3
  126.     5,      Y_INC,  TC_ADDR_PORT_95,    0x21,0x40,
  127.     5,      Y_INC,  TC_ADDR_PORT_95,    0x22,0x0c,
  128.     5,      Y_INC,  TC_ADDR_PORT_95,    0x23,0xa0,
  129.     5,      Y_INC,  TC_ADDR_PORT_95,    0x24,0x22,
  130.     5,      Y_INC,  TC_ADDR_PORT_95,    0x25,0xa1,
  131.     5,      Y_INC,  TC_ADDR_PORT_95,    0x26,0x80,    
  136.     5,      Y_INC,  TC_ADDR_PORT_95,    0x28,0x0c,  // XSTB TCON4
  137.     5,      Y_INC,  TC_ADDR_PORT_95,    0x29,0x40,
  138.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2A,0X0c,
  139.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2B,0x35,
  140.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2C,0x22,
  141.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2D,0xac,
  142.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2E,0x80,    
  145. 5,      Y_INC,  TC_ADDR_PORT_95,    0x60,0x0c,   // YOE TCON11 
  146.     5,      Y_INC,  TC_ADDR_PORT_95,    0x61,0x40, 
  147.     5,      Y_INC,  TC_ADDR_PORT_95,    0x62,0x0c,
  148.     5,      Y_INC,  TC_ADDR_PORT_95,    0x63,0x94,
  149.     5,      Y_INC,  TC_ADDR_PORT_95,    0x64,0x52,
  150.     5,      Y_INC,  TC_ADDR_PORT_95,    0x65,0x14,
  151.     5,      Y_INC,  TC_ADDR_PORT_95,    0x66,0xc0,    
  154. 5,      Y_INC,  TC_ADDR_PORT_95,    0x08,0x0c,  // BXDIO TCON0
  155.     5,      Y_INC,  TC_ADDR_PORT_95,    0x09,0x40,
  156.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0A,0x0c,
  157.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0B,0x9f,
  158.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0C,0x22,
  159.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0D,0xa9,
  160.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0E,0x80,    
  163. 5,      Y_INC,  TC_ADDR_PORT_95,    0x58,0x0c, // YDIO TCON10
  164.     5,      Y_INC,  TC_ADDR_PORT_95,    0x59,0x00,
  165.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5A,0x0e,
  166.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5B,0xd0,
  167.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5C,0x33,
  168.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5D,0xd7,
  169.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5E,0x88,    
  173. 5,      Y_INC,  TC_ADDR_PORT_95,    0x30,0x0c,  // YCLK TCON5
  174.     5,      Y_INC,  TC_ADDR_PORT_95,    0x31,0x40,
  175.     5,      Y_INC,  TC_ADDR_PORT_95,    0x32,0X0c,
  176.     5,      Y_INC,  TC_ADDR_PORT_95,    0x33,0xF4,
  177.     5,      Y_INC,  TC_ADDR_PORT_95,    0x34,0x21,
  178.     5,      Y_INC,  TC_ADDR_PORT_95,    0x35,0x94,
  179.     5,      Y_INC,  TC_ADDR_PORT_95,    0x36,0x80,    
  180. //#if(ANTI_FLICKER)
  181. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x38,0x0c,   // POL TCON6
  182. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x39,0x40,
  183. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x3a,0x0E,
  184. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x3b,0x00,
  185. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x3c,0x00,
  186. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x3d,0x01,
  187. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x3e,0x88,    
  188.   
  189. 5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  190.     5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  191.     5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  192.     5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  193.     5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  194.     5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  195.     5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x8C,    
  196. //#else
  197. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  198. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  199. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  200. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  201. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  202. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  203. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x88,    
  204. //#endif
  205. /*
  206. 5,      Y_INC,  TC_ADDR_PORT_95,    0x20,0x0c,  // FXDIO TCON3
  207.     5,      Y_INC,  TC_ADDR_PORT_95,    0x21,0x40,
  208.     5,      Y_INC,  TC_ADDR_PORT_95,    0x22,0x0c,
  209.     5,      Y_INC,  TC_ADDR_PORT_95,    0x23,0xa0,
  210.     5,      Y_INC,  TC_ADDR_PORT_95,    0x24,0x22,
  211.     5,      Y_INC,  TC_ADDR_PORT_95,    0x25,0xa1,
  212.     5,      Y_INC,  TC_ADDR_PORT_95,    0x26,0x80,    
  215.   5,      Y_INC,  TC_ADDR_PORT_95,    0x28,0x0c,  // XSTB TCON4
  216.     5,      Y_INC,  TC_ADDR_PORT_95,    0x29,0x40,
  217.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2A,0X0c,
  218.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2B,0x35,
  219.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2C,0x22,
  220.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2D,0xac,
  221.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2E,0x80,    
  224. 5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,  // POL TCON7
  225.     5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  226.     5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0d,
  227.     5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  228.     5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  229.     5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  230.     5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x88,    
  233. 5,      Y_INC,  TC_ADDR_PORT_95,    0x08,0x0c,  // BXDIO TCON0
  234.     5,      Y_INC,  TC_ADDR_PORT_95,    0x09,0x40,
  235.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0A,0x0c,
  236.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0B,0x9f,
  237.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0C,0x22,
  238.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0D,0xa9,
  239.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0E,0x80,    
  242. 5,      Y_INC,  TC_ADDR_PORT_95,    0x58,0x0d,   // YDIO TCON10
  243.     5,      Y_INC,  TC_ADDR_PORT_95,    0x59,0x00,
  244.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5A,0x0f,
  245.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5B,0xd0,
  246.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5C,0x33,
  247.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5D,0xd7,
  248.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5E,0x88,    
  252. 5,      Y_INC,  TC_ADDR_PORT_95,    0x30,0x0c,    // YCLK TCON5
  253.     5,      Y_INC,  TC_ADDR_PORT_95,    0x31,0x40,
  254.     5,      Y_INC,  TC_ADDR_PORT_95,    0x32,0X0c,
  255.     5,      Y_INC,  TC_ADDR_PORT_95,    0x33,0xF4,
  256.     5,      Y_INC,  TC_ADDR_PORT_95,    0x34,0x21,
  257.     5,      Y_INC,  TC_ADDR_PORT_95,    0x35,0x94,
  258.     5,      Y_INC,  TC_ADDR_PORT_95,    0x36,0x80,    
  260. 5,      Y_INC,  TC_ADDR_PORT_95,    0x60,0x0c,   // YOE TCON11 
  261.     5,      Y_INC,  TC_ADDR_PORT_95,    0x61,0x40, 
  262.     5,      Y_INC,  TC_ADDR_PORT_95,    0x62,0x0c,
  263.     5,      Y_INC,  TC_ADDR_PORT_95,    0x63,0x94,
  264.     5,      Y_INC,  TC_ADDR_PORT_95,    0x64,0x52,
  265.     5,      Y_INC,  TC_ADDR_PORT_95,    0x65,0x14,
  266.     5,      Y_INC,  TC_ADDR_PORT_95,    0x66,0x80,  
  267. */
  268. /*
  269. 5,      Y_INC,  TC_ADDR_PORT_95,    0x20,0x0c,  // FXDIO TCON3
  270.     5,      Y_INC,  TC_ADDR_PORT_95,    0x21,0x40,
  271.     5,      Y_INC,  TC_ADDR_PORT_95,    0x22,0x0c,
  272.     5,      Y_INC,  TC_ADDR_PORT_95,    0x23,0xa0,
  273.     5,      Y_INC,  TC_ADDR_PORT_95,    0x24,0x22,
  274.     5,      Y_INC,  TC_ADDR_PORT_95,    0x25,0xa1,
  275.     5,      Y_INC,  TC_ADDR_PORT_95,    0x26,0x80,    
  278.     5,      Y_INC,  TC_ADDR_PORT_95,    0x28,0x0c,  // XSTB TCON4
  279.     5,      Y_INC,  TC_ADDR_PORT_95,    0x29,0x40,
  280.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2A,0X0c,
  281.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2B,0x35,
  282.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2C,0x22,
  283.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2D,0xac,
  284.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2E,0x80,    
  287. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  288. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  289. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  290. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  291. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  292. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  293. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x88,    
  295. 5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  296.     5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  297.     5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  298.     5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  299.     5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  300.     5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  301.     5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x8C,    
  303. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON6
  304. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  305. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0E,
  306. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  307. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  308. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  309. //    5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x88,    
  312. 5,      Y_INC,  TC_ADDR_PORT_95,    0x08,0x0c,  // BXDIO TCON0
  313.     5,      Y_INC,  TC_ADDR_PORT_95,    0x09,0x40,
  314.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0A,0x0c,
  315.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0B,0x9f,
  316.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0C,0x22,
  317.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0D,0xa9,
  318.     5,      Y_INC,  TC_ADDR_PORT_95,    0x0E,0x80,    
  321. 5,      Y_INC,  TC_ADDR_PORT_95,    0x30,0x0c,  // YCLK TCON5
  322.     5,      Y_INC,  TC_ADDR_PORT_95,    0x31,0x40,
  323.     5,      Y_INC,  TC_ADDR_PORT_95,    0x32,0X0c,
  324.     5,      Y_INC,  TC_ADDR_PORT_95,    0x33,0xF4,
  325.     5,      Y_INC,  TC_ADDR_PORT_95,    0x34,0x21,
  326.     5,      Y_INC,  TC_ADDR_PORT_95,    0x35,0x94,
  327.     5,      Y_INC,  TC_ADDR_PORT_95,    0x36,0x80,  
  330. 5,      Y_INC,  TC_ADDR_PORT_95,    0x58,0x0c, // YDIO TCON10
  331.     5,      Y_INC,  TC_ADDR_PORT_95,    0x59,0x00,
  332.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5a,0x0e,
  333.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5b,0xd0,
  334.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5c,0x33,
  335.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5d,0xd7,
  336.     5,      Y_INC,  TC_ADDR_PORT_95,    0x5e,0x88,    
  338. 5,      Y_INC,  TC_ADDR_PORT_95,    0x60,0x0c,   // YOE TCON11
  339.     5,      Y_INC,  TC_ADDR_PORT_95,    0x61,0x40, 
  340.     5,      Y_INC,  TC_ADDR_PORT_95,    0x62,0x0c,
  341.     5,      Y_INC,  TC_ADDR_PORT_95,    0x63,0x94,
  342.     5,      Y_INC,  TC_ADDR_PORT_95,    0x64,0x52,
  343.     5,      Y_INC,  TC_ADDR_PORT_95,    0x65,0x14,
  344.     5,      Y_INC,  TC_ADDR_PORT_95,    0x66,0x80, 
  347. 5,      Y_INC,  TC_ADDR_PORT_95,    0x60,0x0c,   // YOE TCON11
  348.     5,      Y_INC,  TC_ADDR_PORT_95,    0x61,0x40, 
  349.     5,      Y_INC,  TC_ADDR_PORT_95,    0x62,0x0c,
  350.     5,      Y_INC,  TC_ADDR_PORT_95,    0x63,0x94,
  351.     5,      Y_INC,  TC_ADDR_PORT_95,    0x64,0x52,
  352.     5,      Y_INC,  TC_ADDR_PORT_95,    0x65,0x14,
  353.     5,      Y_INC,  TC_ADDR_PORT_95,    0x66,0xc0,    
  354. */
  355. /*
  356. 5,      Y_INC,  TC_ADDR_PORT_95,    0x10,0x0c,  // FXDIO TCON1
  357.     5,      Y_INC,  TC_ADDR_PORT_95,    0x11,0x40,
  358.     5,      Y_INC,  TC_ADDR_PORT_95,    0x12,0x0c,
  359.     5,      Y_INC,  TC_ADDR_PORT_95,    0x13,0xa0,
  360.     5,      Y_INC,  TC_ADDR_PORT_95,    0x14,0x22,
  361.     5,      Y_INC,  TC_ADDR_PORT_95,    0x15,0xa1,
  362.     5,      Y_INC,  TC_ADDR_PORT_95,    0x16,0x80,    
  367.     5,      Y_INC,  TC_ADDR_PORT_95,    0x18,0x0c,  // XSTB TCON2
  368.     5,      Y_INC,  TC_ADDR_PORT_95,    0x19,0x40,
  369.     5,      Y_INC,  TC_ADDR_PORT_95,    0x1A,0X0c,
  370.     5,      Y_INC,  TC_ADDR_PORT_95,    0x1B,0x35,
  371.     5,      Y_INC,  TC_ADDR_PORT_95,    0x1C,0x22,
  372.     5,      Y_INC,  TC_ADDR_PORT_95,    0x1D,0xac,
  373.     5,      Y_INC,  TC_ADDR_PORT_95,    0x1E,0x80,    
  376. 5,      Y_INC,  TC_ADDR_PORT_95,    0x20,0x0c,   // YOE TCON3 
  377.     5,      Y_INC,  TC_ADDR_PORT_95,    0x21,0x40, 
  378.     5,      Y_INC,  TC_ADDR_PORT_95,    0x22,0x0c,
  379.     5,      Y_INC,  TC_ADDR_PORT_95,    0x23,0x94,
  380.     5,      Y_INC,  TC_ADDR_PORT_95,    0x24,0x52,
  381.     5,      Y_INC,  TC_ADDR_PORT_95,    0x25,0x14,
  382.     5,      Y_INC,  TC_ADDR_PORT_95,    0x26,0xc0,    
  385. 5,      Y_INC,  TC_ADDR_PORT_95,    0x28,0x0c,  // BXDIO TCON4
  386.     5,      Y_INC,  TC_ADDR_PORT_95,    0x29,0x40,
  387.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2A,0x0c,
  388.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2B,0x9f,
  389.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2C,0x22,
  390.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2D,0xa9,
  391.     5,      Y_INC,  TC_ADDR_PORT_95,    0x2E,0x80,    
  394. 5,      Y_INC,  TC_ADDR_PORT_95,    0x50,0x0c, // YDIO TCON9
  395.     5,      Y_INC,  TC_ADDR_PORT_95,    0x51,0x00,
  396.     5,      Y_INC,  TC_ADDR_PORT_95,    0x52,0x0e,
  397.     5,      Y_INC,  TC_ADDR_PORT_95,    0x53,0xd0,
  398.     5,      Y_INC,  TC_ADDR_PORT_95,    0x54,0x33,
  399.     5,      Y_INC,  TC_ADDR_PORT_95,    0x55,0xd7,
  400.     5,      Y_INC,  TC_ADDR_PORT_95,    0x56,0x88,    
  404. 5,      Y_INC,  TC_ADDR_PORT_95,    0x30,0x0c,  // YCLK TCON5
  405.     5,      Y_INC,  TC_ADDR_PORT_95,    0x31,0x40,
  406.     5,      Y_INC,  TC_ADDR_PORT_95,    0x32,0X0c,
  407.     5,      Y_INC,  TC_ADDR_PORT_95,    0x33,0xF4,
  408.     5,      Y_INC,  TC_ADDR_PORT_95,    0x34,0x21,
  409.     5,      Y_INC,  TC_ADDR_PORT_95,    0x35,0x94,
  410.     5,      Y_INC,  TC_ADDR_PORT_95,    0x36,0x80,    
  411. #if(ANTI_FLICKER)
  412.     5,      Y_INC,  TC_ADDR_PORT_95,    0x38,0x0c,   // POL TCON6
  413.     5,      Y_INC,  TC_ADDR_PORT_95,    0x39,0x40,
  414.     5,      Y_INC,  TC_ADDR_PORT_95,    0x3a,0x0E,
  415.     5,      Y_INC,  TC_ADDR_PORT_95,    0x3b,0x00,
  416.     5,      Y_INC,  TC_ADDR_PORT_95,    0x3c,0x00,
  417.     5,      Y_INC,  TC_ADDR_PORT_95,    0x3d,0x01,
  418.     5,      Y_INC,  TC_ADDR_PORT_95,    0x3e,0x88,    
  419.   
  420. 5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  421.     5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  422.     5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  423.     5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  424.     5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  425.     5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  426.     5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x8C,    
  427. #else
  428.     5,      Y_INC,  TC_ADDR_PORT_95,    0x40,0x0c,   // POL TCON7
  429.     5,      Y_INC,  TC_ADDR_PORT_95,    0x41,0x40,
  430.     5,      Y_INC,  TC_ADDR_PORT_95,    0x42,0x0D,
  431.     5,      Y_INC,  TC_ADDR_PORT_95,    0x43,0x00,
  432.     5,      Y_INC,  TC_ADDR_PORT_95,    0x44,0x00,
  433.     5,      Y_INC,  TC_ADDR_PORT_95,    0x45,0x01,
  434.     5,      Y_INC,  TC_ADDR_PORT_95,    0x46,0x88,    
  435. #endif
  436. */
  439. //---------------------------------------------------------------
  440. // For RSDS TCON END
  441. //---------------------------------------------------------------
  446.     7,      Y_INC,  PLL_DIV_CTRL0_C8,   0x04,0x00,0x20,0x18,
  447.  
  448.     8,      Y_INC,  DPLL_CTRL_D0,       0x10,0xa2,0x52,0x2f,0x06,   // DCLK=100MHz
  450.     13,     Y_INC,  PLL1_CTRL_D6,       0xf2,0x11,0x00,0x7f,0x30,0x0a,0x04,0x3f,0xff,0x81,
  452.     //4,      N_INC,  ADC_CTRL_E6,        0xb0,
  453.     4,      N_INC,  ADC_CTRL_E6,        0x40,
  455.     4,      N_INC,  DV_BKGD_STA_31,     0x60,
  457.     3,      ADC_FRAME_MODULE_EB,        0x06,
  459.     9,      Y_INC,  TMDS_OUTPUT_ENA_A0, 0x0f, 0xef,0x8b,0x26,0x35,0x2f,
  462.     0
  463. };
  465. unsigned char code RTD_DDC_TABLE[]  =
  466. {
  467.     5,      Y_INC,  DDC_ENABLE_FC,      0x00,0x00,  // Disable the DDC channel of VGA
  469.     131,    N_INC,  DDC_ACCESS_P_FE,    0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  470.                                         0x4a,0x8b,0x00,0x00,0x01,0x01,0x01,0x01,
  471.                                         0x1e,0x0c,0x01,0x01,0x0e,0x24,0x1b,0x78,
  472.                                         0xe8,0x8a,0x01,0x9a,0x58,0x52,0x8b,0x28,
  473.                                         0x1e,0x50,0x54,0xff,0xff,0x80,0x61,0x40,
  474.                                         0x61,0x4f,0x61,0x59,0x71,0x4f,0x81,0x40,
  475.                                         0x81,0x59,0x81,0x99,0xa9,0x40,0x00,0x00,
  476.                                         0x00,0xfc,0x00,0x31,0x37,0x27,0x27,0x20,
  477.                                         0x4c,0x43,0x44,0x0a,0x20,0x20,0x20,0x20,
  478.                                         0x00,0x00,0x00,0xfc,0x00,0x4d,0x6f,0x6e,
  479.                                         0x69,0x74,0x6f,0x72,0x0a,0x20,0x20,0x20,
  480.                                         0x20,0x20,0x00,0x00,0x00,0xfd,0x00,0x2b,
  481.                                         0x55,0x14,0x5c,0x0e,0x00,0x0a,0x20,0x20,
  482.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xff,
  483.                                         0x00,0x30,0x30,0x30,0x30,0x30,0x31,0x0a,
  484.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x00,0xbd,
  486.     4,  N_INC,  DDC_ENABLE_FC,          0x05,       // Enable the DDC channel of VGA
  487.     
  488. #if(TMDS_ENABLE)
  489.     5,      Y_INC,  DDC_ENABLE_BC,      0x00,0x00,  // Disable the DDC channel  of DVI
  491.     131,    N_INC,  DDC_ACCESS_PORT_BE, 0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  492.                                         0x26,0xCD,0x68,0x46,0x00,0x00,0x00,0x00,
  493.                                         0x23,0x0c,0x01,0x03,0x81,0x24,0x1D,0x78,
  494.                                         0xeF,0x0D,0xC2,0xa0,0x57,0x47,0x98,0x27,                                        
  495.                                         0x12,0x48,0x4F,0xBF,0xEF,0x00,0x81,0x80,
  496.                                         0x81,0x8F,0x61,0x40,0x61,0x59,0x45,0x40,
  497.                                         0x45,0x59,0x31,0x40,0x31,0x59,0xBC,0x34,
  498.                                         0x00,0x98,0x51,0x00,0x2A,0x40,0x10,0x90,
  500.                                         0x13,0x00,0x68,0x22,0x11,0x00,0x00,0x1e,
  501.                                         0x00,0x00,0x00,0xFF,0x00,0x30,0x0A,0x20,
  502.                                         0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
  503.                                         0x20,0x20,0x00,0x00,0x00,0xFC,0x00,0x41,
  504.                                         0x53,0x34,0x36,0x33,0x37,0x20,0x20,0x20,
  505.                                         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xFD,
  506.                                         0x00,0x38,0x55,0x18,0x50,0x0E,0x00,0x0A,
  507.    0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x06,
  509.     4,  N_INC,  DDC_ENABLE_BC,          0x05,       // Enable the DDC channel of DVI
  510. #endif
  512.     0
  513. };
  515. unsigned char code RTD_IO_INI[]  =
  516. {
  518.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  520.     7,      N_INC,  TC_DATA_PORT_96,    0x00,0x10,0x11,0x08,
  522. #if((OUTPUT_BUS == LVDS_TYPE) || (OUTPUT_BUS == TTL_TYPE))
  524. #if(LVDS_MAP1 == LVDS_MAP)
  525.     8,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x22,0x80,0x80,
  526. #else
  527.     8,      Y_INC,  LVDS_CTRL0_C0,      0x00,0xa3,0x23,0x80,0x80,
  528. #endif
  529. #else  
  530. 5, Y_INC, 0x57,0xa0,0x04,
  531.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  532. //7,      N_INC,  TC_DATA_PORT_96,    0xa2,0x60,0x63,0x9a, //enable global tcon
  533.     7,      N_INC,  TC_DATA_PORT_96,    0xa2,0x40,0x43,0x89, //enable global tcon
  534.     4,      N_INC,  TC_ADDR_PORT_95,    0x00,
  535.     4,      N_INC,  TC_DATA_PORT_96,    0xc2, 
  536. //#if(ANTI_FLICKER)
  537. //    5,      Y_INC,  ANTI_FLICKER_TH1_5B,0x08,0xa5,
  538.     5,      Y_INC,  0x5B,0x08,0xa5,
  539. //#endif
  541. #endif
  544.     0
  545. };
  547. // Be Careful !!
  548. // Display window setting in FreeV[] MUST follow the definition of
  549. // 1. DISP_WID and DISP_LEN
  550. // 2. DH_ACT_STA_POS and DH_ACT_END_POS
  551. // 3. DV_ACT_STA_POS and DV_ACT_END_POS
  552. // 4. Background window must be the same as active window.
  554. unsigned char code FreeV[]  =
  555. {
  556. #if (SPREAD_SPECTRUM)
  557.     4,  N_INC,  DPLL_CTRL_D0,       0x09,                                           // Enable DCLK
  558. #else
  559.     4,  N_INC,  DPLL_CTRL_D0,       0x11,                                           // Enable DCLK
  560. #endif
  562.     27, Y_INC,  VDIS_CTRL_20,       0x20 | DISP_BIT | DISPLAY_PORT,                 // Disable display timing
  563.                                     DISP_INV,
  564.                                     (STD_DH_TOTAL & 0xff), (STD_DH_TOTAL >> 8),     // DH_TOTAL
  565.                                     STD_HSYNC_WIDTH,                                // DH_HS_END
  566.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_BKGD_STA
  567.                                     (DH_ACT_STA_POS & 0xff), (DH_ACT_STA_POS >> 8), // DH_ACT_STA
  568.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_ACT_END
  569.                                     (DH_ACT_END_POS & 0xff), (DH_ACT_END_POS >> 8), // DH_BKGD_END
  570.                                     (STD_DV_TOTAL & 0xff), (STD_DV_TOTAL >> 8),     // DV_TOTAL
  571.                                     STD_VSYNC_LENGTH,                               // DV_VS_END
  572.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8) | AUTO_SWITCH, // DV_BKGD_STA
  573.                                     (DV_ACT_STA_POS & 0xff), (DV_ACT_STA_POS >> 8), // DV_ACT_STA
  574.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_ACT_END
  575.                                     (DV_ACT_END_POS & 0xff), (DV_ACT_END_POS >> 8), // DV_BKGD_END
  577.     4,  N_INC,  VDIS_CTRL_20,       0x23 | DISP_BIT | DISPLAY_PORT,                 // Enable free-run background
  579.     // Force display timing start
  580.     6,  Y_INC,  YUV2RGB_39,         0x00, 0x20 | DCLK_DELAY, 0x04 | DCLK_INV,
  581.     4,  N_INC,  DIS_TIMING0_3A,     0x00 | DCLK_DELAY,
  583.     4,  N_INC,  INT_FLD_DETECT_14,  0x00,
  584.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  586. 4,  N_INC,  SCALE_CTRL_15,      0x00,
  588.     4,  N_INC,  FILTER_CTRL0_1B,    0xc4,
  591.     0
  592. };
  594. unsigned char code OSD_PWUP_INI[]   =
  595. {
  596.     5,  Y_INC,  OSD_ROW_90,     0xaf,0x0f,
  597.     6,  N_INC,  OSD_DATA_92,    0x2c,0xf0,0xf0,
  599.     5,  Y_INC,  OSD_ROW_90,     0xaf,0x19,
  600.     5,  N_INC,  OSD_DATA_92,    0x00,0x88,
  602.     5,  Y_INC,  OSD_ROW_90,     0xaf,0x1c,  //set the window3 & window4 offset = 0
  603.     5,  N_INC,  OSD_DATA_92,    0x80,0x80,
  605.     0
  606. };
  609. ///////////////////////////////////////////////////////////////////////////
  610. //VGA mode detect range
  611. unsigned int code VGA_Mode[][6] =
  612. {
  613. //      HF_min, HF_max, VL_min, VL_max, HF_std, VS+1
  614.     {   0,      0,      0,      0,      0,      0       }, //00:No Signal
  616.     {   764,    806,    620,    636,    781,    2+1     }, //01:VGA [640/720]*350*50Hz
  617.     {   764,    806,    620,    636,    781,    2+1     }, //02:VGA [640/720]*400*50Hz
  618.     {   764,    806,    516,    532,    781,    2+1     }, //03:VGA [640/720]*350*60Hz
  619.     {   764,    806,    516,    532,    781,    2+1     }, //04:VGA [640/720]*400*60Hz
  621.     {   969,    1021,   431,    447,    990,    8+1     }, //05:640*400*56hz
  622.     {   768,    810,    440,    456,    785,    2+1     }, //06:640*350*70hz
  623.     {   764,    806,    440,    456,    781,    2+1     }, //07:720*350*70hz
  624.     {   764,    806,    440,    456,    781,    2+1     }, //08:640*400*70hz
  625.     {   764,    806,    440,    456,    781,    2+1     }, //09:700*400*70hz
  626.     {   635,    670,    436,    452,    649,    3+1     }, //10:640*350*85hz
  627.     {   635,    670,    436,    452,    649,    3+1     }, //11:640*400*85hz
  628.     {   634,    669,    437,    453,    648,    3+1     }, //12:720*400*85hz
  629.     {   764,    806,    620,    636,    781,    2+1     }, //13:640*480*50hz
  630.     {   764,    806,    516,    532,    781,    2+1     }, //14:640*480*60hz
  631.     {   687,    724,    516,    532,    702,    3+1     }, //15:640*480*66hz
  632.     {   635,    670,    511,    527,    649,    3+1     }, //16:640*480*72hz
  633.     {   641,    676,    495,    507,    655,    3+1     }, //17:640*480*75hz
  634.     {   556,    586,    500,    516,    568,    3+1     }, //18:640*480*85hz
  635.     {   684,    721,    616,    632,    699,    2+1     }, //19:800*600*56hz
  636.     {   635,    670,    619,    635,    649,    4+1     }, //20:800*600*60hz
  637.     {   492,    519,    721,    737,    503,    6+1     }, //21:800*600*66hz
  638.     {   500,    527,    657,    673,    511,    6+1     }, //22:800*600*72hz
  639.     {   513,    541,    616,    632,    524,    3+1     }, //23:800*600*75hz
  640.     {   448,    473,    622,    638,    458,    3+1     }, //24:800*600*85hz
  641.     {   483,    510,    658,    674,    494,    3+1     }, //25:832*624*75hz
  642.     {   497,    524,    797,    813,    508,    6+1     }, //26:1024*768*60hz
  643.     {   493,    520,    810,    826,    504,    6+1     }, //27:1024*768*59hz
  644.     {   445,    470,    807,    823,    455,    4+1     }, //28:1024*768*66hz
  645.     {   428,    449,    797,    813,    435,    6+1     }, //29:1024*768*70hz
  646.     {   399,    421,    795,    811,    408,    3+1     }, //30:1024*768*74hz
  647.     {   400,    422,    791,    807,    409,    3+1     }, //31:1024*768*75hz
  648.     {   350,    370,    799,    815,    358,    3+1     }, //32:1024*768*85hz
  649.     {   339,    358,    834,    850,    347,    8+1     }, //33:1024*800*84hz
  650.     {   356,    376,    891,    907,    364,    3+1     }, //34:1152*864*75hz
  651.     {   350,    370,    906,    922,    358,    3+1     }, //35:1152*870*75hz
  652.     {   389,    411,    928,    944,    398,    4+1     }, //36:1152*900*66hz
  653.     {   335,    354,    934,    950,    343,    8+1     }, //37:1152*900*76hz
  654.     {   401,    423,    991,    1007,   410,    3+1     }, //38:1280*960*60hz
  655.     {   280,    295,    1002,   1018,   286,    3+1     }, //39:1280*960*85hz
  656.     {   376,    396,    1057,   1073,   384,    3+1     }, //40:1280*1024*60hz
  657.     {   312,    329,    1060,   1076,   319,    3+1     }, //41:1280*1024*72hz
  658.     {   296,    313,    1057,   1073,   303,    8+1     }, //42:1280*1024*76hz
  659.     {   300,    317,    1057,   1073,   307,    3+1     }, //43:1280*1024*75hz
  660.     {   264,    279,    1063,   1079,   270,    3+1     }, //44:1280*1024*85hz
  661.     {   321,    339,    1241,   1257,   328,    3+1     }, //45:1600*1200*60hz
  663.     {   0,      0,      0,      0,      0,      0       }, //46:Mode reserved 00
  664.     {   0,      0,      0,      0,      0,      0       }, //47:Mode reserved 01
  665.     {   0,      0,      0,      0,      0,      0       }, //48:Mode reserved 02
  666.     {   0,      0,      0,      0,      0,      0       }, //49:Mode reserved 03
  668.     {   642,    1230,   418,    497,    0,      2+1     }, //50:NewMode720x400
  669.     {   535,    1025,   498,    637,    0,      2+1     }, //51:NewMode640x480
  670.     {   428,    820,    618,    785,    0,      2+1     }, //52:NewMode800x600
  671.     {   334,    641,    786,    881,    0,      2+1     }, //53:NewMode1024x768
  672.     {   297,    570,    882,    917,    0,      2+1     }, //54:NewMode1152x864
  673.     {   285,    547,    918,    977,    0,      2+1     }, //55:NewMode1152x900
  674.     {   267,    513,    978,    1041,   0,      2+1     }, //56:NewMode1280x960
  675.     {   251,    481,    1042,   1217,   0,      2+1     }, //57:NewMode1280x1024
  676.     {   292,    559,    1218,   1328,   0,      2+1     }, //58:NewMode1600x1200
  677. };
  679. unsigned int code Mode_Preset[][5]   =
  680. {
  681.     //  DH_TOTAL    DH_ACT_WID  DV_ACT_LEN      DCLK_M/N    IVS_DELAY
  682.     {   1408,       1280,       1024,           0,          0       }, //00:No Signal
  684.     //  VGA confused mode
  685.     {   1408,       1280,       1024,           0,          63      }, //01:VGA [640/720]*350*50Hz
  686.     {   1408,       1280,       1024,           0,          31      }, //02:VGA [640/720]*400*50Hz
  687.     {   1408,       1280,       1024,           0,          63      }, //03:VGA [640/720]*350*60Hz
  688.     {   1408,       1280,       1024,           0,          31      }, //04:VGA [640/720]*400*60Hz
  690.     //  Standard mode
  691.     {   1408,       1280,       1024,           0,          7       }, //05:640*400*56hz
  692.     {   1408,       1280,       1024,           0,          7       }, //06:640*350*70hz
  693.     {   1408,       1280,       1024,           0,          7       }, //07:720*350*70hz
  694.     {   1408,       1280,       1024,           0,          7       }, //08:640*400*70hz
  695.     {   1408,       1280,       1024,           0,          7       }, //09:700*400*70hz
  696.     {   1408,       1280,       896,            0,          7       }, //10:640*350*85hz
  697.     {   1408,       1280,       1024,           0,          7       }, //11:640*400*85hz
  698.     {   1408,       1280,       1024,           0,          7       }, //12:720*400*85hz
  699.     {   1408,       1280,       1024,           0,          31      }, //13:640*480*50hz
  700.     {   1408,       1280,       1024,           0,          7       }, //14:640*480*60hz
  701.     {   1408,       1280,       1024,           0,          7       }, //15:640*480*66hz
  702.     {   1408,       1280,       1024,           0,          7       }, //16:640*480*72hz
  703.     {   1408,       1280,       1024,           0,          3       }, //17:640*480*75hz
  704.     {   1408,       1280,       1024,           0,          7       }, //18:640*480*85hz
  705.     {   1408,       1280,       1024,           0,          3       }, //19:800*600*56hz
  706.     {   1408,       1280,       1024,           0,          7       }, //20:800*600*60hz
  707.     {   1408,       1280,       1024,           0,          7       }, //21:800*600*66hz
  708.     {   1408,       1280,       1024,           0,          7       }, //22:800*600*72hz
  709.     {   1408,       1280,       1024,           0,          3       }, //23:800*600*75hz
  710.     {   1408,       1280,       1024,           0,          7       }, //24:800*600*85hz
  711.     {   1408,       1280,       1024,           0,          7       }, //25:832*624*75hz
  712.     {   1424,       1280,       1024,           0,          7       }, //26:1024*768*60hz
  713.     {   1424,       1280,       1024,           0,          7       }, //27:1024*768*59hz
  714.     {   1408,       1280,       1024,           0,          7       }, //28:1024*768*66hz
  715.     {   1408,       1280,       1024,           0,          7       }, //29:1024*768*70hz
  716.     {   1408,       1280,       1024,           0,          7       }, //30:1024*768*74hz
  717.     {   1408,       1280,       1024,           0,          7       }, //31:1024*768*75hz
  718.     {   1408,       1280,       1024,           0,          7       }, //32:1024*768*85hz
  719.     {   1408,       1280,       1024,           0,          7       }, //33:1024*800*84hz
  720.     {   1408,       1280,       1024,           0,          7       }, //34:1152*864*75hz
  721.     {   1408,       1280,       1024,           0,          7       }, //35:1152*870*75hz
  722.     {   1408,       1280,       1024,           0,          7       }, //36:1152*900*66hz
  723.     {   1408,       1280,       1024,           0,          7       }, //37:1152*900*76hz
  724.     {   1408,       1280,       1024,           0,          7       }, //38:1280*960*60hz
  725.     {   1408,       1280,       1024,           0,          7       }, //39:1280*960*85hz
  726.     {   1408,       1280,       1024,           0,          7       }, //40:1280*1024*60hz
  727.     {   1408,       1280,       1024,           0,          7       }, //41:1280*1024*72hz
  728.     {   1408,       1280,       1024,           0,          7       }, //42:1280*1024*76hz
  729.     {   1408,       1280,       1024,           0,          7       }, //43:1280*1024*75hz
  730.     {   1408,       1280,       1024,           0,          7       }, //44:1280*1024*85hz
  731.     {   1408,       1280,       1024,           0,          7       }, //45:1600*1200*60hz
  733.     //  Reserved mode
  734.     {   1408,       1280,       1024,           0,          0       }, //46:Mode reserved 00
  735.     {   1408,       1280,       1024,           0,          0       }, //47:Mode reserved 01
  736.     {   1408,       1280,       1024,           0,          0       }, //48:Mode reserved 02
  737.     {   1408,       1280,       1024,           0,          0       }, //49:Mode reserved 03
  739.     //  Unknown user mode
  740.     {   1408,       1280,       1024,           0,          3       }, //50:NewMode720x400
  741.     {   1408,       1280,       1024,           0,          3       }, //51:NewMode640x480
  742.     {   1408,       1280,       1024,           0,          3       }, //52:NewMode800x600
  743.     {   1408,       1280,       1024,           0,          3       }, //53:NewMode1024x768
  744.     {   1408,       1280,       1024,           0,          3       }, //54:NewMode1152x864
  745.     {   1408,       1280,       1024,           0,          3       }, //55:NewMode1152x900
  746.     {   1408,       1280,       1024,           0,          3       }, //56:NewMode1280x960
  747.     {   1408,       1280,       1024,           0,          3       }, //57:NewMode1280x1024
  748.     {   1408,       1280,       1024,           0,          3       }, //58:NewMode1600x1200
  749.     
  750.     //  Safe display mode
  751.     {   1408,       1280,       1024,           0,          3       }, //59:Undefined SU mode
  752.     {   1408,       1280,       1024,           0,          3       }, //60:Undefined SD mode
  753. };
  755. ///////////////////////////////////////////////////////////////////////////////
  756. //Video Setting
  757. #if (VIDEO_CHIP == VDC_NONE)
  758. // No Video Decoder
  759. unsigned char code RTD_VIDEO_60[]   = { 0 };
  760. unsigned char code RTD_VIDEO_50[]   = { 0 };
  762. #else
  764. #if (VIDEO_CHIP == VDC_SAA7114 || VIDEO_CHIP == VDC_SAA7115 || VIDEO_CHIP == VDC_SAA7118)
  766. #define H_60    0x91//0x70    // For SAA7114/7118
  767. #define H_50    0x91//0x7c    // For SAA7114/7118
  769. #else
  771. #define H_60    0x56    // For SAA7111A
  772. #define H_50    0x5e    // For SAA7111A
  774. #endif
  776. unsigned char code RTD_VIDEO_60[]   =
  777. {
  778.     11, Y_INC,  IPH_ACT_STA_06,     H_60, 0x00, 0xb8, 0x02,
  779.                                     0x14, 0x00, 0xed, 0x00,
  781.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x40, 0x3b, 0x30,
  783.     4,  N_INC,  FS_FT_DELAY_1E,     0x1a,
  784.     
  785.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0xed, 0x00,
  787.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  789.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  791.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  793. #if (SPREAD_SPECTRUM)
  794.     8,  Y_INC,  DPLL_CTRL_D0,       0x09, 0x9a, 0x52, 0x0a, 0xf7,
  795. #else    
  796.     8,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x9a, 0x52, 0x2f, 0x06,
  797. #endif
  799. //  6,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x44, 0x47,
  801.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  802.                                     DISP_INV,
  803.                                     0x7c, 0x05,
  804.                                     0x10,
  805.                                     0x20, 0x00,
  806.                                     0x20, 0x00,
  807.                                     0x20, 0x05,
  808.                                     0x20, 0x05,
  809.                                     0x80, 0x04,
  810.                                     0x03,
  811.                                     0x0f, 0x00,
  812.                                     0x0f, 0x00,
  813.                                     0x0f, 0x04,
  814.                                     0x0f, 0x04,
  815.                                     0x13, 0x20,
  817.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  819.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  821.     0
  822. };
  824. unsigned char code RTD_VIDEO_50[]=
  825. {
  826.     11, Y_INC,  IPH_ACT_STA_06,     H_50, 0x00, 0xb8, 0x02,
  827.                                     0x18, 0x00, 0x1a, 0x01,
  829.     10, Y_INC,  INT_FLD_DETECT_14,  0x14, 0x03, 0x33, 0x8b, 0x80, 0x46, 0x30,
  831.     4,  N_INC,  FS_FT_DELAY_1E,     0x1a,
  832.     
  833.     7,  Y_INC,  DRW_BSU_40,         0xb8, 0x02, 0x1a, 0x01,
  835.     4,  N_INC,  OP_CRC_CTRL_68,     0x48,
  837.     4,  N_INC,  SD_CTRL_70,         0x00 | VIDEO_ICLK_DELAY,
  839.     5,  Y_INC,  IVS_DELAY_8C,       0x00, 0x00,
  841. #if (SPREAD_SPECTRUM)
  842.     8,  Y_INC,  DPLL_CTRL_D0,       0x09, 0x82, 0x52, 0x0b, 0xf7,
  843. #else    
  844.     8,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x82, 0x52, 0x2f, 0x06,
  845. #endif
  847. //  6,  Y_INC,  DPLL_CTRL_D0,       0x11, 0x75, 0x07,
  849.     29, Y_INC,  VDIS_CTRL_20,       0x28 | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  850.                                     DISP_INV,
  851.                                     0x96, 0x05,
  852.                                     0x10,
  853.                                     0x20, 0x00,
  854.                                     0x20, 0x00,
  855.                                     0x20, 0x05,
  856.                                     0x20, 0x05,
  857.                                     0x80, 0x04,
  858.                                     0x03,
  859.                                     0x0d, 0x00,
  860.                                     0x0d, 0x00,
  861.                                     0x0d, 0x04,
  862.                                     0x0d, 0x04,
  863.                                     0x17, 0x20,
  865.     4,  N_INC,  VDIS_CTRL_20,       0x2b | DISP_BIT | DISPLAY_PORT | DHS_MASK,
  867.     5,  Y_INC,  VGIP_CTRL_04,       0x0d, 0x00 | VIDEO_LATCH,
  869.     0
  870. };
  872. #endif
  874. #else 
  876. extern unsigned char code RTD_PWUP_INI[];
  877. extern unsigned char code RTD_DDC_TABLE[];
  878. extern unsigned char code RTD_IO_INI[];
  880. extern unsigned char code FreeV[];
  881. extern unsigned char code OSD_PWUP_INI[];
  883. extern unsigned int code VGA_Mode[][6];
  884. extern unsigned int code Mode_Preset[][5];
  886. extern unsigned char code RTD_VIDEO_60[];
  887. extern unsigned char code RTD_VIDEO_50[];
  889. #endif