test_for_FPGA1.asv
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上传日期:2013-06-30
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文件大小:1k
- clear
- %k=1--------------------------------
- %a=[00 00 00 00 00 00 00 04];
- %b=[20 20 28 28 20 24 28 28];
- %d12=16;d32=8;d31=8;
- %k=2---------------------------------
- %a=[00 00 08 20 00 00 08 04];
- %b=[16 16 16 16 20 28 20 28];
- %d12=8;d32=0;d31=8;
- %k=3---------------------------------
- %a=[00 20 08 12 00 20 00 08];
- %b=[16 16 20 20 16 16 20 20];
- %d12=8;d32=8;d31=0;
- %k=4---------------------------------
- a=[20 12 20 16 20 12 28 08];
- b=[04 04 12 12 04 12 16 16];
- d12=0;d32=0;d31=0;
- d22=d12;
- d72=d12;
- d82=d12;
- d42=d32;
- d52=d32;
- d62=d32;
- d41=d31;
- d51=d31;
- d61=d31;
- a=a([8,7,6,5,4,3,2,1]);
- b=b([8,7,6,5,4,3,2,1]);
- l(1)=max([...
- (a(1)+d12+b(5)),(a(2)+d22+b(1)),...
- (a(3)+d32+b(2)),(a(4)+d42+b(6)),...
- (a(5)+d52+b(7)),(a(6)+d62+b(3)),...
- (a(7)+d72+b(4)),(a(8)+d82+b(8))...
- ])-max([...
- (a(1)+b(1)),(a(2)+b(5)),...
- (a(3)+d31+b(6)),(a(4)+d41+b(2)),...
- (a(5)+d51+b(3)),(a(6)+d61+b(7)),...
- (a(7)+b(8)),(a(8)+b(4))...
- ])