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regmap_8202.h
资源名称：8202s.rar　[点击查看]
上传用户：poi891205
上传日期：2013-07-15
资源大小：9745k
文件大小：48k
源码类别：

DVD

开发平台：

C/C++

regmap_8202.h：源码内容
  1. #ifndef __REGMAP_8202_H
  2. #define __REGMAP_8202_H
  4. /*
  5. ** FILE
  6. ** regmap.h
  7. **
  8. ** DESCRIPTION
  9. ** define register-file structure.
  10. **
  11. ** NOTE:
  12. ** specific for sphe8202
  13. */
  15. #include "types.h"
  16. #include "dmabuf.h"
  18. /*
  19. ** TYPE
  20. ** RegisterFile
  21. */
  22. typedef struct
  23. {
  24.   // GROUP 0: Chip Information
  25.   UINT32 stamp;                                 // 00    0      (0000) $bffe8000
  26.   UINT32 emulation;                             // 01    1      (0004)
  27.   UINT32 reset;                                 // 02    2      (0008)
  28.   UINT32 reset2;                                // 03    3      (000c)
  29.   UINT32 pad_ctrl;                              // 04    4      (0010)
  30.   UINT32 sdram_clko_cfg;                        // 05    5      (0014)
  31.   UINT32 sdram_clki_cfg;                        // 06    6      (0018)
  32.   UINT32 sdram_clki_dly_cfg;                    // 07    7      (001c)
  33.   UINT32 clk_mon_sel;                           // 08    8      (0020)
  34.   UINT32 clk_mon_result;                        // 09    9      (0024)
  35.   UINT32 clken0;                                // 0a   10      (0028)
  36.   UINT32 clken1;                                // 0b   11      (002c)
  37.   UINT32 gclken0;                               // 0c   12      (0030)
  38.   UINT32 gclken1;                               // 0d   13      (0034)
  39.   UINT32 sysclk_div_sel;                        // 0e   14      (0038)
  40.   UINT32 sysclk_sel;                            // 0f   15      (003c)
  41.   UINT32 pllv_cfg;                              // 10   16      (0040)
  42.   UINT32 sft_cfg0;                              // 11   17      (0044)
  43.   UINT32 sft_cfg1;                              // 12   18      (0048)
  44.   UINT32 sft_cfg2;                              // 13   19      (004c)
  45.   UINT32 sft_cfg3;                              // 14   20      (0050)
  46.   UINT32 sft_cfg4;                              // 15   21      (0054)
  47.   UINT32 sft_cfg5;                              // 16   22      (0058)
  48.   UINT32 sft_cfg6;                              // 17   23      (005c)
  49.   UINT32 sft_cfg7;                              // 18   24      (0060)
  50.   UINT32 sft_cfg8;                              // 19   25      (0064)
  51.   UINT32 hw_bo;                                 // 1a   26      (0068)
  52.   UINT32 hw_cfg;                                // 1b   27      (006c)
  53.   UINT32 hw_cfg_chg;                            // 1c   28      (0070)
  54.   UINT32 sft_cfg9;                              // 1d   29      (0074)
  55.   UINT32 sft_cfga;                              // 1e   30      (0078)
  56.   UINT32 g0_reserved_1[1];                      // 1f   31~  31 (007c)
  58.   // GROUP 1: Timers
  59.   UINT32 stc_15_0;                              // 00   32      (0080) $bffe8080
  60.   UINT32 stc_31_16;                             // 01   33      (0084)
  61.   UINT32 stc_32;                                // 02   34      (0088)
  62.   UINT32 stc_divisor;                           // 03   35      (008c)
  63.   UINT32 rtc_15_0;                              // 04   36      (0090)
  64.   UINT32 rtc_31_16;                             // 05   37      (0094)
  65.   UINT32 rtc_divisor;                           // 06   38      (0098)
  66.   UINT32 stc_config;                            // 07   39      (009c)
  67.   UINT32 timer0_ctrl;                           // 08   40      (00a0)
  68.   UINT32 timer0_cnt;                            // 09   41      (00a4)
  69.   UINT32 timer1_ctrl;                           // 0a   42      (00a8)
  70.   UINT32 timer1_cnt;                            // 0b   43      (00ac)
  71.   UINT32 timerw_ctrl;                           // 0c   44      (00b0)
  72.   UINT32 timerw_cnt;                            // 0d   45      (00b4)
  73.   UINT32 g1_unused_1[2];                        // 0e   46~  47 (00b8)
  74.   UINT32 timer2_ctrl;                           // 10   48      (00c0)
  75.   UINT32 timer2_divisor;                        // 11   49      (00c4)
  76.   UINT32 timer2_reload;                         // 12   50      (00c8)
  77.   UINT32 timer2_cnt;                            // 13   51      (00cc)
  78.   UINT32 timer3_ctrl;                           // 14   52      (00d0)
  79.   UINT32 timer3_divisor;                        // 15   53      (00d4)
  80.   UINT32 timer3_reload;                         // 16   54      (00d8)
  81.   UINT32 timer3_cnt;                            // 17   55      (00dc)
  82.   UINT32 stcl_0;                                // 18   56      (00e0)
  83.   UINT32 stcl_1;                                // 19   57      (00e4)
  84.   UINT32 stcl_2;                                // 1a   58      (00e8)
  85.   UINT32 atc_0;                                 // 1b   59      (00ec)
  86.   UINT32 atc_1;                                 // 1c   60      (00f0)
  87.   UINT32 atc_2;                                 // 1d   61      (00f4)
  88.   UINT32 g1_reserved[2];                        // 1e   62~  63 (00f8)
  90.   // GROUP 2: RISC interface
  91.   UINT32 intr_mask;                             // 00   64      (0100) $bffe8100
  92.   UINT32 intr_flag;                             // 01   65      (0104)
  93.   UINT32 intr_masked_flag;                      // 02   66      (0108)
  94.   UINT32 intr_clear;                            // 03   67      (010c)
  95.   UINT32 intr_polarity;                         // 04   68      (0110)
  96.   UINT32 intr_edge;                             // 05   69      (0114)
  97.   UINT32 intr1_mask;                            // 06   70      (0118)
  98.   UINT32 intr1_flag;                            // 07   71      (011c)
  99.   UINT32 intr1_masked_flag;                     // 08   72      (0120)
  100.   UINT32 intr1_clear;                           // 09   73      (0124)
  101.   UINT32 intr1_polarity;                        // 0a   74      (0128)
  102.   UINT32 intr1_edge;                            // 0b   75      (012c)
  103.   UINT32 lbc_control;                           // 0c   76      (0130)
  104.   UINT32 lbc_watchdog;                          // 0d   77      (0134)
  105.   UINT32 rec_start;                             // 0e   78      (0138)
  106.   UINT32 rec_end;                               // 0f   79      (013c)
  107.   UINT32 rec_l_m;                               // 10   80      (0140)
  108.   UINT32 g2_reserved[13];                       // 11   81~  93 (0144)
  109.   UINT32 ri_misc_b0;                            // 1e   94      (0178)
  110.   UINT32 ri_misc_b1;                            // 1f   95      (017c)
  112.   // GROUP 3: Video bitstream parameters
  113.   UINT32 seq_ext;                               // 00   96      (0180) $bffe8180
  114.   UINT32 h_size;                                // 01   97      (0184)
  115.   UINT32 v_size;                                // 02   98      (0188)
  116.   UINT32 g3_unused;                             // 03   99      (018c)
  117.   UINT32 pic_coding_type;                       // 04  100      (0190)
  118.   UINT32 pic_f_code;                            // 05  101      (0194)
  119.   UINT32 pic_coding_ext0;                       // 06  102      (0198)
  120.   UINT32 pic_coding_ext1;                       // 07  103      (019c)
  121.   UINT32 pic_start;                             // 08  104      (01a0)
  122.   UINT32 dis_pic_id;                            // 09  105      (01a4)
  123.   UINT32 dis_seq_tag;                           // 0a  106      (01a8)
  124.   UINT32 g3_reserved[21];                       // 0b  107~ 127 (01ac)
  126.   // GROUP 4: VLD parameters
  127.   UINT32 vld_ctrl;                              // 00  128      (0200) $bffe8200
  128.   UINT32 vld_status;                            // 01  129      (0204)
  129.   UINT32 vld_decode_time;                       // 02  130      (0208)
  130.   UINT32 vld_int_trb_trd;                             // 03  131      (020c)
  131.   UINT32 vld_mon0;                              // 04  132      (0210)
  132.   UINT32 vld_mon1;                              // 05  133      (0214)
  133.   UINT32 vld_mon2;                              // 06  134      (0218)
  134.   UINT32 vld_mon3;                              // 07  135      (021c)
  135.   UINT32 jpeg_control;                          // 08  136      (0220)
  136.   UINT32 jpeg_write_addr;                       // 09  137      (0224)
  137.   UINT32 jpeg_write_data;                       // 0a  138      (0228)
  138.   UINT32 jpeg_read_addr;                        // 0b  139      (022c)
  139.   UINT32 jpeg_read_data;                        // 0c  140      (0230)
  140.   UINT32 error_mb_threshold;                    // 0d  141      (0234)
  141.   UINT32 vld_config;                            // 0e  142      (0238)
  142.   UINT32 vld_trb_trd;                           // 0f  143      (023c)
  143.   UINT32 vld_trb_trd_ext;                       // 10  144      (0240)
  144.   UINT32 vld_2trbp_2dp;                         // 11  145      (0244)
  145.   UINT32 vld_2trbm_2dm;                         // 12  146      (0248)
  146.   UINT32 vld_packet_header;                     // 13  147      (024c)
  147.   UINT32 vld_vol_header;                        // 14  148      (0250)
  148.   UINT32 vld_vop_header;                        // 15  149      (0254)
  149.   UINT32 vld_mp4_misc;                         // 16  150      (0258)
  150.   UINT32 g4_reserved[8];                        // 17  151~ 158 (025c)
  151.   UINT32 vld_gob_num;                           // 1f  159      (027c)
  153.   // GROUP 5: MC configuration zero registers
  154.   UINT32 mc_config;                             // 00  160      (0280) $bffe8280
  155.   UINT32 ref0_luma;                             // 01  161      (0284)
  156.   UINT32 ref0_chroma;                           // 02  162      (0288)
  157.   UINT32 ref1_luma;                             // 03  163      (028c)
  158.   UINT32 ref1_chroma;                           // 04  164      (0290)
  159.   UINT32 bidir_luma;                            // 05  165      (0294)
  160.   UINT32 bidir_chroma;                          // 06  166      (0298)
  161.   UINT32 g5_reserved_0[5];                      // 07  167~ 171 (029c)
  162.   UINT32 divx_mw_pad;                           // 0c  172      (02b0)
  163.   UINT32 vop_round_type;                        // 0d  173      (02b4)
  164.   UINT32 mc_time_ctrl;                     // 0e  174 (02b8)
  165.   UINT32 qpel_gmc_ctrl;                     // 0f  175 (02bc)
  166.   UINT32 g5_reserved_1[8];                      // 10  176~ 183 (02c0)
  167.   UINT32 mc_spare_0;                            // 18  184      (02e0)
  168.   UINT32 mc_compress;                           // 19  185      (02e4)
  169.   UINT32 mc_pardec_start;                       // 1a  186      (02e8)
  170.   UINT32 mc_pardec_end;                         // 1b  187      (02ec)
  171.   UINT32 mc_mbwidth;                            // 1c  188      (02f0)
  172.   UINT32 mc_pardec_en;                          // 1d  189      (02f4)
  173.   UINT32 mc_spare_6;                            // 1e  190      (02f8)
  174.   UINT32 mc_spare_7;                            // 1f  191      (02fc)
  176.   // GROUP 6: SDRAM control
  177.   UINT32 sdctrl_cfg0;                           // 00  192      (0300) $bffe8300
  178.   UINT32 sdctrl_cfg1;                           // 01  193      (0304)
  179.   UINT32 sdctrl_cfg2;                           // 02  194      (0308)
  180.   UINT32 sdctrl_mrs;                            // 03  195      (030c)
  181.   UINT32 sdctrl_sref_cfg;                       // 04  196      (0310)
  182.   UINT32 sdctrl_cfg3;                           // 05  197      (0314)
  183.   UINT32 sdctrl_data_mon_st;                    // 06  198      (0318)
  184.   UINT32 sdctrl_data_cyc_l;                     // 07  199      (031c)
  185.   UINT32 sdctrl_data_cyc_h;                     // 08  200      (0320)
  186.   UINT32 sdctrl_data_cnt_l;                     // 09  201      (0324)
  187.   UINT32 sdctrl_data_cnt_h;                     // 0a  202      (0328)
  188.   UINT32 sdctrl_gclk_dis;                       // 0b  203      (032c)
  189.   UINT32 sdctrl_aref1_cfg;                      // 0c  204      (0330)
  190.   UINT32 sdctrl_int;                            // 0d  205      (0334)
  191.   UINT32 sdctrl_int_mask;                       // 0e  206      (0338)
  192.   UINT32 sdctrl_int_status;                     // 0f  207      (033c)
  193.   UINT32 sdctrl_lmem_base;                      // 10  208      (0340)
  194.   UINT32 sdctrl_lmem_row_st;                    // 11  209      (0344)
  195.   UINT32 g6_unused_0;                           // 12  210      (0348)
  196.   UINT32 sdctrl_cfg4;                           // 13  211      (034c)
  197.   UINT32 sdctrl_mon[10];                        // 14  212~ 221 (0350)
  198.   UINT32 sdctrl_misc_b0;                        // 1e  222      (0378)
  199.   UINT32 sdctrl_misc_b1;                        // 1f  223      (037c)
  201.   // GROUP 7: VPP Control
  202.   UINT32 dis_x_start;                           // 00  224      (0380) $bffe8380
  203.   UINT32 dis_y_start;                           // 01  225      (0384)
  204.   UINT32 dis_x_size;                            // 02  226      (0388)
  205.   UINT32 dis_y_size;                            // 03  227      (038c)
  206.   UINT32 v_offset;                              // 04  228      (0390)
  207.   UINT32 h_offset;                              // 05  229      (0394)
  208.   UINT32 vpp_bg_y;                              // 06  230      (0398)
  209.   UINT32 vpp_bg_cb_cr;                          // 07  231      (039c)
  210.   UINT32 v_filter0_setup;                       // 08  232      (03a0)
  211.   UINT32 v_filter1_setup;                       // 09  233      (03a4)
  212.   UINT32 h_filter_setup;                        // 0a  234      (03a8)
  213.   UINT32 vpp_config;                            // 0b  235      (03ac)
  214.   UINT32 vpp_config1;                           // 0c  236      (03b0)
  215.   UINT32 ds_field_config;                       // 0d  237      (03b4)
  216.   UINT32 dip_config;                            // 0e  238      (03b8)
  217.   UINT32 dip_param;                             // 0f  239      (03bc)
  218.   UINT32 dip_mv_ptr;                            // 10  240      (03c0)
  219.   UINT32 vppref0_luma;                          // 11  241      (03c4)
  220.   UINT32 vppref0_chroma;                        // 12  242      (03c8)
  221.   UINT32 vppref1_luma;                          // 13  243      (03cc)
  222.   UINT32 vppref1_chroma;                        // 14  244      (03d0)
  223.   UINT32 vppbidir_luma;                         // 15  245      (03d4)
  224.   UINT32 vppbidir_chroma;                       // 16  246      (03d8)
  225.   UINT32 dip_ref_base;                          // 17  247      (03dc)
  226.   UINT32 dip_param_threshold;                   // 18  248      (03e0)
  227.   UINT32 dip_param_fading;                      // 19  249      (03e4)
  228.   UINT32 vpp_act_region_top;                    // 1a  250      (03e8)
  229.   UINT32 vpp_act_region_bottom;                 // 1b  251      (03ec)
  230.   UINT32 vpp_spare_0;                           // 1c  252      (03f0)
  231.   UINT32 vpp_clut_ay;                           // 1d  253      (03f4)
  232.   UINT32 vpp_clut_uv;                           // 1e  254      (03f8)
  233.   UINT32 vpp_spare_1;                           // 1f  255      (03fc)
  234.   /*
  235.   UINT32 vpp_config2;                           // 1c  252      (03f0)
  236.   UINT32 vpp_clut_ay;                           // 1d  253      (03f4)
  237.   UINT32 vpp_clut_uv;                           // 1e  254      (03f8)
  238.   UINT32 vpp_video_in;                          // 1f  255      (03fc)
  239.   */
  241.   // GROUP 8: TV0
  242.   UINT32 tv_mode[6];                            // 00  256~ 261 (0400) $bffe8400
  243.   UINT32 tv_subc_f[2];                          // 06  262~ 263 (0418)
  244.   UINT32 tv_subc_p;                             // 08  264      (0420)
  245.   UINT32 tv_line_t[2];                          // 09  265~ 266 (0424)
  246.   UINT32 tv_line_b[2];                          // 0b  267~ 268 (042c)
  247.   UINT32 tv_cc_t;                               // 0d  269      (0434)
  248.   UINT32 tv_cc_b;                               // 0e  270      (0438)
  249.   UINT32 tv_cgms[2];                            // 0f  271~ 272 (043c)
  250.   UINT32 tv_id_status;                          // 11  273      (0444)
  251.   UINT32 tv_dac[2];                             // 12  274~ 275 (0448)
  252.   UINT32 tv_misc[12];                           // 14  276~ 287 (0450)
  254.   // GROUP 9: DSP24
  255.   UINT32 dsp24_control;                         // 00  288      (0480) $bffe8480
  256.   UINT32 dsp3dbg_mode;                          // 01  289      (0484)
  257.   UINT32 dsp3dbg_break;                         // 02  290      (0488)
  258.   UINT32 dsp3dbg_addr;                          // 03  291      (048c)
  259.   UINT32 dsp3dbg_step;                          // 04  292      (0490)
  260.   UINT32 dsp3dbg_rd_l;                          // 05  293      (0494)
  261.   UINT32 dsp3dbg_rd_h;                          // 06  294      (0498)
  262.   UINT32 dsp3dbg_wr_l;                          // 07  295      (049c)
  263.   UINT32 dsp3dbg_wr_h;                          // 08  296      (04a0)
  264.   UINT32 dsp3dbg_pc;                            // 09  297      (04a4)
  265.   UINT32 rom_l;                                 // 0a  298      (04a8)
  266.   UINT32 rom_h;                                 // 0b  299      (04ac)
  267.   UINT32 dsp24ya;                               // 0c  300      (04b0)
  268.   UINT32 pcmya;                                 // 0d  301      (04b4)
  269.   UINT32 audya;                                 // 0e  302      (04b8)
  270.   UINT32 g9_reserved;                           // 0f  303      (04bc)
  271.   UINT32 dsp24_port[16];                        // 10  304~ 319 (04c0)
  273.   // GROUP 10: OSD control
  274.   UINT32 osd_tv_std;                            // 00  320      (0500) $bffe8500
  275.   UINT32 osd_tv_out;                            // 01  321      (0504)
  276.   UINT32 osd_mixer;                             // 02  322      (0508)
  277.   UINT32 osd_display_status;                    // 03  323      (050c)
  278.   UINT32 osd_en;                                // 04  324      (0510)
  279.   UINT32 osd_tlink_addr;                        // 05  325      (0514)
  280.   UINT32 osd_blink_addr;                        // 06  326      (0518)
  281.   UINT32 y_clip;                                // 07  327      (051c)
  282.   UINT32 cb_clip;                               // 08  328      (0520)
  283.   UINT32 osd_base_addr;                         // 09  329      (0524)
  284.   UINT32 osd_mode[12];                          // 0a  330~ 341 (0528)
  286.   UINT32 g10_reserved[10];                      // 16  342~ 351 (0558)
  288.   // GROUP 11: Graphic control
  289.   UINT32 graph_mode;                            // 00  352      (0580) $bffe8580
  290.   UINT32 graph_status;                          // 01  353      (0584)
  291.   UINT32 dma_mode;                              // 02  354      (0588)
  292.   UINT32 dma_xaddr;                             // 03  355      (058c)
  293.   UINT32 dma_yaddr;                             // 04  356      (0590)
  294.   UINT32 dma_done;                              // 05  357      (0594)
  295.   UINT32 g11_reserved[26];                      // 06  358~ 383 (0598)
  297.   // GROUP 12: HOST
  298.   UINT32 g12_dvddsp_vy;                         // 00  384      (0600) $bffe8600
  299.   UINT32 g12_dvddsp_vx;                         // 01  385      (0604)
  300.   UINT32 dvddsp_function;                       // 02  386      (0608)
  301.   UINT32 dvddsp_ata_config;                     // 03  387      (060c)
  302.   UINT32 dvddsp_blocksize;                      // 04  388      (0610)
  303.   UINT32 dvddsp_blocklength;                    // 05  389      (0614)
  304.   UINT32 g12_dvddsp_ry;                         // 06  390      (0618)
  305.   UINT32 dvddsp_rx;                             // 07  391      (061c)
  306.   UINT32 dvddsp_public;                         // 08  392      (0620)
  307.   UINT32 dvddsp_ude_config;                     // 09  393      (0624)
  308.   UINT32 dvddsp_ata_pio_cycle;                  // 0a  394      (0628)
  309.   UINT32 dvddsp_ata_udma_cycle;                 // 0b  395      (062c)
  310.   UINT32 g12_reserved[4];                       // 0c  396~ 399 (0630)
  311.   UINT32 dvddsp_mon[4];                         // 10  400~ 403 (0640)
  312.   UINT32 g12_reserved1[12];                     // 14  404~ 415 (0650)
  314.   // GROUP 13: CSS
  315.   UINT32 css_tk0;                               // 00  416      (0680) $bffe8680
  316.   UINT32 css_tk1;                               // 01  417      (0684)
  317.   UINT32 css_tk2;                               // 02  418      (0688)
  318.   UINT32 css_tk3;                               // 03  419      (068c)
  319.   UINT32 css_tbyte;                             // 04  420      (0690)
  320.   UINT32 css_public;                            // 05  421      (0694)
  321.   UINT32 css_config;                            // 06  422      (0698)
  322.   UINT32 css_l0;                                // 07  423      (069c)
  323.   UINT32 css_l1;                                // 08  424      (06a0)
  324.   UINT32 css_r0;                                // 09  425      (06a4)
  325.   UINT32 css_r1;                                // 0a  426      (06a8)
  326.   UINT32 cppm_aukey3;                           // 0b  427      (06ac)
  327.   UINT32 cppm_aukey2;                           // 0c  428      (06b0)
  328.   UINT32 cppm_aukey1;                           // 0d  429      (06b4)
  329.   UINT32 cppm_aukey0;                           // 0e  430      (06b8)
  330.   UINT32 g13_reserved[17];                      // 0f  431~ 447 (06bc)
  332.   // GROUP 14:  IOP
  333.   UINT32 iop_control;                           // 00  448      (0700) $bffe8700
  334.   UINT32 iop_status;                            // 01  449      (0704)
  335.   UINT32 iop_bp;                                // 02  450      (0708)
  336.   UINT32 iop_regsel;                            // 03  451      (070c)
  337.   UINT32 iop_regout;                            // 04  452      (0710)
  338.   UINT32 iop_memlimit;                          // 05  453      (0714)
  339.   UINT32 g14_reserved[2];                       // 06  454~ 455 (0718)
  340.   UINT32 iop_data[8];                           // 08  456~ 463 (0720)
  341.   UINT32 g14_reserved1[16];                     // 10  464~ 479 (0740)
  343.   // GROUP 15:  SUP
  344.   UINT32 sup_fst_cmd_addr;                      // 00  480      (0780) $bffe8780
  345.   UINT32 sup_snd_cmd_addr;                      // 01  481      (0784)
  346.   UINT32 sup_h_size;                            // 02  482      (0788)
  347.   UINT32 sup_mode;                              // 03  483      (078c)
  348.   UINT32 sup_tv_mode;                           // 04  484      (0790)
  349.   UINT32 sup_panning;                           // 05  485      (0794)
  350.   UINT32 sup_aspect_ratio;                      // 06  486      (0798)
  351.   UINT32 sup_mon[5];                            // 07  487~ 491 (079c)
  352.   UINT32 sup_config;                            // 0c  492      (07b0)
  353.   UINT32 sup_buffer_limit;                      // 0d  493      (07b4)
  354.   UINT32 g15_reserved[18];                      // 0e  494~ 511 (07b8)
  356.   // GROUP 16
  357.   UINT32 g16_reserved[32];                      // 00  512~ 543 (0800) $bffe8800
  359.   // GROUP 17
  360.   UINT32 g17_reserved[32];                      // 00  544~ 575 (0880) $bffe8880
  362.   // GROUP 18:  UARTs
  363.   // UART0
  364.   UINT32 uart0_data;                            // 00  576      (0900) $bffe8900
  365.   UINT32 uart0_lsr;                             // 01  577      (0904)
  366.   UINT32 uart0_msr;                             // 02  578      (0908)
  367.   UINT32 uart0_lcr;                             // 03  579      (090c)
  368.   UINT32 uart0_mcr;                             // 04  580      (0910)
  369.   UINT32 uart0_div_l;                           // 05  581      (0914)
  370.   UINT32 uart0_div_h;                           // 06  582      (0918)
  371.   UINT32 uart0_isc;                             // 07  583      (091c)
  372.   // UART1
  373.   UINT32 uart1_data;                            // 08  584      (0920)
  374.   UINT32 uart1_lsr;                             // 09  585      (0924)
  375.   UINT32 uart1_msr;                             // 0a  586      (0928)
  376.   UINT32 uart1_lcr;                             // 0b  587      (092c)
  377.   UINT32 uart1_mcr;                             // 0c  588      (0930)
  378.   UINT32 uart1_div_l;                           // 0d  589      (0934)
  379.   UINT32 uart1_div_h;                           // 0e  590      (0938)
  380.   UINT32 uart1_isc;                             // 0f  591      (093c)
  381.   UINT32 g18_reserved[16];                      // 10  592~ 607 (0940)
  383.   // GROUP 19:  GPIO control
  384.   UINT32 gpio_master[8];                        // 00  608~ 615 (0980) $bffe8980
  385.   UINT32 gpio_oe[8];                            // 08  616~ 623 (09a0)
  386.   UINT32 gpio_out[8];                           // 10  624~ 631 (09c0)
  387.   UINT32 gpio_in[8];                            // 18  632~ 639 (09e0)
  389.   // GROUP 20:  CDDSP
  390.   UINT32 cddsp_config;                          // 00  640      (0a00) $bffe8a00
  391.   UINT32 cddsp_control;                         // 01  641      (0a04)
  392.   UINT32 cddsp_mm_bcd;                          // 02  642      (0a08)
  393.   UINT32 cddsp_ss_bcd;                          // 03  643      (0a0c)
  394.   UINT32 cddsp_ff_bcd;                          // 04  644      (0a10)
  395.   UINT32 cddsp_status;                          // 05  645      (0a14)
  396.   UINT32 cddsp_mmss;                            // 06  646      (0a18)
  397.   UINT32 cddsp_ffmm;                            // 07  647      (0a1c)
  398.   UINT32 g20_reserved[24];                      // 08  648~ 671 (0a20)
  400.   // GROUP 21:  TV1
  401.   UINT32 tv_gamma[5];                           // 00  672~ 676 (0a80) $bffe8a80
  402.   UINT32 tv_pccon[18];                          // 05  677~ 694 (0a94)
  403.   UINT32 g21_reserved[9];                       // 17  695~ 703 (0adc)
  405.   // GROUP 22:  MBUS
  406.   UINT32 mbus_bridge_config;                    // 00  704      (0b00) $bffe8b00
  407.   UINT32 evbya;                                 // 01  705      (0b04)
  408.   UINT32 osdya;                                 // 02  706      (0b08)
  409.   UINT32 cdwya;                                 // 03  707      (0b0c)
  410.   UINT32 cdrya;                                 // 04  708      (0b10)
  411.   UINT32 supya;                                 // 05  709      (0b14)
  413.   UINT32 evbya_limit;                           // 06  710      (0b18)
  414.   UINT32 osdya_limit;                           // 07  711      (0b1c)
  415.   UINT32 cdwya_limit;                           // 08  712      (0b20)
  416.   UINT32 cdrya_limit;                           // 09  713      (0b24)
  417.   UINT32 supya_limit;                           // 0a  714      (0b28)
  419.   UINT32 bs_ystop;                              // 0b  715      (0b2c)
  420.   UINT32 bs_ry;                                 // 0c  716      (0b30)
  421.   UINT32 bs_yinit;                              // 0d  717      (0b34)
  422.   UINT32 bs_xinit;                              // 0e  718      (0b38)
  423.   UINT32 dvddsp_vy;                             // 0f  719      (0b3c)
  424.   UINT32 dvddsp_vx;                             // 10  720      (0b40)
  425.   UINT32 dvddsp_ry;                             // 11  721      (0b44)
  427.   UINT32 cdr_vy;                                // 12  722      (0b48)
  428.   UINT32 cdr_vx;                                // 13  723      (0b4c)
  429.   UINT32 supya2;                                // 14  724      (0b50)
  430.   UINT32 supya2_limit;                          // 15  725      (0b54)
  432.   UINT32 iopya;                                 // 16  726      (0b58)
  433.   UINT32 cdrya_xlimit;                          // 17  727      (0b5c)
  434.   UINT32 mvcya;                                 // 18  728      (0b60)
  435.   UINT32 g22_reserved[7];                       // 19  729~ 735 (0b64)
  437.   // GROUP 23: VPP2
  438.   UINT32 g23_vpp_contrast_adj[2];               // 00  736~ 737 (0b80) $bffe8b80
  439.   UINT32 g23_vpp_contrast_slope[3];             // 02  738~ 740 (0b88)
  440.   UINT32 g23_vpp_histogram[8];                  // 05  741~ 748 (0b94)
  441.   UINT32 g23_vpp_chksum;                        // 0d  749      (0bb4)
  442.   UINT32 g23_vpp_mv_ptr;                        // 0e  750      (0bb8)
  443.   UINT32 g23_vpp_hue_adj[2];                    // 0f  751~ 752 (0bbc)
  444.   UINT32 g23_reserved[15];                      // 11  753~ 767 (0bc4)
  445.   /*
  446.   UINT32 g23_vpp_contrast_adj[2];               // 00  736~ 737 (0b80) $bffe8b80
  447.   UINT32 g23_vpp_contrast_slope[3];             // 02  738~ 740 (0b88)
  448.   UINT32 g23_vpp_histogram[8];                  // 05  741~ 748 (0b94)
  449.   UINT32 g23_vpp_chksum;                        // 0d  749      (0bb4)
  450.   UINT32 g23_vpp_mv_ptr;                        // 0e  750      (0bb8)
  451.   UINT32 g23_vpp_sb_checksum;                   // 0f  751 (0bbc)
  452.   UINT32 g23_vpp_sb_eflg;                     // 10  752  (0bc0)
  453.   UINT32 g23_vpp_linear_size;                   // 11  753  (0bc4)
  454.   UINT32 g23_vpp_c_up_sample;                   // 12  754  (0bc8)
  455.   UINT32 g23_vpp_mask_frame;                    // 13  755  (0bcc)
  456.   UINT32 g23_dip_threshold2;                    // 14  756  (0bd0)
  457.   UINT32 g23_dip_mv_ptr;                     // 15  757  (0bd4)
  458.   UINT32 g23_ds_pic_id2;                     // 16  758  (0bd8)
  459.   UINT32 g23_bdir2_luma_base;               // 17  759  (0bdc)
  460.   UINT32 g23_bdir2_chroma_base;             // 18  760  (0be0)
  461.   UINT32 g23_color_space;                     // 19  761  (0be4)
  462.   UINT32 g23_mask_win_start;                  // 1a  762  (0be8)
  463.   UINT32 g23_mask_win_end;                  // 1b  763  (0bec)
  464.   UINT32 g23_video_h_size;                  // 1c  764  (0bf0)
  465.   UINT32 g23_spare1;                  // 1d  765  (0bf4)
  466.   UINT32 g23_spare2;                  // 1e  766  (0bf8)
  467.   UINT32 g23_stamp;                  // 1f  767  (0bfc)
  468. */
  469.   // GROUP 24: Buffer Control
  470.   UINT32 bufctl[8];                             // 00  768~ 775 (0c00) $bffe8c00
  471.   UINT32 g24_reserved[24];                      // 08  776~ 799 (0c20)
  473.   // GROUP 25: INVQ
  474.   UINT32 invq_qmx_par;                          // 00  800      (0c80) $bffe8c80
  475.   UINT32 invq_mode;                             // 01  801      (0c84)
  476.   UINT32 invq_chksum;                           // 02  802      (0c88)
  477.   UINT32 g25_reserved_0[2];                     // 03  803~ 804 (0c8c)
  478.   UINT32 invq_vol_header;                       // 05  805      (0c94)
  479.   UINT32 g25_reserved_1[26];                    // 06  806~ 831 (0c98)
  481.   // GROUP 26: RI/ROM
  482.   UINT32 rom_config;                            // 00  832      (0d00) $bffe8d00
  483.   UINT32 wait_cyc1_0;                           // 01  833      (0d04)
  484.   UINT32 wait_cyc3_2;                           // 02  834      (0d08)
  485.   UINT32 oe_wait_cyc1_0;                        // 03  835      (0d0c)
  486.   UINT32 oe_wait_cyc3_2;                        // 04  836      (0d10)
  487.   UINT32 we_wait_cyc1_0;                        // 05  837      (0d14)
  488.   UINT32 we_wait_cyc3_2;                        // 06  838      (0d18)
  489.   UINT32 iochrdy_wait_cyc;                      // 07  839      (0d1c)
  490.   UINT32 rom1_base;                             // 08  840      (0d20)
  491.   UINT32 rom2_base;                             // 09  841      (0d24)
  492.   UINT32 rom3_base;                             // 0a  842      (0d28)
  493.   UINT32 pcmcia_iorw_wait;                      // 0b  843      (0d2c)
  494.   UINT32 pcmcia_ctrl;                           // 0c  844      (0d30)
  495.   UINT32 g26_reserved1[8];                      // 0d  845~ 852 (0d34)
  496.   UINT32 adt[4];                                // 15  853~ 856 (0d54)
  497.   UINT32 dat[4];                                // 19  857~ 860 (0d64)
  498.   UINT32 adm[2];                                // 1d  861~ 862 (0d74)
  499.   UINT32 dar;                                   // 1f  863      (0d7c)
  501.   // GROUP 27: System Bus Arbitrator
  502.   UINT32 sbar_config;                           // 00  864      (0d80) $bffe8d80
  503.   UINT32 sbar_prr[16];                          // 01  865~ 880 (0d84)
  504.   UINT32 g27_reserved[2];                       // 11  881~ 882 (0dc4)
  505.   UINT32 sbar_sdram_rom;                        // 13  883      (0dcc)
  506.   UINT32 g27_reserved1[12];                     // 14  884~ 895 (0dd0)
  508.   // GROUP 28: Bridge
  509.   UINT32 rf_sdramif_tbya;                       // 00  896      (0e00) $bffe8e00
  510.   UINT32 rf_servo_band_en;                      // 01  897      (0e04)
  511.   UINT32 rf_servo_band_val;                     // 02  898      (0e08)
  512.   UINT32 g28_reserved[29];                      // 03  899~ 927 (0e0c)
  514.   // GROUP 29: Servo
  515.   UINT32 rf_regif_addr;                         // 00  928      (0e80) $bffe8e80
  516.   UINT32 rf_regif_wdata;                        // 01  929      (0e84)
  517.   UINT32 rf_regif_rdata;                        // 02  930      (0e88)
  518.   UINT32 rf_regif_sample_ctrl;                  // 03  931      (0e8c)
  519.   UINT32 rf_regif_intr_addr;                    // 04  932      (0e90)
  520.   UINT32 rf_regif_intr_wdata;                   // 05  933      (0e94)
  521.   UINT32 rf_regif_intr_rdata;                   // 06  934      (0e98)
  522.   UINT32 g29_reserved[25];                      // 07  935~ 959 (0e9c)
  524.   // GROUP 30: Emulation control
  525.   UINT32 emu_cfg[32];                           // 00  960~ 991 (0f00) $bffe8f00
  527.   // GROUP 31: Audio hardware control
  528.   UINT32 aud_reset;                             // 00  992      (0f80) $bffe8f80
  529.   UINT32 aud_pcm_cfg;                           // 01  993      (0f84)
  530.   UINT32 aud_spdif_cfg;                         // 02  994      (0f88)
  531.   UINT32 aud_enable;                            // 03  995      (0f8c)
  532.   UINT32 aud_adc_stereo_cfg;                    // 04  996      (0f90)
  533.   UINT32 aud_adc_mono_cfg;                      // 05  997      (0f94)
  534.   UINT32 aud_pcm_ramp_delta;                    // 06  998      (0f98)
  535.   UINT32 aud_pcm_ramp_cfg;                      // 07  999      (0f9c)
  536.   UINT32 aud_pcm_ramp_value;                    // 08 1000      (0fa0)
  537.   UINT32 aud_spdif_period;                      // 09 1001      (0fa4)
  538.   UINT32 aud_fifo_flag;                         // 0a 1002      (0fa8)
  539.   UINT32 aud_chn_pcm_cnt[10];                   // 0b 1003~1012 (0fac)
  540.   UINT32 aud_xck_cfg;                           // 15 1013      (0fd4)
  541.   UINT32 aud_pcm_bck_cfg;                       // 16 1014      (0fd8)
  542.   UINT32 aud_iec_bclk_cfg;                      // 17 1015      (0fdc)
  543.   UINT32 aud_adc_mclk_cfg;                      // 18 1016      (0fe0)
  544.   UINT32 aud_dsp_run_cnt;                       // 19 1017      (0fe4)
  545.   UINT32 aud_dsp_stall_cnt;                     // 1a 1018      (0fe8)
  546.   UINT32 aud_dsp_reset_flag;                    // 1b 1019      (0fec)
  547.   UINT32 aud_dsp_dec_cnt_toggle;                // 1c 1020      (0ff0)
  548.   UINT32 aud_dsp_dec_cnt;                       // 1d 1021      (0ff4)
  549.   UINT32 aud_fpga_v2[2];                        // 1e 1022~1023 (0ff8)
  551.   // GROUP 32
  552.   //UINT32 g32_reserved[32];                    // 00 1024~1055 (1000) $bffe9000
  553.   UINT32 card_mediaType;
  554.   UINT32 g32_reserved1[10];
  555.   UINT32 fm_gpio_mode; // 11
  556.   UINT32 fm_gpio_len; //12
  557.   UINT32 g32_reserved2[19];
  559.   // GROUP 33
  560.   //UINT32 g33_reserved[32];                      // 00 1056~1087 (1080) $bffe9080
  561.   UINT32 ndData;             // 0x20
  562.   UINT32 ndTimeProf;         // 0x21
  563.   UINT32 g33_reserved1;      // 0x22
  564.   UINT32 ndCtrl[2];          // 0x23 ~ 0x24
  565.   UINT32 g33_reserved2[11];  // 0x25 ~ 0x2f
  566.   UINT32 ataData;            // 0x30
  567.   UINT32 cfCtrl;             // 0x31
  568.   UINT32 cfAddrLsb;          // 0x32
  569.   UINT32 cfAddrMsb;          // 0x33
  570.   UINT32 ataMode;            // 0x34
  571.   UINT32 ataPulsWidth;       // 0x35
  572.   UINT32 ataCsnn;            // 0x36
  573.   UINT32 g33_reserved3[2];   // 0x37 ~ 0x38
  574.   UINT32 ataRegnn;           // 0x39
  575.   UINT32 ataRstnn;           // 0x3A
  576.   UINT32 fmGpioA;            // 0x3B
  577.   UINT32 g33_reserved4;      // 0x3C
  578.   UINT32 cfActTime;          // 0x3D
  579.   UINT32 g33_reserved5[2];   // 0x3e ~ 0x3f
  581.   // GROUP 34
  582.   //UINT32 g34_reserved[32];                      // 00 1088~1119 (1100) $bffe9100
  583.     UINT32  g34_reserved1[6];     // (1100) $bffe9100
  584. UINT32  spiFreq;            /* 0x46          */// (1106) $bffe9118
  585. UINT32  spiConfig;          /* 0x47          */// (1107) $bffe911C
  586. UINT32  spiMode;            /* 0x48          */
  587. UINT32  g34_reserved2[2];
  588. UINT32  spiStatus;          /* 0x4B          */
  589. UINT32  g34_reserved3[4];   /* 0x4C ~ 0x4F   */
  590. UINT32  sdRst;              /* 0x50          */
  591. UINT32  sdConfig;           /* 0x51          */
  592. UINT32  sdCtrl;             /* 0x52          */
  593. UINT32  sdStatus0;          /* 0x53          */
  594. UINT32  sdStatus1;          /* 0x54          */
  595. UINT32  sdBlockSize;        /* 0x55          */
  596. UINT32  g34_reserved4;      /* 0x56          */
  597. UINT32  sdRspTmr;           /* 0x57          */
  598. UINT32  sdCrcTmr;           /* 0x58          */
  599. UINT32  sdPioDataTx;        /* 0x59          */
  600. UINT32  sdPioDataRx;        /* 0x5a          */
  601. UINT32  sdCmdBuf[5];        /* 0x5b ~ 0x5f   */
  602.   // GROUP 35
  603.   //UINT32 g35_reserved[32];                      // 00 1120~1151 (1180) $bffe9180
  604.     UINT32  sdRspBuf[6];        /* 0x60 ~ 0x65   */
  605. UINT32  sdCrc7Buf;          /* 0x66          */
  606. UINT32  sdCrc16Buf0Lsb;     /* 0x67          */
  607. UINT32  sdCrc16Buf0Msb;     /* 0x68          */
  608. UINT32  sdCrc16Buf1Lsb;     /* 0x69          */
  609. UINT32  sdCrc16Buf1Msb;     /* 0x6a          */
  610. UINT32  sdCrc16Buf2Lsb;     /* 0x6b          */
  611. UINT32  sdCrc16Buf2Msb;     /* 0x6c          */
  612. UINT32  sdCrc16Buf3Lsb;     /* 0x6d          */
  613. UINT32  sdCrc16Buf3Msb;     /* 0x6e          */
  614. UINT32  sdCrc16Flag;        /* 0x6f          */
  616.     UINT32  msPioDmaRst;        /* 0x70          */
  617.     UINT32  msCmd;              /* 0x71          */
  618.     UINT32  g35_reserved1[2];   /* 0x72,0x73     */
  619.     UINT32  msModeSpeed;        /* 0x74          */
  620.     UINT32  msTimout;           /* 0x75          */
  621.     UINT32  msState1;           /* 0x76          */
  622.     UINT32  msState2;           /* 0x77          */
  623.     UINT32  msRddata[4];        /* 0x78~0x7B     */
  624.     UINT32  msCrcBufLsb;        /* 0x7C          */
  625.     UINT32  msCrcBufMsb;        /* 0x7D          */
  626.     UINT32  msCrcError;         /* 0x7E          */
  627.     UINT32  msPioRdy;           /* 0x7F          */
  630.     // GROUP 36
  632.     UINT32  msWdData[16];       /* 0x80~0x8f     */
  633.     UINT32  g36_reserved1[16];
  635.     // GROUP 37
  636.     //UINT32 g37_reserved[32];                      // 00 1184~1215 (1280) $bffe9280
  637.     UINT32  eccReset;           /* 0xa0        */
  638.     UINT32  psFmData;           /* 0xa1        */
  639.     UINT32  eccMask;            /* 0xa2        */
  640.     UINT32  eccMode;            /* 0xa3        */
  641.     UINT32  ecc1;               /* 0xa4        */
  642.     UINT32  ecc0;               /* 0xa5        */
  643.     UINT32  ecc2;               /* 0xa6        */
  644.     UINT32  ecc4;               /* 0xa7        */
  645.     UINT32  ecc3;               /* 0xa8        */
  646.     UINT32  ecc5;               /* 0xa9        */
  647.     UINT32  ecc7;               /* 0xaa        */
  648.     UINT32  ecc6;               /* 0xab        */
  649.     UINT32  ecc8;               /* 0xac        */
  650.     UINT32  ecca;               /* 0xad        */
  651.     UINT32  ecc9;               /* 0xae        */
  652.     UINT32  eccb;               /* 0xaf        */
  653.     UINT32  g37_reserved1[16];  /* 0xb0~ 0xbf  */
  655.   // GROUP 38
  656.   UINT32 g38_reserved[32];                      // 00 1216~1247 (1300) $bffe9300
  658.   // GROUP 39
  659.   UINT32 gpio_mode_B;
  660.   UINT32 g39_reserved[31];                      // 00 1248~1279 (1380) $bffe9380
  662.   // GROUP 40: DMA Controller Register
  663.   UINT32 dma_data;                              // 0x00 1280      (1400) $bffe9400
  664.   UINT32 dma_srcDst;                            // 0x01 1281~1308
  665.   UINT32 dma_size;                              // 0x02
  666.   UINT32 g40_reserved1;     // 0x03
  667.   UINT32 dma_ctrl; // 0x04
  668.   UINT32 dma_base_addrL;    // 0x05
  669.   UINT32 dma_base_addrH; // 0x06
  670.   UINT32 g40_reserved2[14]; // 0x07 ~  0x14
  671.   UINT32 dma_start;  // 0x15
  672.   UINT32 g40_reserved3;  // 0x16
  673.   UINT32 dma_cmp; // 0x17
  674.   UINT32 dma_cmpEn; // 0x18
  675.   UINT32 g40_reserved4[7];    // 0x19 ~  0x1f
  677.   // GROUP 41: (EMU) SDRAM 6A
  678.   UINT32 sdc_data_cnt[14][2];                   // 00 1312~1339 (0520) $bffe9480
  679.   UINT32 sdc_n_req_cnt[2];                      // 1c 1340~1341 (14f0)
  680.   UINT32 sdc_cke_cnt[2];                        // 1e 1342~1343 (14f8)
  682.   // GROUP 42~44
  683.   UINT32 g42_reserved[32];                      // 00 1344~1375 (1500) $bffe9500
  684.   UINT32 g43_reserved[32];                      // 00 1376~1407 (1580) $bffe9580
  685.   UINT32 g44_reserved[32];                      // 00 1408~1439 (1600) $bffe9600
  687.   // GROUP 45:  GAME16  
  688.   UINT32 game16_control; // 00  512~ 543 (0800) $bffe9680
  689.   UINT32 game16_status; // 0xbffe8804
  690.   UINT32 game16_code_base; // 0xbffe8808
  691.   UINT32 game16_vram_base; // 0xbffe880c
  692.   UINT32 game16_work_base;  // 0xbffe8810
  693.   UINT32 game16_game_dsp_dec_base; // 0xbffe8814
  694.   UINT32 game16_frame_base0; // 0xbffe8818
  695.   UINT32 game16_frame_base1; // 0xbffe881c
  696.   UINT32 game16_version; // 0xbffe8820
  697.   UINT32 game16_int_mode; // 0xbffe8824
  698.   UINT32 game16_io_data1; // 0xbffe8828
  699.   UINT32 game16_io_data2; // 0xbffe882c
  700.   UINT32 game16_io_data3; // 0xbffe8830
  701.   UINT32 game16_dma_control; // 0xbffe8834
  702.   UINT32 game16_game_dsp_dec_control; // 0xbffe8838
  703.   UINT32 game16_game_dsp_dec_wait; // 0xbffe883c
  704.   UINT32 game16_game_dsp_dec_buf_base; // 0xbffe8840
  705.   UINT32 game16_game_dsp_dec_buf_size; // 0xbffe8844
  706.   UINT32 game16_game_dsp_dec_buf_in; // 0xbffe8848 
  707.   UINT32 game16_game_dsp_dec_buf_out; // 0xbffe884c
  708.   UINT32 game16_game_dsp_dec_ice_base; // 0xbffe8850
  709.   UINT32 game16_game_dsp_dec_int_addr; // 0xbffe8854  
  710.   UINT32 game16_disp_control; // 0xbffe8858  
  711.   UINT32 game16_risc_control; // 0xbffe885c 
  712.   UINT32 game16_risc_data; // 0xbffe8860   
  713.   UINT32 g45_reserved[7]; // 
  715.   // GROUP 46~49
  716.   UINT32 g46_reserved[32];                      // 00 1472~1503 (1700) $bffe9700
  717.   UINT32 g47_reserved[32];                      // 00 1504~1535 (1780) $bffe9780
  718.   UINT32 g48_reserved[32];                      // 00 1536~1567 (1800) $bffe9800
  719.   UINT32 g49_reserved[32];                      // 00 1568~1599 (1880) $bffe9880
  721.   // GROUP 50
  722.   UINT32 g50_reserved[29];                      // 00 1600~1628 (1900) $bffe9900
  723.   UINT32 risc_fpga_version[3];                  // 1d 1629~1631 (1974)
  725.   // GROUP 51
  726.   UINT32 g51_reserved[29];                      // 00 1632~1660 (1980) $bffe9980
  727.   UINT32 block_fpga_version[3];                 // 1d 1661~1663 (19f4)
  729.   // GROUP 52
  730.   UINT32 g52_reserved[29];                      // 00 1664~1692 (1a00) $bffe9a00
  731.   UINT32 aud_fpga_version[3];                   // 1d 1693~1695 (1a74)
  733.   // GROUP 53~63
  734.   UINT32 g53_reserved[32];                      // 00 1696~1727 (1a80) $bffe9a80
  735.   UINT32 g54_reserved[32];                      // 00 1728~1759 (1b00) $bffe9b00
  736.   UINT32 g55_reserved[32];                      // 00 1760~1791 (1b80) $bffe9b80
  737.   UINT32 g56_reserved[32];                      // 00 1792~1823 (1c00) $bffe9c00
  738.   UINT32 g57_reserved[32];                      // 00 1824~1855 (1c80) $bffe9c80
  739.   UINT32 g58_reserved[32];                      // 00 1856~1887 (1d00) $bffe9d00
  740.   UINT32 g59_reserved[32];                      // 00 1888~1919 (1d80) $bffe9d80
  741.   UINT32 g60_reserved[32];                      // 00 1920~1951 (1e00) $bffe9e00
  742.   UINT32 g61_reserved[32];                      // 00 1952~1983 (1e80) $bffe9e80
  743.   UINT32 g62_reserved[32];                      // 00 1984~2015 (1f00) $bffe9f00
  744.   UINT32 g63_reserved[32];                      // 00 2016~2047 (1f80) $bffe9f80
  746.   // GROUP 64~255
  747.   UINT32 gxx_reserved[192][32];                 // 00 2048~8191 (0800) $bffea000
  749.   // GROUP
  750.   WorkBuf reg_dma_buf;
  751.   WorkBuf reg_dma_buf256;
  752.   WorkBuf reg_dma_buf512;
  753.   WorkBuf reg_dma_buf768;
  755.   //
  756.   // (OLD hardware, just for compatible issue)
  757.   //
  758. //  UINT32 evbya2;                                // 00 8192      (8000) $bfff0000
  759. //  UINT32 eabya;                                 // 01 8193      (8004)
  760. //  UINT32 dsp16ya;                               // 02 8194      (8008)
  761. //  UINT32 dma_addrmode;                          // 03 8195      (800c)
  762. //  UINT32 dma_addrlen;                           // 04 8196      (8010)
  763. //  UINT32 epp_status;                            // 05 8197      (8014)
  764. //  UINT32 epp_data;                              // 06 8198      (8018)
  765. //  UINT32 agdc_config;                           // 07 8199      (801c)
  766. //  UINT32 video_compress;                        // 08 8200      (8020)
  767. //  UINT32 dis_tv_out;                            // 09 8201      (8024)
  768. //  UINT32 audio_clkgen;                          // 05    5      (0014)
  770. } RegisterFile;
  773. /*
  774. **  Video
  775. */
  776. #define RF_CODING_EXT0_PROGRESSIVE_FRAME (1<<0)
  777. #define RF_CODING_EXT0_CHROMA_420_TYPE (1<<1)
  778. #define RF_CODING_EXT0_REPEAT_FIRST_FIELD (1<<2)
  779. #define RF_CODING_EXT0_ALTERNATE_SCAN (1<<3)
  780. #define RF_CODING_EXT0_INTRA_VLC_FORMAT (1<<4)
  781. #define RF_CODING_EXT0_Q_SCALE_TYPE (1<<5)
  782. #define RF_CODING_EXT0_CONCEAL_MOTION_VECTORS (1<<6)
  783. #define RF_CODING_EXT0_FRAME_PRED_FRAME_DCT (1<<7)
  784. #define RF_CODING_EXT0_TOP_FIELD_FIRST (1<<8)
  785. #define RF_CODING_EXT0_PICTURE_STRUCTURE (0x03<<9)
  786. #define RF_CODING_EXT0_INTRA_DC_PRECISION (0x03<<11)
  787. //#define RF_CODING_EXT0_LAST_PICTURE (1<<14)
  788. #define RF_CODING_EXT0_BACK_LAST (1<<14)
  789. #define RF_CODING_EXT0_SECOND_FIELD (1<<15)
  791. #define ext0_pic_struct(x) (((x)>>9)&0x03)
  793. /*
  794. ** Display Output Tweaking
  795. */
  796. #define RF_VOUT_SWAP_CBCR (1<<1)
  797. #define RF_VOUT_SWAP_LC (1<<2)
  799. /*
  800. **  Display Status
  801. */
  802. #define RF_Display_OSDRegion 0x00ff
  803. #define RF_Display_FieldNo 0x8000
  804. #define RF_Display_VSyncB 0x4000
  805. #define RF_Display_HSyncB 0x2000
  806. #define RF_Display_FieldEnd 0x1000
  808. #define DISPLAY_STATUS                  regs0->osd_display_status
  809. #define IsVSync()                       ((DISPLAY_STATUS & RF_Display_VSyncB)==0)
  810. #define IsHSync()                       ((DISPLAY_STATUS & RF_Display_HSyncB)==0)
  811. #define IsTopField()                    ((DISPLAY_STATUS & RF_Display_FieldNo)==0)
  812. #define IsBottomField()                 ((DISPLAY_STATUS & RF_Display_FieldNo))
  813. #define IsFieldEnd()                    ((DISPLAY_STATUS & RF_Display_FieldEnd))
  815. #define RF_Video_VPicEnd 0x0001
  816. #define RF_Video_VTblErr 0x0002
  817. #define RF_Video_VRunErr 0x0004
  818. #define RF_Video_VSliceErr 0x0008
  819. #define RF_Video_VErr 0x8000
  821. /*
  822. ** RISC Picture Start
  823. */
  824. #define IsRPicStart (regs0->pic_start)
  826. /*
  827. ** VLD Decoding Status
  828. */
  829. #define VLD_STATUS                      (regs0->vld_status)
  830. #define IsVPicEnd                       (VLD_STATUS & RF_Video_VPicEnd)
  831. #define IsVRunErr                       (VLD_STATUS & RF_Video_VRunErr)
  832. #define IsVTblErr                       (VLD_STATUS & RF_Video_VTblErr)
  833. #define IsVErr                          (VLD_STATUS & RF_Video_VErr)
  835. #define RF_CODING_EXT1_FORWARD_REF0 (0<<1)
  836. #define RF_CODING_EXT1_FORWARD_REF1 (1<<1)
  838. #define RF_CODING_EXT1_RECONST_REF0 (0<<2)
  839. #define RF_CODING_EXT1_RECONST_REF1 (1<<2)
  840. #define RF_CODING_EXT1_RECONST_B (2<<2)
  842. #define RF_CODING_EXT1_FIELDID (1<<4)
  845. //
  846. // TIMER TIMER TIMER TIMER TIMER TIMER TIMER
  847. //
  848. #define RF_TIMER_SRC_SYSCLK (0<<14)
  849. #define RF_TIMER_SRC_STC (1<<14)
  850. #define RF_TIMER_SRC_RTC (2<<14)
  851. #define RF_TIMER_SRC_TIMER (3<<14)
  852. #define RF_TIMER_RUN_ON (1<<13)
  853. #define RF_TIMER_RUN_OFF (0<<13)
  854. #define RF_TIMER_GO_ON (1<<11)
  855. #define RF_TIMER_GO_OFF (0<<11)
  856. #define RF_TIMER_MASK (0x3ff)
  858. #define TIMER_CONFIG_STOP ( RF_TIMER_GO_OFF )
  859. #define TIMER_CONFIG_STC ( RF_TIMER_SRC_STC
  860. | RF_TIMER_RUN_ON
  861. | RF_TIMER_GO_ON)
  863. #define TIMER_CONFIG_10ms ( TIMER_CONFIG_STC | (900-1))
  864. #define TIMER_CONFIG_4ms ( TIMER_CONFIG_STC | (360-1))
  865. #define TIMER_CONFIG_1ms ( TIMER_CONFIG_STC | (90-1))
  867. #define TIMER_CONFIG_dly ( RF_TIMER_SRC_STC
  868.      | RF_TIMER_RUN_OFF
  869. | RF_TIMER_GO_ON)
  871. #define TIMER_CONFIG_dlys(n) ( TIMER_CONFIG_dly | (n-1))
  872. #define TIMER_CONFIG_90k(n) ( TIMER_CONFIG_STC | (n-1))
  875. /*
  876. ** VPP VPP VPP VPP VPP VPP VPP
  877. */
  878. #define RF_HFACTOR_HEXP_ENABLE (1<<8)
  879. #define RF_HFACTOR_CIF_ENABLE (1<<9)
  882. /*
  883. **  CDDSP Control/Status
  884. */
  885. #define RF_CDDSP_RESET 0x0001
  886. #define RF_CDDSP_STOP 0x0002
  887. #define RF_CDDSP_PAUSE 0x0004
  888. #define RF_CDDSP_SEEK 0x0008
  890. #define RF_CDDSP_CRC_ERROR 0x0001
  891. #define RF_CDDSP_CRC_ERROR_LAST 0x0002
  892. #define RF_CDDSP_CRC_ERROR_MASK 0x0003
  894. /*
  895. **
  896. */
  897. #define RF_DSP24_RESET (1<<0)
  898. #define RF_DSP24_STALL (1<<1)
  900. /*
  901. ** EPP status
  902. */
  903. #define RF_EPP_IN_FULL (1<<3)
  904. #define RF_EPP_IN_EMPTY (1<<2)
  905. #define RF_EPP_OUT_FULL (1<<1)
  906. #define RF_EPP_OUT_EMPTY (1<<0)
  908. #define RF_Video_MPEG2_flag 0x08
  911. /*
  912. ** AGDC config
  913. */
  914. #define RF_AGDC_BPIC_LOC_RIGHT (0 << 0)
  915. #define RF_AGDC_BPIC_LOC_BOTTOM (1 << 0)
  916. #define RF_AGDC_BPIC_SIZE_LINE (0 << 2)
  917. #define RF_AGDC_BPIC_SIZE_FIELD (1 << 2)
  918. #define RF_AGDC_BPIC_SIZE_FULL (2 << 2)
  919. #define RF_AGDC_SDRAM_64MB (0 << 6)
  920. #define RF_AGDC_SDRAM_16MB (1 << 6)
  922. #define set_dis_tv_std(n) (regs0->osd_tv_std=(n))
  925. /*
  926. ** VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO
  927. */
  928. #define RF_COMPRESS_888 (0 << 0)
  929. #define RF_COMPRESS_866 (1 << 0)
  930. #define RF_COMPRESS_666 (2 << 0)
  931. #define RF_COMPRESS_8655 (3 << 0)
  932. #define RF_COMPRESS_DITHER_ON (1 << 7)
  933. #define RF_COMPRESS_DITHER_OFF (0 << 7)
  934. #define RF_COMPRESS_CHROMA_FULL (0 << 8)
  935. #define RF_COMPRESS_CHROMA_HALF (1 << 8)
  937. /*
  938. ** regs0: register file pointer
  939. */
  940. #ifdef  GLOBAL_REGISTER
  941. register volatile       RegisterFile    *regs0  asm ("22");
  942. #define InitRegFile()   (regs0 = (volatile RegisterFile *)RGST_OFFSET)
  943. #else
  944. #define regs0           ((volatile RegisterFile *)RGST_OFFSET)
  945. #define InitRegFile()   {}
  946. #endif
  948. #endif/*__REGMAP_DVD_H*/