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regmapo_8200.h
资源名称：8202s.rar　[点击查看]
上传用户：poi891205
上传日期：2013-07-15
资源大小：9745k
文件大小：39k
源码类别：

DVD

开发平台：

C/C++

regmapo_8200.h：源码内容
  1. #ifndef __REGMAP_8200_H
  2. #define __REGMAP_8200_H
  4. /*
  5. ** FILE
  6. ** regmap.h
  7. **
  8. ** DESCRIPTION
  9. ** define register-file structure.
  10. **
  11. ** NOTE:
  12. ** specific for sphe8200
  13. */
  15. #include "types.h"
  16. #include "dmabuf.h"
  18. /*
  19. ** TYPE
  20. ** RegisterFile
  21. */
  22. typedef struct 
  23. {
  24.   // GROUP 0: Chip Information
  25.   UINT32 stamp;                                 // 00    0      (0000) $bffe8000
  26.   UINT32 emulation;                             // 01    1      (0004)
  27.   UINT32 reset;                                 // 02    2      (0008)
  28.   UINT32 reset2;                                // 03    3      (000c)
  29.   UINT32 pad_ctrl;                              // 04    4      (0010)
  30.   UINT32 sdram_clko_cfg;                        // 05
  31.   UINT32 sdram_clki_cfg;                        // 06
  32.   UINT32 sdram_clki_dly_cfg;                    // 07
  33.   UINT32 clk_mon_sel;                           // 08
  34.   UINT32 clk_mon_result;                        // 09 
  35.   UINT32 clken0;                                // 0a 
  36.   UINT32 clken1;                                // 0b 
  37.   UINT32 gclken0;                               // 0c
  38.   UINT32 gclken1;                               // 0d
  39.   UINT32 sysclk_div_sel;                        // 0e
  40.   UINT32 sysclk_sel;                            // 0f
  41.   UINT32 pllv_cfg;                              // 10
  42.   UINT32 sft_cfg0;                              // 11   17      (0044)
  43.   UINT32 sft_cfg1;                              // 12   18      (0048)
  44.   UINT32 sft_cfg2;                              // 13   19      (004c)
  45.   UINT32 sft_cfg3;                              // 14   20      (0050)
  46.   UINT32 sft_cfg4;                              // 15   21      (0054)
  47.   UINT32 sft_cfg5;                              // 16   22      (0058)
  48.   UINT32 sft_cfg6;                              // 17   23      (005c)
  49.   UINT32 sft_cfg7;                              // 16   22      (0058)
  50.   UINT32 sft_cfg8;                              // 17   23      (005c)
  51.   UINT32 hw_bo;
  52.   UINT32 hw_cfg;
  53.   UINT32 hw_cfg_chg;
  54.   UINT32 sft_cfg9;                              // 16   22      (0058)
  55.   UINT32 sft_cfga;                              // 17   23      (005c)
  56.   UINT32 g0_reserved_1[1];                      // 
  58.   // GROUP 1: Timers
  59.   UINT32 stc_15_0;                              // 00   32      (0080) $bffe8080
  60.   UINT32 stc_31_16;                             // 01   33      (0084)
  61.   UINT32 stc_32;                                // 02   34      (0088)
  62.   UINT32 stc_divisor;                           // 03   35      (008c)
  63.   UINT32 rtc_15_0;                              // 04   36      (0090)
  64.   UINT32 rtc_31_16;                             // 05   37      (0094)
  65.   UINT32 rtc_divisor;                           // 06   38      (0098)
  66.   UINT32 stc_config;                            // 07   39~  39 (009c)
  67.   UINT32 timer0_ctrl;                           // 08   40      (00a0)
  68.   UINT32 timer0_cnt;                            // 09   41      (00a4)
  69.   UINT32 timer1_ctrl;                           // 0a   42      (00a8)
  70.   UINT32 timer1_cnt;                            // 0b   43      (00ac)
  71.   UINT32 timerw_ctrl;                           // 0c   44      (00b0)
  72.   UINT32 timerw_cnt;                            // 0d   45      (00b4)
  73.   UINT32 g1_unused_1[2];                        // 0e   46~  47 (00b8)
  74.   UINT32 timer2_ctrl;                           // 10   48      (00c0)
  75.   UINT32 timer2_divisor;                        // 11   49      (00c4)
  76.   UINT32 timer2_reload;                         // 12   50      (00c8)
  77.   UINT32 timer2_cnt;                            // 13   51      (00cc)
  78.   UINT32 timer3_ctrl;                           // 14   52      (00d0)
  79.   UINT32 timer3_divisor;                        // 15   53      (00d4)
  80.   UINT32 timer3_reload;                         // 16   54      (00d8)
  81.   UINT32 timer3_cnt;                            // 17   55      (00dc)
  82.   UINT32 stcl_0;
  83.   UINT32 stcl_1;
  84.   UINT32 stcl_2;
  85.   UINT32 atc_0;
  86.   UINT32 atc_1;
  87.   UINT32 atc_2;
  88.   UINT32 g1_reserved[2];                        // 18   56~  63 (00e0)
  90.   // GROUP 2: RISC interface
  91.   UINT32 intr_mask;                             // 00   64      (0100) $bffe8100
  92.   UINT32 intr_flag;                             // 01   65      (0104)
  93.   UINT32 intr_masked_flag;                      // 02   66      (0108)
  94.   UINT32 intr_clear;                            // 03   67      (010c)
  95.   UINT32 intr_polarity;                         // 04   68      (0110)
  96.   UINT32 intr_edge;                             // 05   69      (0114)
  97.   UINT32 intr1_mask;                            // 06   70      (0118)
  98.   UINT32 intr1_flag;                            // 07   71      (011c)
  99.   UINT32 intr1_masked_flag;                     // 08   72      (0120)
  100.   UINT32 intr1_clear;                           // 09   73      (0124)
  101.   UINT32 intr1_polarity;                        // 0a   74      (0128)
  102.   UINT32 intr1_edge;                            // 0b   75      (012c)
  103.   UINT32 lbc_control;                           // 0c   76      (0130)
  104.   UINT32 lbc_watchdog;                          // 0d   77      (0134)
  105.   UINT32 rec_start;                             // 0e   78      (0138)
  106.   UINT32 rec_end;                               // 0f   79      (013c)
  107.   UINT32 rec_l_m;                               // 10   80      (0140)
  108.   UINT32 g2_reserved[13];                       // 11   81~  95 (0144)
  109.   UINT32 ri_misc_b0;                            // 1e   81~  95 (0144)
  110.   UINT32 ri_misc_b1;                            // 1f   81~  95 (0144)
  112.   // GROUP 3: Video bitstream parameters 
  113.   UINT32 seq_ext;                               // 00   96      (0180) $bffe8180
  114.   UINT32 h_size;                                // 01   97      (0184)
  115.   UINT32 v_size;                                // 02   98      (0188)
  116.   UINT32 g3_unused;                             // 03   99      (018c)
  117.   UINT32 pic_coding_type;                       // 04  100      (0190)
  118.   UINT32 pic_f_code;                            // 05  101      (0194)
  119.   UINT32 pic_coding_ext0;                       // 06  102      (0198)
  120.   UINT32 pic_coding_ext1;                       // 07  103      (019c)
  121.   UINT32 pic_start;                             // 08  104      (01a0)
  122.   UINT32 dis_pic_id;                            // 09  105      (01a4)
  123.   UINT32 dis_seq_tag;                           // 0a  106      (01a8)
  124.   UINT32 g3_reserved[21];                       // 0b  107~ 127 (01ac)
  126.   // GROUP 4: VLD parameters
  127.   UINT32 vld_ctrl;                              // 00  128      (0200) $bffe8200
  128.   UINT32 vld_status;                            // 01  129      (0204)
  129.   UINT32 vld_decode_time;                       // 02  130      (0208)
  130.   UINT32 g4_unused;                             // 03  131      (020c)
  131.   UINT32 vld_mon0;                              // 04  132      (0210)
  132.   UINT32 vld_mon1;                              // 05  133      (0214)
  133.   UINT32 vld_mon2;                              // 06  134      (0218)
  134.   UINT32 vld_mon3;                              // 07  135      (021c)
  135.   UINT32 jpeg_control;                          // 08  136      (0220)
  136.   UINT32 jpeg_write_addr;                       // 09  137      (0224)
  137.   UINT32 jpeg_write_data;                       // 0a  138      (0228)
  138.   UINT32 jpeg_read_addr;                        // 0b  139      (022c)
  139.   UINT32 jpeg_read_data;                        // 0c  140      (0230)
  140.   UINT32 error_mb_threshold;                    // 0d  141      (0234)
  141.   UINT32 vld_config;                            // 0e  142      (0238)
  142.   UINT32 g4_reserved[17];                       // 0f  143~ 159 (023c)
  144.   // GROUP 5: MC configuration zero registers
  145.   UINT32 mc_config;                             // 00  160      (0280) $bffe8280
  146.   UINT32 ref0_luma;                             // 01  161      (0284)
  147.   UINT32 ref0_chroma;                           // 02  162      (0288)
  148.   UINT32 ref1_luma;                             // 03  163      (028c)
  149.   UINT32 ref1_chroma;                           // 04  164      (0290)
  150.   UINT32 bidir_luma;                            // 05  165      (0294)
  151.   UINT32 bidir_chroma;                          // 06  166      (0298)
  152.   UINT32 g5_reserved[17];                       // 07  167~ 183 (029c)
  153.   UINT32 mc_spare_0;                            // 18  184      (02e0)
  154.   UINT32 mc_compress;                           // 19  185      (02e4)
  155.   UINT32 mc_pardec_start;                       // 1a  186      (02e8)
  156.   UINT32 mc_pardec_end;                         // 1b  187      (02ec)
  157.   UINT32 mc_mbwidth;                            // 1c  188      (02f0)
  158.   UINT32 mc_pardec_en;                          // 1d  189      (02f4)
  159.   UINT32 mc_spare_6;                            // 1e  190      (02f8)
  160.   UINT32 mc_spare_7;                            // 1f  191      (02fc)
  162.   // GROUP 6: SDRAM control
  163.   UINT32 sdctrl_cfg0;                           // 00  192      (0300) $bffe8300
  164.   UINT32 sdctrl_cfg1;                           // 01  193      (0304)
  165.   UINT32 sdctrl_cfg2;                           // 02  194      (0308)
  166.   UINT32 sdctrl_mrs;                            // 03  195      (030c)
  167.   UINT32 sdctrl_sref_cfg;                       // 04  196      (0310)
  168.   UINT32 sdctrl_cfg3;                           // 05  197      (0314)
  169.   UINT32 sdctrl_data_mon_st;                    // 06  198      (0318)
  170.   UINT32 sdctrl_data_cyc_l;                     // 07  199      (031c)
  171.   UINT32 sdctrl_data_cyc_h;                     // 08  200      (0320)
  172.   UINT32 sdctrl_data_cnt_l;                     // 09  201      (0324)
  173.   UINT32 sdctrl_data_cnt_h;                     // 0a  202      (0328)
  174.   UINT32 sdctrl_gclk_dis;                       // 0b  203      (032c)
  175.   UINT32 sdctrl_aref1_cfg;                      // 0c  204      (0330)
  176.   UINT32 sdctrl_int;                            // 0d  205      (0334)
  177.   UINT32 sdctrl_int_mask;                       // 0e  206      (0338)
  178.   UINT32 sdctrl_int_status;                     // 0f  207      (033c)
  179.   UINT32 sdctrl_lmem_base;                      // 10  208      (0340)
  180.   UINT32 sdctrl_lmem_row_st;                    // 11  209      (0344)
  181.   UINT32 g6_unused_0;                           // 12  210      (0348)
  182.   UINT32 sdctrl_cfg4;                           // 13  211      (034c)
  183.   UINT32 g6_reserved[10];                       // 14  212~ 223 (0350)
  184.   UINT32 sdctrl_misc_b0;                        // 1e
  185.   UINT32 sdctrl_misc_b1;                        // 1f
  187.   // GROUP 7: VPP Control
  188.   UINT32 dis_x_start;                           // 00  224 E0   (0380) $bffe8380
  189.   UINT32 dis_y_start;                           // 01  225 E1   (0384)
  190.   UINT32 dis_x_size;                            // 02  226 E2   (0388)
  191.   UINT32 dis_y_size;                            // 03  227 E3   (038c)
  192.   UINT32 v_offset;                              // 04  228 E4   (0390)
  193.   UINT32 h_offset;                              // 05  229 E5   (0394)
  194.   UINT32 vpp_bg_y;                              // 06  230 E6   (0398)
  195.   UINT32 vpp_bg_cb_cr;                          // 07  231 E7   (039c)
  196.   UINT32 v_filter0_setup;                       // 08  232 E8   (03a0)
  197.   UINT32 v_filter1_setup;                       // 09  233 E9   (03a4)
  198.   UINT32 h_filter_setup;                        // 0a  234 EA   (03a8)
  199.   UINT32 vpp_config;                            // 0b  235 EB   (03ac)
  200.   UINT32 vpp_config1;                           // 0c  236 EC   (03b0)
  201.   UINT32 ds_field_config;                       // 0d  237 ED   (03b4)
  202.   UINT32 dip_config;                            // 0e  238 EE   (03b8)
  203.   UINT32 dip_param;                             // 0f  239 EF   (03bc)
  204.   UINT32 dip_mv_ptr;                            // 10  240 F0   (03c0)
  205.   UINT32 vppref0_luma;                          // 11  241 F1   (03c4)
  206.   UINT32 vppref0_chroma;                        // 12  242 F2   (03c8)
  207.   UINT32 vppref1_luma;                          // 13  243 F3   (03cc)
  208.   UINT32 vppref1_chroma;                        // 14  244 F4   (03d0)
  209.   UINT32 vppbidir_luma;                         // 15  245 F5   (03d4)
  210.   UINT32 vppbidir_chroma;                       // 16  246 F6   (03d8)
  211.   UINT32 dip_ref_base;                          // 17  247 F7   (03dc)
  212.   UINT32 dip_param_threshold;                   // 18  248 F8   (03e0)
  213.   UINT32 dip_param_fading;                      // 19  249 F9   (03e4)
  214.   UINT32 vpp_act_region_top;                    // 1a  250 FA   (03e8)
  215.   UINT32 vpp_act_region_bottom;                 // 1b  251 FB   (03ec)
  216.   UINT32 vpp_spare_0;                           // 1c  252 FC   (03f0)
  217.   UINT32 vpp_clut_ay;                           // 1d  253 FD   (03f4)
  218.   UINT32 vpp_clut_uv;                           // 1e  254 FE   (03f8)
  219.   UINT32 vpp_spare_1;                           // 1f  255 FF   (03fc)
  221.   // GROUP 8: TV0
  222.   UINT32 tv_mode[6];                            // 00  256~ 261 (0400) $bffe8400
  223.   UINT32 tv_subc_f[2];                          // 06  262~ 263 (0418)
  224.   UINT32 tv_subc_p;                             // 08  264      (0420)
  225.   UINT32 tv_line_t[2];                          // 09  265~ 266 (0424)
  226.   UINT32 tv_line_b[2];                          // 0b  267~ 268 (042c)
  227.   UINT32 tv_cc_t;                               // 0d  269      (0434)
  228.   UINT32 tv_cc_b;                               // 0e  270      (0438)
  229.   UINT32 tv_cgms[2];                            // 0f  271~ 272 (043c)
  230.   UINT32 tv_id_status;                          // 11
  231.   UINT32 tv_dac[2];                             // 12~13
  232.   UINT32 tv_misc[12];                           // 14~1f
  234.   // GROUP 9: DSP24
  235.   UINT32 dsp24_control;                         // 00  288      (0480) $bffe8480
  236.   UINT32 dsp3dbg_mode;                          // 01  289      (0484)
  237.   UINT32 dsp3dbg_break;                         // 02  290      (0488)
  238.   UINT32 dsp3dbg_addr;                          // 03  291      (048c)
  239.   UINT32 dsp3dbg_step;                          // 04  292      (0490)
  240.   UINT32 dsp3dbg_rd_l;                          // 05  293      (0494)
  241.   UINT32 dsp3dbg_rd_h;                          // 06  294      (0498)
  242.   UINT32 dsp3dbg_wr_l;                          // 07  295      (049c)
  243.   UINT32 dsp3dbg_wr_h;                          // 08  296      (04a0)
  244.   UINT32 dsp3dbg_pc;                            // 09  297      (04a4)
  245.   UINT32 rom_l;                                 // 0a  298      (04a8)
  246.   UINT32 rom_h;                                 // 0b  299      (04ac)
  247.   UINT32 dsp24ya;                               // 0c  300      (04b0)
  248.   UINT32 pcmya;                                 // 0d  301      (04b4)
  249.   UINT32 audya;                                 // 0e  302      (04b8)
  250.   UINT32 g9_reserved;                           // 0f  303      (04bc)
  251.   UINT32 dsp24_port[16];                        // 10  304~ 319 (04c0)
  253.   // GROUP 10: OSD control 
  254.   UINT32 osd_tv_std;                            // 00  320      (0500) $bffe8500
  255.   UINT32 osd_tv_out;                            // 01  321      (0504)
  256.   UINT32 osd_mixer;                             // 02  322      (0508)
  257.   UINT32 osd_display_status;                    // 03  323      (050c)
  258.   UINT32 osd_en;                                // 04  324      (0510)
  259.   UINT32 osd_tlink_addr;                        // 05  325      (0514)
  260.   UINT32 osd_blink_addr;                        // 06  326      (0518)
  261.   UINT32 y_clip;                                // 07  327      (051c)
  262.   UINT32 cb_clip;                               // 08  328      (0520)
  263.   UINT32 osd_base_addr;                         // 09  329      (0524)
  264.   UINT32 osd_mode[12];                          // 0a  330~ 341 (0528)
  265.   
  266.   UINT32 g10_reserved[10];                      // 16  342~ 351 (0558)
  268.   // GROUP 11: Graphic control
  269.   UINT32 graph_mode;                            // 00  352      (0580) $bffe8580
  270.   UINT32 graph_status;                          // 01  353      (0584)
  271.   UINT32 dma_mode;                              // 02  354      (0588)
  272.   UINT32 dma_xaddr;                             // 03  355      (058c)
  273.   UINT32 dma_yaddr;                             // 04  356      (0590)
  274.   UINT32 dma_done;                              // 05  357      (0594)
  275.   UINT32 g11_reserved[26];                      // 06  358~ 383 (0598)
  277.   // GROUP 12: HOST
  278.   UINT32 g12_dvddsp_vy;                         // 00  384      (0600) $bffe8600
  279.   UINT32 g12_dvddsp_vx;                         // 01  385      (0604)
  280.   UINT32 dvddsp_function;                       // 02  386      (0608)
  281.   UINT32 dvddsp_ata_config;                     // 03  387      (060c)
  282.   UINT32 dvddsp_blocksize;                      // 04  388      (0610)
  283.   UINT32 dvddsp_blocklength;                    // 05  389      (0614)
  284.   UINT32 g12_dvddsp_ry;                         // 06  390      (0618)
  285.   UINT32 dvddsp_rx;                             // 07  391      (061c)
  286.   UINT32 dvddsp_public;                         // 08  392      (0620)
  287.   UINT32 dvddsp_ude_config;                     // 09  393      (0624)
  288.   UINT32 dvddsp_ata_pio_cycle;                  // 0a  394      (0628)
  289.   UINT32 dvddsp_ata_udma_cycle;                 // 0b  395      (062c)
  290.   UINT32 g12_reserved[4];                       // 0c  396~ 399 (0630)
  291.   UINT32 dvddsp_mon[4];                         // 10  400~ 403 (0640)
  292.   UINT32 g12_reserved1[12];                     // 14  404~ 415 (0650)
  294.   // GROUP 13: CSS
  295.   UINT32 css_tk0;                               // 00  416      (0680) $bffe8680
  296.   UINT32 css_tk1;                               // 01  417      (0684)
  297.   UINT32 css_tk2;                               // 02  418      (0688)
  298.   UINT32 css_tk3;                               // 03  419      (068c)
  299.   UINT32 css_tbyte;                             // 04  420      (0690)
  300.   UINT32 css_public;                            // 05  421      (0694)
  301.   UINT32 css_config;                            // 06  422      (0698)
  302.   UINT32 css_l0;                                // 07  423      (069c)
  303.   UINT32 css_l1;                                // 08  424      (06a0)
  304.   UINT32 css_r0;                                // 09  425      (06a4)
  305.   UINT32 css_r1;                                // 0a  426      (06a8)
  306.   UINT32 cppm_aukey3;                           // 0b  427      (06ac)
  307.   UINT32 cppm_aukey2;                           // 0c  428      (06b0)
  308.   UINT32 cppm_aukey1;                           // 0d  429      (06b4)
  309.   UINT32 cppm_aukey0;                           // 0e  430      (06b8)
  310.   UINT32 g13_reserved[17];                      // 0f  431~ 447 (06bc)
  312.   // GROUP 14:  IOP
  313.   UINT32 iop_control;                           // 00  448      (0700) $bffe8700
  314.   UINT32 iop_status;                            // 01  449      (0704)
  315.   UINT32 iop_bp;                                // 02  450      (0708)
  316.   UINT32 iop_regsel;                            // 03  451      (070c)
  317.   UINT32 iop_regout;                            // 04  452      (0710)
  318.   UINT32 iop_memlimit;                          // 05  453      (0714)
  319.   UINT32 g14_reserved[2];                       // 06  454~ 455 (0718)
  320.   UINT32 iop_data[8];                           // 08  456~ 463 (0720)
  321.   UINT32 g14_reserved1[16];                     // 10  464~ 479 (0740)
  323.   // GROUP 15:  SUP
  324.   UINT32 sup_fst_cmd_addr;                      // 00  480      (0780) $bffe8780
  325.   UINT32 sup_snd_cmd_addr;                      // 01  481      (0784)
  326.   UINT32 sup_h_size;                            // 02  482      (0788)
  327.   UINT32 sup_mode;                              // 03  483      (078c)
  328.   UINT32 sup_tv_mode;                           // 04  484      (0790)
  329.   UINT32 sup_panning;                           // 05  485      (0794)
  330.   UINT32 sup_aspect_ratio;                      // 06  486      (0798)
  331.   UINT32 sup_mon[5];                            // 07  487~ 491 (079c)
  332.   UINT32 sup_config;                            // 0c  492      (07b0)
  333.   UINT32 sup_buffer_limit;                      // 0d  493      (07b4)
  334.   UINT32 g15_reserved[18];                      // 0e  494~ 511 (07b8)
  336.   // GROUP 16
  337.   UINT32 g16_reserved[32];                      // 00  512~ 543 (0800) $bffe8800
  339.   // GROUP 17
  340.   UINT32 g17_reserved[32];                      // 00  544~ 575 (0880) $bffe8880
  342.   // GROUP 18:  UARTs
  343.   // UART0
  344.   UINT32 uart0_data;                            // 00  576      (0900) $bffe8900
  345.   UINT32 uart0_lsr;                             // 01  577      (0904)
  346.   UINT32 uart0_msr;                             // 02  578      (0908)
  347.   UINT32 uart0_lcr;                             // 03  579      (090c)
  348.   UINT32 uart0_mcr;                             // 04  580      (0910)
  349.   UINT32 uart0_div_l;                           // 05  581      (0914)
  350.   UINT32 uart0_div_h;                           // 06  582      (0918)
  351.   UINT32 uart0_isc;                             // 07  583      (091c)
  352.   // UART1
  353.   UINT32 uart1_data;                            // 08  584      (0920)
  354.   UINT32 uart1_lsr;                             // 09  585      (0924)
  355.   UINT32 uart1_msr;                             // 0a  586      (0928)
  356.   UINT32 uart1_lcr;                             // 0b  587      (092c)
  357.   UINT32 uart1_mcr;                             // 0c  588      (0930)
  358.   UINT32 uart1_div_l;                           // 0d  589      (0934)
  359.   UINT32 uart1_div_h;                           // 0e  590      (0938)
  360.   UINT32 uart1_isc;                             // 0f  591      (093c)
  361.   UINT32 g18_reserved[16];                      // 10  592~ 607 (0940)
  363.   // GROUP 19:  GPIO control
  364.   UINT32 gpio_master[4];                        // 00  608~ 611 (0980) $bffe8980
  365.   UINT32 gpio_oe[4];                            // 04  612~ 615 (0990)
  366.   UINT32 gpio_out[4];                           // 0c  616~ 619 (09a0)
  367.   UINT32 gpio_in[4];                            // 10  620~ 623 (09b0)
  368.   UINT32 gpio2_inout[2];                        // 10  624~ 625 (09c0)
  369.   UINT32 gpio2_oe[2];                           // 10  626~ 627 (09c8)
  370.   UINT32 g19_reserved1[12];                     // 14  628~ 639 (09d0)
  372.   // GROUP 20:  CDDSP
  373.   UINT32 cddsp_config;                          // 00  640      (0a00) $bffe8a00
  374.   UINT32 cddsp_control;                         // 01  641      (0a04)
  375.   UINT32 cddsp_mm_bcd;                          // 02  642      (0a08)
  376.   UINT32 cddsp_ss_bcd;                          // 03  643      (0a0c)
  377.   UINT32 cddsp_ff_bcd;                          // 04  644      (0a10)
  378.   UINT32 cddsp_status;                          // 05  645      (0a14)
  379.   UINT32 cddsp_mmss;                            // 06  646      (0a18)
  380.   UINT32 cddsp_ffmm;                            // 07  647      (0a1c)
  381.   UINT32 g20_reserved[24];                      // 08  648~ 671 (0a20)
  383.   // GROUP 21:  TV1
  384.   UINT32 tv_gamma[5];                           // 00  672      (0a80) $bffe8a80
  385.   UINT32 tv_pccon[18];                          // 01  673      (0a84)
  386.   UINT32 g21_reserved[9];                       // 04  676~ 703 (0a90)
  388.   // GROUP 22:  MBUS 
  389.   UINT32 mbus_bridge_config;                    // 00  704      (0b00) $bffe8b00
  390.   UINT32 evbya;                                 // 01  705      (0b04)
  391.   UINT32 osdya;                                 // 02  706      (0b08)
  392.   UINT32 cdwya;                                 // 03  707      (0b0c)
  393.   UINT32 cdrya;                                 // 04  708      (0b10)
  394.   UINT32 supya;                                 // 05  709      (0b14)
  396.   UINT32 evbya_limit;                           // 06  710      (0b18)
  397.   UINT32 osdya_limit;                           // 07  711      (0b1c)
  398.   UINT32 cdwya_limit;                           // 08  712      (0b20)
  399.   UINT32 cdrya_limit;                           // 09  713      (0b24)
  400.   UINT32 supya_limit;                           // 0a  714      (0b28)
  402.   UINT32 bs_ystop;                              // 0b  715      (0b2c)
  403.   UINT32 bs_ry;                                 // 0c  716      (0b30)
  404.   UINT32 bs_yinit;                              // 0d  717      (0b34)
  405.   UINT32 bs_xinit;                              // 0e  718      (0b38)
  406.   UINT32 dvddsp_vy;                             // 0f  719      (0b3c)
  407.   UINT32 dvddsp_vx;                             // 10  720      (0b40)
  408.   UINT32 dvddsp_ry;                             // 11  721      (0b44)
  410.   UINT32 cdr_vy;                                // 12  722      (0b48)
  411.   UINT32 cdr_vx;                                // 13  723      (0b4c)
  412.   UINT32 supya2;                                // 14  724      (0b50)
  413.   UINT32 supya2_limit;                          // 15  725      (0b54)
  415.   UINT32 iopya;                                 // 16  726      (0b58)
  416.   UINT32 cdrya_xlimit;                          // 17  727      (0b5c)
  418.   UINT32 g22_reserved[8];                       // 18  728~ 735 (0b60)
  420.   // GROUP 23: VPP2
  421.   UINT32 g23_vpp_contrast_adj[2];               // 00  736~ 737 (0b80) $bffe8b80
  422.   UINT32 g23_vpp_contrast_slope[3];             // 02  738~ 740 (0b88)
  423.   UINT32 g23_vpp_histogram[8];                  // 05  741~ 748 (0b94)
  424.   UINT32 g23_vpp_chksum;                        // 0d  749      (0bb4)
  425.   UINT32 g23_vpp_mv_ptr;                        // 0e  750      (0bb8)
  426.   UINT32 g23_vpp_hue_adj[2];                    // 0f  751~ 752 (0bbc)
  427.   UINT32 g23_reserved[15];                      // 11  753~ 767 (0bc4)
  429.   // GROUP 24: Buffer Control
  430.   UINT32 bufctl[8]
  431.   UINT32 g24_reserved[24];                      // 04  772~ 799 (0c10)
  433.   // GROUP 25: INVQ
  434.   UINT32 invq_qmx_par;                          // 00  800      (0c80) $bffe8c80
  435.   UINT32 invq_mode;                             // 01  801      (0c84)
  436.   UINT32 invq_chksum;                           // 02  802      (0c88)
  437.   UINT32 g25_reserved[29];                      // 03  803~ 831 (0c8c)
  439.   // GROUP 26: RI/ROM
  440.   UINT32 rom_config;                            // 00  832      (0d00) $bffe8d00
  441.   UINT32 wait_cyc1_0;                           // 01  833      (0d04)
  442.   UINT32 wait_cyc3_2;                           // 02  834      (0d08)
  443.   UINT32 oe_wait_cyc1_0;                        // 03  835      (0d0c)
  444.   UINT32 oe_wait_cyc3_2;                        // 04  836      (0d10)
  445.   UINT32 we_wait_cyc1_0;                        // 05  837      (0d14)
  446.   UINT32 we_wait_cyc3_2;                        // 06  838      (0d18)
  447.   UINT32 iochrdy_wait_cyc;                      // 07  839      (0d1c)
  448.   UINT32 rom1_base;                             // 08  840      (0d20)
  449.   UINT32 rom2_base;                             // 09  841      (0d24)
  450.   UINT32 rom3_base;                             // 0a  842      (0d28)
  451.   UINT32 pcmcia_iorw_wait;                      // 0b  843      (0d2c)
  452.   UINT32 pcmcia_ctrl;                           // 0c  844      (0d30)
  453.   UINT32 g26_reserved1[8];                      // 0d  845~ 852 (0d34)
  454.   UINT32 adt[4];                                
  455.   UINT32 dat[4];                                
  456.   UINT32 adm[2];
  457.   UINT32 dar;
  459.   // GROUP 27: System Bus Arbitrator
  460.   UINT32 sbar_config;                           // 00  864      (0d80) $bffe8d80
  461.   UINT32 sbar_prr[16];                          // 01  865~ 880 (0d84)
  462.   UINT32 g27_reserved[15];                      // 11  881~ 895 (0dc4)
  464.   // GROUP 28: Bridge
  465.   UINT32 rf_sdramif_tbya;                       // 00  896      (0e00) $bffe8e00
  466.   UINT32 rf_servo_band_en;                      // 01  897      (0e04)
  467.   UINT32 rf_servo_band_val;                     // 02  898      (0e08)
  468.   UINT32 g28_reserved[29];                      // 03  899~ 927 (0e0c)
  470.   // GROUP 29: Servo
  471.   UINT32 rf_regif_addr;                         // 00  928      (0e80) $bffe8e80
  472.   UINT32 rf_regif_wdata;                        // 01  929      (0e84)
  473.   UINT32 rf_regif_rdata;                        // 02  930      (0e88)
  474.   UINT32 rf_regif_sample_ctrl;                  // 03  931      (0e8c)
  475.   UINT32 rf_regif_intr_addr;                    // 04  932      (0e90)
  476.   UINT32 rf_regif_intr_wdata;                   // 05  933      (0e94)
  477.   UINT32 rf_regif_intr_rdata;                   // 06  934      (0e98)
  478.   UINT32 g29_reserved[25];                      // 07  935~ 959 (0e9c)
  480.   // GROUP 30: Emulation control
  481.   UINT32 emu_cfg[32];                           // 00  960~ 991 (0f00) $bffe8f00
  482.   
  483.   // GROUP 31: Audio hardware control
  484.   UINT32 aud_reset;                             // 00  992(3E0) (0f80) $bffe8f80
  485.   UINT32 aud_pcm_cfg;         // 01  993      (0f84)
  486.   UINT32 aud_spdif_cfg;         // 02  994      (0f88)
  487.   UINT32 aud_enable;         // 03  995      (0f8c)
  488.   UINT32 aud_adc_stereo_cfg;         // 04  996      (0f90)
  489.   UINT32 aud_adc_mono_cfg;         // 05  997      (0f94)
  490.   UINT32 aud_pcm_ramp_delta;         // 06  998      (0f98)
  491.   UINT32 aud_pcm_ramp_cfg;         // 07  999      (0f9c)
  492.   UINT32 aud_pcm_ramp_value;         // 08  1000     (0fa0)
  493.   UINT32 aud_spdif_period;         // 09  1001     (0fa4)
  494.   UINT32 aud_fifo_flag;         // 0a  1002     (0fa8)
  495.   UINT32 aud_chn_pcm_cnt[10];         // 0b~14
  496.   UINT32 aud_xck_cfg;         // 15  1013 (0fd4)
  497.   UINT32 aud_pcm_bck_cfg;         // 16  1014 (0fd8)
  498.   UINT32 aud_iec_bclk_cfg;         // 17  1015 (0fdc)
  499.   UINT32 aud_adc_mclk_cfg;         // 18  1016 (0fe0)
  500.   UINT32 aud_dsp_run_cnt;         // 19  1017 (0fe4)
  501.   UINT32 aud_dsp_stall_cnt;         // 1a  1018 (0fe8)
  502.   UINT32 aud_dsp_reset_flag;         // 1b  1019 (0fec)
  503.   UINT32 aud_dsp_dec_cnt_toggle;         // 1c  1020 (0ff0)
  504.   UINT32 aud_dsp_dec_cnt;         // 1d  1021 (0ff4)
  505.   UINT32 aud_fpga_v2[2];                        // 1e~1f
  506.   
  507.   // GROUP 32
  508.   UINT32 g32_reserved[32];                      // 00 1024~1055 (1000) $bffe9000
  509.   
  510.   // GROUP 33
  511.   UINT32 g33_reserved[32];                      // 00 1056~1087 (1080) $bffe9080
  512.   
  513.   // GROUP 34
  514.   UINT32 g34_reserved[32];                      // 00 1088~1119 (1100) $bffe9100
  515.   
  516.   // GROUP 35
  517.   UINT32 g35_reserved[32];                      // 00 1120~1151 (1180) $bffe9180
  518.   
  519.   // GROUP 36
  520.   UINT32 g36_reserved[32];                      // 00 1152~1183 (1200) $bffe9200
  521.   
  522.   // GROUP 37
  523.   UINT32 g37_reserved[32];                      // 00 1184~1215 (1280) $bffe9280
  525.   // GROUP 38
  526.   UINT32 g38_reserved[32];                      // 00 1216~1247 (1300) $bffe9300
  528.   // GROUP 39
  529.   UINT32 g39_reserved[32];                      // 00 1248~1279 (1380) $bffe9380
  530.   
  531.   // GROUP 40: (EMU) SDRAM 6B
  532.   UINT32 sdc_req_t_reset;                       // 00 1280      (1400) $bffe9400
  533.   UINT32 sdc_req_time[14][2];                   // 01 1281~1308
  534.   UINT32 g40_reserved[3];                       // 1d 1309~1311 (1474)
  536.   // GROUP 41: (EMU) SDRAM 6A
  537.   UINT32 sdc_data_cnt[14][2];                   // 00 1312~1339 (0520) $bffe9480
  538.   UINT32 sdc_n_req_cnt[2];                      // 1c 1340~1341 (14f0)
  539.   UINT32 sdc_cke_cnt[2];                        // 1e 1342~1343 (14f8)
  541.   // GROUP 42~49
  542.   UINT32 g42_reserved[32];                      // 00 1344~1375 (1500) $bffe9500
  543.   UINT32 g43_reserved[32];                      // 00 1376~1407 (1580) $bffe9580
  544.   UINT32 g44_reserved[32];                      // 00 1408~1439 (1600) $bffe9600
  545.   UINT32 g45_reserved[32];                      // 00 1440~1471 (1680) $bffe9680
  546.   UINT32 g46_reserved[32];                      // 00 1472~1503 (1700) $bffe9700
  547.   UINT32 g47_reserved[32];                      // 00 1504~1535 (1780) $bffe9780
  548.   UINT32 g48_reserved[32];                      // 00 1536~1567 (1800) $bffe9800
  549.   UINT32 g49_reserved[32];                      // 00 1568~1599 (1880) $bffe9880
  551.   // GROUP 50
  552.   UINT32 g50_reserved[29];                      // 00 1600~1628 (1900) $bffe9900
  553.   UINT32 risc_fpga_version[3];                  // 1d 1629~1631 (1974)
  555.   // GROUP 51
  556.   UINT32 g51_reserved[29];                      // 00 1632~1660 (1980) $bffe9980
  557.   UINT32 block_fpga_version[3];                 // 1d 1661~1663 (19f4)
  559.   // GROUP 52
  560.   UINT32 g52_reserved[29];                      // 00 1664~1692 (1a00) $bffe9a00
  561.   UINT32 aud_fpga_version[3];                   // 1d 1693~1695 (1a74)
  563.   // GROUP 53~63
  564.   UINT32 g53_reserved[32];                      // 00 1696~1727 (1a80) $bffe9a80
  565.   UINT32 g54_reserved[32];                      // 00 1728~1759 (1b00) $bffe9b00
  566.   UINT32 g55_reserved[32];                      // 00 1760~1791 (1b80) $bffe9b80
  567.   UINT32 g56_reserved[32];                      // 00 1792~1823 (1c00) $bffe9c00
  568.   UINT32 g57_reserved[32];                      // 00 1824~1855 (1c80) $bffe9c80
  569.   UINT32 g58_reserved[32];                      // 00 1856~1887 (1d00) $bffe9d00
  570.   UINT32 g59_reserved[32];                      // 00 1888~1919 (1d80) $bffe9d80
  571.   UINT32 g60_reserved[32];                      // 00 1920~1951 (1e00) $bffe9e00
  572.   UINT32 g61_reserved[32];                      // 00 1952~1983 (1e80) $bffe9e80
  573.   UINT32 g62_reserved[32];                      // 00 1984~2015 (1f00) $bffe9f00
  574.   UINT32 g63_reserved[32];                      // 00 2016~2047 (1f80) $bffe9f80
  576.   // GROUP 64~255
  577.   UINT32 gxx_reserved[192][32];                 // 00 2048~8191 (0800) $bffea000
  579.   // GROUP
  580.   WorkBuf reg_dma_buf;
  581.   WorkBuf reg_dma_buf256;
  582.   WorkBuf reg_dma_buf512;
  583.   WorkBuf reg_dma_buf768;
  585.   //
  586.   // (OLD hardware, just for compatible issue)
  587.   //
  588. //  UINT32 evbya2;                                // 00 8192      (8000) $bfff0000
  589. //  UINT32 eabya;                                 // 01 8193      (8004)
  590. //  UINT32 dsp16ya;                               // 02 8194      (8008)
  591. //  UINT32 dma_addrmode;                          // 03 8195      (800c)
  592. //  UINT32 dma_addrlen;                           // 04 8196      (8010)
  593. //  UINT32 epp_status;                            // 05 8197      (8014)
  594. //  UINT32 epp_data;                              // 06 8198      (8018)
  595. //  UINT32 agdc_config;                           // 07 8199      (801c)
  596. //  UINT32 video_compress;                        // 08 8200      (8020)
  597. //  UINT32 dis_tv_out;                            // 09 8201      (8024)
  598. //  UINT32 audio_clkgen;                          // 05    5      (0014)
  599.   
  600. } RegisterFile;
  603. /*
  604. **  Video
  605. */
  606. #define RF_CODING_EXT0_PROGRESSIVE_FRAME (1<<0)
  607. #define RF_CODING_EXT0_CHROMA_420_TYPE (1<<1)
  608. #define RF_CODING_EXT0_REPEAT_FIRST_FIELD (1<<2)
  609. #define RF_CODING_EXT0_ALTERNATE_SCAN (1<<3)
  610. #define RF_CODING_EXT0_INTRA_VLC_FORMAT (1<<4)
  611. #define RF_CODING_EXT0_Q_SCALE_TYPE (1<<5)
  612. #define RF_CODING_EXT0_CONCEAL_MOTION_VECTORS (1<<6)
  613. #define RF_CODING_EXT0_FRAME_PRED_FRAME_DCT (1<<7)
  614. #define RF_CODING_EXT0_TOP_FIELD_FIRST (1<<8)
  615. #define RF_CODING_EXT0_PICTURE_STRUCTURE (0x03<<9)
  616. #define RF_CODING_EXT0_INTRA_DC_PRECISION (0x03<<11)
  617. //#define RF_CODING_EXT0_LAST_PICTURE (1<<14)
  618. #define RF_CODING_EXT0_BACK_LAST (1<<14)
  619. #define RF_CODING_EXT0_SECOND_FIELD (1<<15)
  621. #define ext0_pic_struct(x) (((x)>>9)&0x03)
  623. /*
  624. ** Display Output Tweaking
  625. */
  626. #define RF_VOUT_SWAP_CBCR (1<<1)
  627. #define RF_VOUT_SWAP_LC (1<<2)
  629. /*
  630. **  Display Status
  631. */
  632. #define RF_Display_OSDRegion 0x00ff
  633. #define RF_Display_FieldNo 0x8000
  634. #define RF_Display_VSyncB 0x4000
  635. #define RF_Display_HSyncB 0x2000
  636. #define RF_Display_FieldEnd 0x1000
  638. #define DISPLAY_STATUS                  regs0->osd_display_status
  639. #define IsVSync()                       ((DISPLAY_STATUS & RF_Display_VSyncB)==0)
  640. #define IsHSync()                       ((DISPLAY_STATUS & RF_Display_HSyncB)==0)
  641. #define IsTopField()                    ((DISPLAY_STATUS & RF_Display_FieldNo)==0)
  642. #define IsBottomField()                 ((DISPLAY_STATUS & RF_Display_FieldNo))
  643. #define IsFieldEnd()                    ((DISPLAY_STATUS & RF_Display_FieldEnd))
  645. #define RF_Video_VPicEnd 0x0001
  646. #define RF_Video_VTblErr 0x0002
  647. #define RF_Video_VRunErr 0x0004
  648. #define RF_Video_VSliceErr 0x0008
  649. #define RF_Video_VErr 0x8000
  651. /*
  652. ** RISC Picture Start
  653. */
  654. #define IsRPicStart (regs0->pic_start)
  656. /*
  657. ** VLD Decoding Status
  658. */
  659. #define VLD_STATUS                      (regs0->vld_status)
  660. #define IsVPicEnd                       (VLD_STATUS & RF_Video_VPicEnd)
  661. #define IsVRunErr                       (VLD_STATUS & RF_Video_VRunErr)
  662. #define IsVTblErr                       (VLD_STATUS & RF_Video_VTblErr)
  663. #define IsVErr                          (VLD_STATUS & RF_Video_VErr)
  665. #define RF_CODING_EXT1_FORWARD_REF0 (0<<1)
  666. #define RF_CODING_EXT1_FORWARD_REF1 (1<<1)
  668. #define RF_CODING_EXT1_RECONST_REF0 (0<<2)
  669. #define RF_CODING_EXT1_RECONST_REF1 (1<<2)
  670. #define RF_CODING_EXT1_RECONST_B (2<<2)
  672. #define RF_CODING_EXT1_FIELDID (1<<4)
  675. //
  676. // TIMER TIMER TIMER TIMER TIMER TIMER TIMER
  677. //
  678. #define RF_TIMER_SRC_SYSCLK (0<<14)
  679. #define RF_TIMER_SRC_STC (1<<14)
  680. #define RF_TIMER_SRC_RTC (2<<14)
  681. #define RF_TIMER_SRC_TIMER (3<<14)
  682. #define RF_TIMER_RUN_ON (1<<13)
  683. #define RF_TIMER_RUN_OFF (0<<13)
  684. #define RF_TIMER_GO_ON (1<<11)
  685. #define RF_TIMER_GO_OFF (0<<11)
  686. #define RF_TIMER_MASK (0x3ff)
  688. #define TIMER_CONFIG_STOP ( RF_TIMER_GO_OFF )
  689. #define TIMER_CONFIG_STC ( RF_TIMER_SRC_STC
  690. | RF_TIMER_RUN_ON
  691. | RF_TIMER_GO_ON)
  693. #define TIMER_CONFIG_10ms ( TIMER_CONFIG_STC | (900-1))
  694. #define TIMER_CONFIG_4ms ( TIMER_CONFIG_STC | (360-1))
  695. #define TIMER_CONFIG_1ms ( TIMER_CONFIG_STC | (90-1))
  697. #define TIMER_CONFIG_dly ( RF_TIMER_SRC_STC
  698.      | RF_TIMER_RUN_OFF
  699. | RF_TIMER_GO_ON)
  701. #define TIMER_CONFIG_dlys(n) ( TIMER_CONFIG_dly | (n-1))
  702. #define TIMER_CONFIG_90k(n) ( TIMER_CONFIG_STC | (n-1))
  705. /*
  706. ** VPP VPP VPP VPP VPP VPP VPP
  707. */
  708. #define RF_HFACTOR_HEXP_ENABLE (1<<8)
  709. #define RF_HFACTOR_CIF_ENABLE (1<<9)
  712. /*
  713. **  CDDSP Control/Status
  714. */
  715. #define RF_CDDSP_RESET 0x0001
  716. #define RF_CDDSP_STOP 0x0002
  717. #define RF_CDDSP_PAUSE 0x0004
  718. #define RF_CDDSP_SEEK 0x0008
  720. #define RF_CDDSP_CRC_ERROR 0x0001
  721. #define RF_CDDSP_CRC_ERROR_LAST 0x0002
  722. #define RF_CDDSP_CRC_ERROR_MASK 0x0003
  724. /*
  725. **
  726. */
  727. #define RF_DSP24_RESET (1<<0)
  728. #define RF_DSP24_STALL (1<<1)
  730. /*
  731. ** EPP status
  732. */
  733. #define RF_EPP_IN_FULL (1<<3)
  734. #define RF_EPP_IN_EMPTY (1<<2)
  735. #define RF_EPP_OUT_FULL (1<<1)
  736. #define RF_EPP_OUT_EMPTY (1<<0)
  738. #define RF_Video_MPEG2_flag 0x08
  741. /*
  742. ** AGDC config
  743. */
  744. #define RF_AGDC_BPIC_LOC_RIGHT (0 << 0)
  745. #define RF_AGDC_BPIC_LOC_BOTTOM (1 << 0)
  746. #define RF_AGDC_BPIC_SIZE_LINE (0 << 2)
  747. #define RF_AGDC_BPIC_SIZE_FIELD (1 << 2)
  748. #define RF_AGDC_BPIC_SIZE_FULL (2 << 2)
  749. #define RF_AGDC_SDRAM_64MB (0 << 6)
  750. #define RF_AGDC_SDRAM_16MB (1 << 6)
  752. #define set_dis_tv_std(n) (regs0->osd_tv_std=(n))
  755. /*
  756. ** VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO VIDEO
  757. */
  758. #define RF_COMPRESS_888 (0 << 0)
  759. #define RF_COMPRESS_866 (1 << 0)
  760. #define RF_COMPRESS_666 (2 << 0)
  761. #define RF_COMPRESS_8655 (3 << 0)
  762. #define RF_COMPRESS_DITHER_ON (1 << 7)
  763. #define RF_COMPRESS_DITHER_OFF (0 << 7)
  764. #define RF_COMPRESS_CHROMA_FULL (0 << 8)
  765. #define RF_COMPRESS_CHROMA_HALF (1 << 8)
  767. /*
  768. ** regs0: register file pointer
  769. */
  770. #ifdef  GLOBAL_REGISTER
  771. register volatile       RegisterFile    *regs0  asm ("22"); 
  772. #define InitRegFile()   (regs0 = (volatile RegisterFile *)RGST_OFFSET)
  773. #else
  774. #define regs0           ((volatile RegisterFile *)RGST_OFFSET)
  775. #define InitRegFile()   {}
  776. #endif
  778. #endif/*__REGMAP_DVD_H*/