I24BCD.VHD
上传用户:dgjihui88
上传日期:2013-07-23
资源大小:43k
文件大小:2k
源码类别:
VHDL/FPGA/Verilog
开发平台:
MultiPlatform
- --The IEEE standard 1164 package, declares std_logic, rising_edge(), etc.
- library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- use IEEE.std_logic_unsigned.all;
- entity i24bcd is
- port (interg : in integer range 0 to 23;--interger number
- ten : out std_logic_vector (3 downto 0) ;--decimal bit
- one : out std_logic_vector (3 downto 0) );--individual bit
- end i24bcd;
- architecture arch of i24bcd is
- begin
- with interg select
- one<="0000" when 0,
- "0001" when 1,
- "0010" when 2,
- "0011" when 3,
- "0100" when 4,
- "0101" when 5,
- "0110" when 6,
- "0111" when 7,
- "1000" when 8,
- "1001" when 9,
- "0000" when 10,
- "0001" when 11,
- "0010" when 12,
- "0011" when 13,
- "0100" when 14,
- "0101" when 15,
- "0110" when 16,
- "0111" when 17,
- "1000" when 18,
- "1001" when 19,
- "0000" when 20,
- "0001" when 21,
- "0010" when 22,
- "0011" when 23,
- "1110" when others;--error input
- with interg select
- ten<="0000" when 0,
- "0000" when 1,
- "0000" when 2,
- "0000" when 3,
- "0000" when 4,
- "0000" when 5,
- "0000" when 6,
- "0000" when 7,
- "0000" when 8,
- "0000" when 9,
- "0001" when 10,
- "0001" when 11,
- "0001" when 12,
- "0001" when 13,
- "0001" when 14,
- "0001" when 15,
- "0001" when 16,
- "0001" when 17,
- "0001" when 18,
- "0001" when 19,
- "0010" when 20,
- "0010" when 21,
- "0010" when 22,
- "0010" when 23,
- "1110" when others;--error input
- end arch;