VHDL/FPGA/Verilog

开发平台：

MultiPlatform

TRAFFIC_LIB.VHD：源码内容

							--declaraction of package traffic_lib including component "clk_gen" 
--"traffic_mux" "count_down" "traffic_fsm"
library ieee;
use ieee.std_logic_1164.all;
package traffic_lib is
  component clk_gen 
   port(reset: in std_logic;
        clk:in std_logic;
        ena_scan:out std_logic;
        ena_1Hz:out std_logic;
        flash_1Hz: out std_logic);
  end component;
  
  component traffic_mux
  port(reset: in std_logic;
       clk:in std_logic;
       ena_scan:in std_logic;
       recount:in std_logic; 
       sign_state: in std_logic_vector(1 downto 0);
       load: out std_logic_vector(7 downto 0));
  end component;
  
  component count_down
    port(reset: in std_logic;
         clk:in std_logic;
         ena_1Hz:in std_logic;
         recount:in std_logic;
         load: in std_logic_vector(7 downto 0);
         seg7:out std_logic_vector(15 downto 0);
         next_state: out std_logic);
  end component;
  
  component traffic_fsm
  port(reset:in std_logic;
       clk:in std_logic;
       ena_scan:in std_logic;
       ena_1Hz:in std_logic;
       flash_1Hz:in std_logic;
       a_m:in std_logic;
       st_butt:in std_logic;
       next_state: in std_logic;
       recount: out std_logic;
       sign_state: out std_logic_vector(1 downto 0);
       red: out std_logic_vector(1 downto 0);
       green: out std_logic_vector(1 downto 0);
       yellow: out std_logic_vector(1 downto 0));
  end component;
end traffic_lib;
     

						