VHDL/FPGA/Verilog

开发平台：

MultiPlatform

KEY_SCAN.VHD：源码内容

							
--key_scan.vhd keypress scaner
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.components.all;
entity key_scan is
port(
  col : in std_logic_vector(3 downto 0);--keybord column state
  scan_cnt : in std_logic_vector(3 downto 0);--keybord scan location
  row : out std_logic_vector(3 downto 0);--keybord row state
  key_pressed : out std_logic);--key_pressed->0 unkey_pressed->1
end key_scan;
architecture behavior of key_scan is
begin 
  row<="1110" when scan_cnt(3 downto 2)="00" else--row scan
       "1101" when scan_cnt(3 downto 2)="01" else
       "1011" when scan_cnt(3 downto 2)="10" else
       "0111";
  key_pressed<=col(0) when scan_cnt(1 downto 0)="00" else--colum scan
               col(1) when scan_cnt(1 downto 0)="01" else
               col(2) when scan_cnt(1 downto 0)="10" else
               col(3);
end behavior;

						