NEGATIVE.VHD
上传用户:dgjihui88
上传日期:2013-07-23
资源大小:43k
文件大小:1k
源码类别:
VHDL/FPGA/Verilog
开发平台:
MultiPlatform
- --negative.vhd correct negative number circuit
- library ieee ;
- use ieee.std_logic_1164.all;
- use work.components.all;
- entity negative is
- port(
- a : in std_logic_vector(11 downto 0);--块