VHDL/FPGA/Verilog

开发平台：

MultiPlatform

STOP_WATCH.VHD：源码内容

							----libray and package declaraction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
----input and output pins declaraction
Entity stop_watch is
  Port(rst,hz1: in std_logic;--system clock 1Hz
      stop: in std_logic;--keep pushing to declare stop setting
      ok: in std_logic;--keep pushing to declare stop setting
      sec_tune: in std_logic;--pushing button to tune seconds
      min_tune: in std_logic;--pushing button to tune minutes
      hour_tune: in std_logic;--pushing button to tune hours
      stop_sec,stop_min: out integer range 0 to 59;
      stop_hour: out integer range 0 to 23;      
      index: out std_logic;      
      disp: out std_logic);           
End stop_watch;
architecture arch of stop_watch is
  signal a_sec,a_min: integer range 0 to 59;
  signal a_hour: integer range 0 to 23; 
begin
  process(stop,ok,hz1)
  begin
    if rst='1' then index<='0'; disp<='0';
    elsif rising_edge(hz1) then
       if stop='1' and ok='0' then --setting
          if sec_tune='1' then 
             if a_sec=59 then a_sec<=0;
                         else a_sec<=a_sec + 1;
             end if;
          end if;
          if min_tune='1' then 
             if a_min=59 then a_min<=0;
                         else a_min<=a_min + 1;
             end if;
          end if;
          if hour_tune='1' then
             if a_hour=23 then a_hour<=0;
                          else a_hour<=a_hour + 1;
             end if;
          end if;
          disp<='1';
       elsif stop='1' and ok='1'then --down counting
             if a_sec=0 then 
                if a_min=0 then 
                   if a_hour=0 then index<='1';
                                    disp<='0';  
                               else a_hour<=a_hour - 1;
                                    a_min<=59;
                                    a_sec<=59;
                   end if;
                           else a_min<=a_min - 1;
                                a_sec<=59;
                end if;
                        else a_sec<=a_sec - 1;
                             index<='0';
                             disp<='1';      
             end if;
        else disp<='0';
      end if;
    end if;
  end process;   
  stop_sec<=a_sec;
  stop_min<=a_min;
  stop_hour<=a_hour;
end arch;

						