TRAFFIC_FSM.VHD
上传用户:dgjihui88
上传日期:2013-07-23
资源大小:43k
文件大小:6k
源码类别:
VHDL/FPGA/Verilog
开发平台:
MultiPlatform
- LIBRARY IEEE;
- USE IEEE.std_logic_1164.all;
- USE IEEE.std_logic_arith.all;
- USE IEEE.std_logic_unsigned.all;
- entity traffic_FSM is
- port(reset:in std_logic;
- clk:in std_logic;
- ena_scan:in std_logic;
- ena_1Hz:in std_logic;
- flash_1Hz:in std_logic;
- a_m:in std_logic;
- st_butt:in std_logic;
- next_state: in std_logic;
- recount: out std_logic;
- sign_state: out std_logic_vector(1 downto 0);
- red: out std_logic_vector(1 downto 0);
- green: out std_logic_vector(1 downto 0);
- yellow: out std_logic_vector(1 downto 0));
- end;
- architecture BEHAVIOR of traffic_FSM is
- type Sreg0_type is (r0g1, r0y1, g0r1, y0r1, y0y1, y0g1, g0y1, r0r1);
- signal state: Sreg0_type;
- signal st_transfer: std_logic;
- signal light: std_logic_vector(5 downto 0); -- r(10)y(10)g(10)
- begin
- rebounce:process (reset,clk,ena_scan,st_butt)
- variable rebn_ff: std_logic_vector(5 downto 0);
- begin
- if (st_butt='1' or reset='1') then
- rebn_ff := "111111";
- st_transfer <='0';
- elsif (clk'event and clk='1') then
- if (ena_scan='1') then
- if (rebn_ff >= 3) then
- rebn_ff := rebn_ff-1;
- st_transfer<='0';
- elsif (rebn_ff=2) then
- rebn_ff := rebn_ff-1;
- st_transfer <='1';
- else
- rebn_ff := rebn_ff;
- st_transfer <='0';
- end if;
- end if;
- end if;
- end process;
- FSM: process (clk,ena_1Hz,reset)
- begin
- if (reset='1') then
- state<=r0g1; -- red=2'b01; green=2'b10; yellow=2'b00;
- sign_state<="01";
- recount<='1';
- else
- if (clk'event and clk='1') then
- case STATE is
- when r0g1 => -- now state: red0 on green1 on
- if (a_m='1' and ena_1Hz='1') then
- if (next_state = '1') then
- recount<='1';
- state<=r0y1;
- sign_state <= "01";
- else
- recount<='0';
- state<=r0g1; --red=2'b01; green=2'b10; yellow=2'b00;
- end if;
- elsif (a_m='0' and ena_scan='1') then
- if (st_transfer='0') then -- 0: unchange 1:transfer light state
- recount<='1';
- state<=r0g1;
- else
- recount<='1';
- state<=r0y1;
- sign_state <= "01";
- end if;
- end if;
- when r0y1 => -- now state: red0 on yellow1 flash
- if (a_m='1' and ena_1Hz='1') then
- if (next_state = '1') then
- recount<='1';
- state<=g0r1;
- sign_state <= "10";
- else
- recount<='0';
- state<=r0y1; -- red=2'b01; green=2'b00; yellow=2'b10;
- end if;
- elsif (a_m='0' and ena_scan='1') then
- if (st_transfer='0') then -- 0: unchange 1:transfer light state
- recount<='1';
- state<=r0y1;
- else
- recount<='1';
- state<=g0r1;
- sign_state <= "10";
- end if;
- end if;
- when g0r1 => -- now state: green0 on red1 on
- if (a_m='1' and ena_1Hz='1') then
- if (next_state = '1') then
- recount<='1';
- state<=y0r1;
- sign_state <= "11";
- else
- recount<='0';
- state<=g0r1; -- red=2'b10; green=2'b01; yellow=2'b00;
- end if;
- elsif (a_m='0' and ena_scan='1') then
- if (st_transfer='0') then -- 0: unchange 1:transfer light state
- recount<='1';
- state<=g0r1;
- else
- recount<='1';
- state<=y0r1;
- sign_state <= "11"; --
- end if;
- end if;
- when y0r1 => -- now state: green0 on red1 on
- if (a_m='1' and ena_1Hz='1') then
- if (next_state = '1') then
- recount<='1';
- state<=r0g1;
- sign_state <= "00";
- else
- recount<='0';
- state<=y0r1; -- red=2'b10; green=2'b00; yellow=2'b01;
- end if;
- elsif (a_m='0' and ena_scan='1') then
- if (st_transfer='0') then -- 0: unchange 1:transfer light state
- recount<='1';
- state<=y0r1;
- else
- recount<='1';
- state<=r0g1;
- sign_state <= "00"; --
- end if;
- end if;
- when others =>
- state<=r0g1;
- recount<='0';
- sign_state <= "00";
- end case;
- end if;
- end if;
- end process;
- -- light: r(10)y(10)g(10)
- light <= "010010" when (state=r0g1) else
- "011000" when (state=r0y1) else
- "100001" when (state=g0r1) else
- "100100" when (state=y0r1) else
- "110000";
- red <= light(5 downto 4);
- yellow <= light(3 downto 2) and (flash_1Hz & flash_1Hz);
- green <= light(1 downto 0);
- end BEHAVIOR;