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AIC.rar
使用FPGA/CPLD设置语音AD、DA转换芯片AIC23,FPGA/CPLD系统时钟为24.576MHz
1、AIC系统时钟为12.288MHz,SPI时钟为6.144MHz
2、AIC处于主控模式
3、input bit length 16bit output bit length 16bit MSB first
4、帧同步在96KHz
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I2C.rar
I2C core code in Hardware descrption language so as enable a cpld/fpga to be programmed for specific customized applications of our requirment & make the pcb work to meet the application requirements.
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serial.rar
... 串口处于全双工工作状态,按动SW0,CPLD向PC发送“welcome"
--字符串(串口调试工具设成按ASCII码接受方式);PC可随时向CPLD发送0-F的十六进制
--数据,CPLD ...
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