VHDL 源码搜索结果, 第78页, Verysource

A-Simplified-VHDL-UART.rar ... will need to interface to the processor. In this lab we will design a simplified UART (Universal Asynchronous Reciever Transmitter) in VHDL and download it to the FPGA on the XS40 baord. Serial communication is often used either to control or to receive ...
vhdl-golden-reference-guide.rar 一本介绍vhdl的经典黄金指导书，附有详细的实验代码
vhdl-program-for-seven-segment-display.rar seven segment code using vhdl
comparator-using-vhdl.rar vhdl code for comparator
Xilinx-ISE-Simulator-(ISim)-VHDL-Test-Bench-Tutor Xilinx ISE Simulator (ISim) VHDL Test Bench Tutorial
VHDL.rar 3-8译码器与程序 164译码器时钟编程的VHDL程序
VHDL-.rar VHDL的学习方案过程学习指导实验方案
VHDL-routines.rar 滤波器设计模数转换多数表决器任意整数模的VHDL例程
VHDL-digital-clock-.zip VHDL编写的数字钟，采用元件例化的方法，可实现调秒调分调时报时闹铃的功能开发板使用的是EP3C16Q240C8
RC6-block-cipher-using-VHDL.rar VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped