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50973937-VHDL-Report.rar
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VHDL/FPGA/Verilog

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资源说明：Introduction This report is organized as following.First, it is divided into chapter 2 to chapter 12. Within each chapter, VHDL code is presented at the beginning of each problem. Then, simulation results for these codes is also included. For some problems, more than one solution is presented. Second, a conclusion is made about the main confronts that I have faced. Finally, a list of refrences is included. Regarding the software tools, ISE 9.2i Design suite is used. However, due to bugs introduced with ISE Simulator 9.2i. I have upgradted to the next version ISE Design suite 10.1. Sometimes, ModelSim is also used for checking some codes. With respect to FPGA, All the codes are synthesized and implementedsome of them- for Spartan3an xc3s700AN. The same kind of FPGA we have within our lab
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