-
-
-
sd_IP.rar
SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). ...
-
-
-
-
-
sound.rar
AD转换代码 HDG12864L-6 LCD: 128x64 Grighic，SED1565 controller
-
systemforcatchingfastmovingobjectsbyvision.rar
...
time delays introduced by visual processing and by the
robot controller. A simple but reliable model of the
robot controller has been taken into account in the
control architecture for improving the performance of the
system. Experimental ...
-
-
-
Go To English Version 超过100万源码资源，1000万源码文件免费下载
