English
资源说明：Abstract—Low-Density Parity Check (LDPC) error correction
decoders have become popular in communications systems, as
a benefit of their strong error correction performance and
their suitability to parallel hardware implementation. A great
deal of research effort has been invested into LDPC decoder
designs that exploit the flexibility, the high processing speed
and the parallelism of Field-Programmable Gate Array (FPGA)
devices. FPGAs are ideal for design prototyping and for the
manufacturing of small-production-run devices, where their insystem
programmability makes them far more cost-effective
than Application-Specific Integrated Circuits (ASICs). However,
the FPGA-based LDPC decoder designs published in the open
literature vary greatly in terms of design choices and performance
criteria, making them a challenge to compare. This paper
explores the key factors involved in FPGA-based LDPC decoder
design and presents an extensive review of the current literature.
In-depth comparisons are drawn amongst 140 published designs
(both academic and industrial) and the associated performance
trade-offs are characterised, discussed and illustrated. Seven key
performance characteristics are described, namely their processing
throughput, processing latency, hardware resource requirements,
error correction capability, processing energy efficiency,
bandwidth efficiency and flexibility. We offer recommendations
that will facilitate fairer comparisons of future designs, as well
as opportunities for improving the design of FPGA-based LDPC
decoders.
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