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uart.rar
uart - universal asynchronous receicer and transmitter source code using VHDL
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UART.rar
the uart transmitter and receiver are used to design the data transmission for 8bit sipo and piso in verilog
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uart.rar
the uart model is used to design the synthies and beherival model in verilog fpga
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uart.rar
UART模块提供了一个全双工标准接口,用于完成SPCE061A与外设之间的串行通讯。借助于IOB口的特殊功能和UART IRQ中断,可以同时完成UART接口的接收发送数据的过程。
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