开通博客赚积分
发布资源赚积分
分类

源码开发语言/平台
当前位置：首页 > 源码/资料 > 压缩解压 > 查看源码
ExtCodec.c
资源名称：SDK_M5661.rar　[点击查看]
上传用户：hjhsjcl
上传日期：2020-09-25
资源大小：11378k
文件大小：17k
源码类别：

压缩解压

开发平台：

C++ Builder

ExtCodec.c：源码内容
  1. /*==========================================================================
  2. Copyright (c) 2004 ALi Corporation. All Rights Reserved
  4. File: Codec.c
  6. content: Audio Codec Functions
  8. History: Created by David Chiu 2004/4/29
  9. ==========================================================================*/
  10. #define _EXT_CODEC_H_
  13. #include <DP8051XP.H>
  14. #include "TypeDef.h"
  15. #include "Const.h"
  16. #include "Reg5661.h"
  17. #include "Common.h"
  18. #include "Idma.h"
  19. #include "ExtCodec.h"
  20. #if(!EXT_ADC | !EXT_DAC | EXT_PA)
  21. #include "IntCodec.h"
  22. #endif
  24. #if(EXT_ADC | EXT_DAC | EXT_PA)
  25. void CdcWriteCmd(BYTE bAddr, BYTE bData) large;
  27. #if(CDC_WM_8731)
  28. #define CDC_DEVICE_ADDRESS 0x34 //Wolfson WM8731
  29. #define WM_L_LINE_IN 0x00 //WM8731 Register address
  30. #define WM_LR_LINE_IN 0x01
  31. #define WM_R_LINE_IN 0x02
  32. #define WM_RL_LINE_IN 0x03
  33. #define WM_L_PHONE_OUT 0x04
  34. #define WM_LR_PHONE_OUT 0x05
  35. #define WM_R_PHONE_OUT 0x06
  36. #define WM_RL_PHONE_OUT 0x07
  37. #define WM_ANG_CTRL 0x08
  38. #define WM_DIG_CTRL 0x0A
  39. #define WM_PW_CTRL 0x0C
  40. #define WM_DIG_FORMAT 0x0E
  41. #define WM_SAMPLE_CTRL 0x10
  42. #define WM_ACTIVE_CTRL 0x12
  43. #define WM_RESET_REG 0x1E
  44. #endif
  46. #if(CDC_WM_8750)
  47. #define CDC_DEVICE_ADDRESS 0x34 //Wolfson WM8750
  48. #define WM_L_LINE_IN 0x00 //WM8750 Register address
  49. #define WM_LR_LINE_IN 0x01
  50. #define WM_R_LINE_IN 0x02
  51. #define WM_RL_LINE_IN 0x03
  52. #define WM_L_PHONE_OUT 0x04
  53. #define WM_LR_PHONE_OUT 0x05
  54. #define WM_R_PHONE_OUT 0x06
  55. #define WM_RL_PHONE_OUT 0x07
  56. #define WM_AD_DA_CTRL 0x0A
  57. #define WM_AUD_IF 0x0E
  58. #define WM_SAMPLE_RATE 0x10
  59. #define WM_L_DAC_VOL 0x14
  60. #define WM_LR_DAC_VOL 0x15
  61. #define WM_R_DAC_VOL 0x16
  62. #define WM_RL_DAC_VOL 0x17
  63. #define WM_BASS_CTRL 0x18
  64. #define WM_TREBLE_CTRL 0x1A
  65. #define WM_RESET_REG 0x1E
  66. #define WM_3D_CTRL 0x20
  67. #define WM_NOISE_GAIN 0x28
  68. #define WM_L_ADC_VOL 0x2A
  69. #define WM_LR_ADC_VOL 0x2B
  70. #define WM_R_ADC_VOL 0x2C
  71. #define WM_RL_ADC_VOL 0x2D
  72. #define WM_PW1_0 0x32
  73. #define WM_PW1_1 0x33
  74. #define WM_PW2_0 0x34
  75. #define WM_PW2_1 0x35
  76. #define WM_ADC_MODE_LINE1 0x3E
  77. #define WM_ADC_MODE_LINE2 0x3F
  78. #define WM_ADCL_PATH 0x40
  79. #define WM_ADCR_PATH 0x42
  80. #define WM_L_OUT_MIX1_0 0x44
  81. #define WM_L_OUT_MIX1_1 0x45
  82. #define WM_L_OUT_MIX2_0 0x46
  83. #define WM_L_OUT_MIX2_1 0x47
  84. #define WM_R_OUT_MIX1_0 0x48
  85. #define WM_R_OUT_MIX1_1 0x49
  86. #define WM_R_OUT_MIX2_0 0x4A
  87. #define WM_R_OUT_MIX2_1 0x4B
  88. #define WM_R_MONO_MIX1_0 0x4C
  89. #define WM_R_MONO_MIX1_1 0x4D
  90. #define WM_R_MONO_MIX2_0 0x4E
  91. #define WM_R_MONO_MIX2_1 0x4F
  92. #endif
  93. #endif
  96. #if((EXT_ADC | EXT_DAC | EXT_PA) & !_PM_INIT_)
  97. //#if(!( CDC_FOR_M5638C & _PM_DVR_ & SETTING_FOR_ICE_START)) //vicky050521#1 //CV0602
  98. API void ExtCdcCtrl(BYTE bCommand)
  99. {
  100. switch(bCommand)
  101. {
  102. case CDC_VOL_UP:
  103. case CDC_VOL_DOWN:
  104. #if(CDC_WM_8731|CDC_WM_8750)
  105. CdcWriteCmd(WM_LR_PHONE_OUT,(gxbVolume*2+47));
  106. //CdcWriteCmd(WM_L_PHONE_OUT,(gxbVolume*2+47)|0x80);
  107. CdcWriteCmd(WM_RL_PHONE_OUT,(gxbVolume*2+47));
  108. #endif
  110. break;
  112. case CDC_PLAYBACK_PAUSE:
  113. obI2S2CTRL1REG &= 0x7f; //Dis I2S IRQ
  114. break;
  116. case CDC_RETURN_PLAYBACK:
  117. obI2S2CTRL1REG |= 0x80; //En I2S IRQ
  118. break;
  120. case CDC_INIT:
  121. MCU_ACCESS_CODEC_I2S_EN(); 
  122. //obMODSEL1 |=  0x12; //Enable SD,MS ,known issue //Vicky050411#1
  123. obMODSEL2 |=  0x08; //Enable I2CM, I2S2, 
  124. obCLKI2CMCTRL=0xD0; //I2CM clock, 12MHz
  125. obREADYENL |= 0x80; //IOBUF
  126. obREADYENH |= 0x08; //I2C/I2S Ready
  127. obSYSSOFTRSTCTRL2|=0x04; //I2CM Normal
  128. obI2CCLKDIV =7; //I2C BCLK 375KHz
  129. obSYSSOFTRSTCTRL2&=0xfd; //I2S2 Reset
  130. obSYSSOFTRSTCTRL2|=0x02; //I2S2 Normal
  131. obDP8051SET|=0x48; //I2S2 to GPIOA, Reference clock output enable
  132. obCLKI2S2CTRL=0xB8; //I2S2 clock, AUD (73/67) MHz //Renshuo050310#X
  133. obCLKI2S2DIVF = 0x02; //default div by 4
  134. MCU_ACCESS_CODEC_I2S_DIS();
  136. #if(CDC_WM_8750)
  137. CdcWriteCmd(WM_RESET_REG,0x00); //reset registers
  138. #endif
  140. #if(CDC_WM_8731)          //reset registers       // Jeff_061016
  141. CdcWriteCmd(WM_RESET_REG,0x00);
  142. #endif
  144. #if(!EXT_ADC)
  145. IntCdcCtrl(CDC_INIT);
  146. #endif
  147. gfCdcAlreadyInit = TRUE; //Renshuo041203#A
  148. break;
  150. case CDC_PLAY_START:
  151. if(!gfCdcAlreadyInit) //2004.11.12 Renshuo
  152. {
  153. ExtCdcCtrl(CDC_INIT); //tne 2006/12/26 #1
  154. //gfCdcAlreadyInit = TRUE; //Renshuo041203#A
  155. }
  157. #if(CDC_WM_8750)
  158. CdcWriteCmd(WM_PW1_0,0xC0); //Power up VMID[50Kohm] and VREF
  159. CdcWriteCmd(WM_PW2_1,0x80); //Powerup DACL & DACR
  160. CdcWriteCmd(WM_PW2_1,0xE0); //Powerup Output Buffer L1 & R1(DACL & DACR still up)
  161. CdcWriteCmd(WM_AD_DA_CTRL,0x00);//dis DAV mute 
  162. CdcWriteCmd(WM_AUD_IF,0x11); //16 bits, MSB Left justified
  163. CdcWriteCmd(WM_LR_DAC_VOL,0xff); //DAC vol 0dB
  164. CdcWriteCmd(WM_L_OUT_MIX1_1,0x50);//LD2LO enable
  165. CdcWriteCmd(WM_R_OUT_MIX2_1,0x50);//RD2RO enable
  166. #endif      // Jeff_061016 start
  168. #if(CDC_WM_8731)
  169. CdcWriteCmd(WM_L_LINE_IN,0x97);  // Jeff_061016
  170. CdcWriteCmd(WM_R_LINE_IN,0x97);
  171. CdcWriteCmd(WM_L_PHONE_OUT,0x70);
  172. CdcWriteCmd(WM_R_PHONE_OUT,0x70);   // Jeff_061016
  173. //CdcWriteCmd(WM_L_LINE_IN,0x97);
  174. //CdcWriteCmd(WM_R_LINE_IN,0x97);
  175. //CdcWriteCmd(WM_L_PHONE_OUT,0x70);
  176. //CdcWriteCmd(WM_R_PHONE_OUT,0x70);
  177. CdcWriteCmd(WM_ACTIVE_CTRL,0x00);
  178. CdcWriteCmd(WM_ANG_CTRL,0x12);
  179. CdcWriteCmd(WM_DIG_CTRL,0x00);
  180. CdcWriteCmd(WM_DIG_FORMAT,0x11);
  181. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  182. CdcWriteCmd(WM_PW_CTRL,0x67);
  183. #endif      // Jeff_061016 end
  185. CdcSetSampleRate();
  186. MCU_ACCESS_CODEC_I2S_EN();
  187. obI2S2CTRL3REG=0x08; //Audio data mode, PIO data
  188. obI2S2FIFOCTL=0x88; //Clear buffer
  189. obI2S2FIFOCTL=0x00;
  190. obI2S2CTRL1REG=0x97; //INT EN, WCLK EN, SDATA_OUT EN, 2 Channel, BCLK EN
  191. MCU_ACCESS_CODEC_I2S_DIS();
  192. CdcCtrl(CDC_VOL_DOWN); //set volume
  193. //#endif   // Jeff_061016
  195. break;
  197. #if(!_PM_PLAY_) //add by tne 2005/01/29 #1
  198. case CDC_REC_START:
  200. #if(CDC_WM_8750)
  201. CdcWriteCmd(WM_PW1_0,0xfc);
  202. CdcWriteCmd(WM_PW2_0,0x60);
  203. //CdcWriteCmd(WM_PW1_0,0xfE);
  204. //CdcWriteCmd(WM_PW2_0,0xff);
  205. CdcWriteCmd(WM_AUD_IF,0x11); //16 bits, MSB Left justified
  206. CdcSetSampleRate();
  207. MCU_ACCESS_CODEC_I2S_EN();
  208. obI2S2CTRL1REG=0x1B; //WCLK EN, SDATA_IN EN, 2 Channel, BCLK EN
  209. obI2S2CTRL3REG=0x08; //Audio data mode, PIO data
  210. obI2S2FIFOCTL=0x80; //Clear buffer
  211. obI2S2FIFOCTL=0x00;
  212. MCU_ACCESS_CODEC_I2S_DIS();
  213. CdcWriteCmd(WM_LR_LINE_IN,0x17);//Analogue vol 0dB //Renshuo050322#A
  214. CdcWriteCmd(WM_RL_LINE_IN,0x17);//Analogue vol 0dB
  215. CdcWriteCmd(WM_LR_ADC_VOL,0xc3);
  216. CdcWriteCmd(WM_RL_ADC_VOL,0xc3);
  217. #endif               // Jeff_061016 start
  219. #if(CDC_WM_8731)
  220. /* CdcWriteCmd(WM_ANG_CTRL,0xE5);
  221. CdcWriteCmd(WM_DIG_CTRL,0x09);
  222. CdcWriteCmd(WM_PW_CTRL,0x69);
  223. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  224. CdcWriteCmd(WM_DIG_FORMAT,0x11); //16 bits, MSB Left justified*/
  225. CdcSetSampleRate();
  226. MCU_ACCESS_CODEC_I2S_EN();
  227. obI2S2CTRL1REG=0x1B; //WCLK EN, SDATA_IN EN, 2 Channel, BCLK EN
  228. obI2S2CTRL3REG=0x08; //Audio data mode, PIO data
  229. obI2S2FIFOCTL=0x80; //Clear buffer
  230. obI2S2FIFOCTL=0x00;
  231. MCU_ACCESS_CODEC_I2S_DIS();
  232. #endif            // Jeff_061016 end
  234. #if(!EXT_ADC)
  235. IntCdcCtrl(CDC_REC_START);
  236. #endif
  237. //#endif // Jeff_061016
  238. break;
  240. case CDC_FM_START:
  242. #if(CDC_WM_8750)
  243. CdcWriteCmd(WM_PW1_0,0xf0);
  244. CdcWriteCmd(WM_PW2_0,0x60);
  245. CdcCtrl(CDC_VOL_DOWN);   //set volume
  246. CdcWriteCmd(WM_L_OUT_MIX1_0,0xa1);//LINPUT2 to Lout
  247. CdcWriteCmd(WM_R_OUT_MIX1_0,0xa1);//RINPUT2 to Rout
  248. #endif
  250. #if(CDC_WM_8731)              // Jeff_061016 start
  251. obDCVARRD=0x14; //DCV power 
  252. obDCVWRDATA=0x98; //44.1K domain, Audio clock=67.7143M //D1003#9
  254. // For S-Case FM noise issue
  255. MCU_ACCESS_CODEC_I2S_EN(); 
  256. obCLKI2S2CTRL=0xB8; //I2S2 clock, AUD (73/67) MHz //Renshuo050310#X
  257. obCLKI2S2DIVF = 0x02; //default div by 4
  258. MCU_ACCESS_CODEC_I2S_DIS();
  260. CdcWriteCmd(WM_L_LINE_IN,0x1E);
  261. CdcWriteCmd(WM_R_LINE_IN,0x1E);
  262. CdcWriteCmd(WM_ANG_CTRL,0x0A);
  263. CdcWriteCmd(WM_PW_CTRL,0x6E);
  264. CdcWriteCmd(WM_DIG_CTRL,0x09);
  265. #endif                        // Jeff_061016 end
  267. #if(!EXT_ADC)  //Renshuo050322#A
  268. IntCdcCtrl(CDC_FM_START);
  269. ClkCdcEn();
  270. obALGPAREG = 0x80;
  271. ClkCdcDis();
  272. #endif
  273. break;
  275. case CDC_FM_IN_AUD_OUT:
  277. #if(CDC_WM_8750)
  278. CdcWriteCmd(WM_ADCL_PATH,0x40); //LINPUT2 to ADC, boost off //Renshuo050322#A
  279. CdcWriteCmd(WM_ADCR_PATH,0x40); //RINPUT2 to ADC, boost off
  280. CdcWriteCmd(WM_LR_LINE_IN,0x17);//Analogue vol 0dB
  281. CdcWriteCmd(WM_RL_LINE_IN,0x17);//Analogue vol 0dB
  282. CdcCtrl(CDC_VOL_DOWN);   //set volume
  283. CdcWriteCmd(WM_L_OUT_MIX1_0,0xa1);//LINPUT2 to Lout
  284. CdcWriteCmd(WM_R_OUT_MIX1_0,0xa1);//RINPUT2 to Rout
  285. #endif             // Jeff_061016 start
  287. #if(CDC_WM_8731)
  288. CdcWriteCmd(WM_ACTIVE_CTRL,0x00);
  289. CdcWriteCmd(WM_DIG_FORMAT,0x11);
  290. CdcWriteCmd(WM_L_LINE_IN,0x1E);
  291. CdcWriteCmd(WM_R_LINE_IN,0x1E);
  292. // CdcWriteCmd(WM_L_PHONE_OUT,0x79 - 12 - 6);
  293. // CdcWriteCmd(WM_R_PHONE_OUT,0x79 - 12 - 6);
  294. CdcWriteCmd(WM_ANG_CTRL,0x0A);
  296. CdcWriteCmd(WM_DIG_CTRL,0x19);
  297. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  298. CdcWriteCmd(WM_PW_CTRL,0x62);
  299. #endif             // Jeff_061016 end
  301. #if(!EXT_ADC)
  302. IntCdcCtrl(CDC_FM_IN_AUD_OUT);
  303. #else
  304. MCU_ACCESS_CODEC_I2S_EN();
  305. obI2S2CTRL1REG |= 0x80;   //En I2S IRQ
  306. MCU_ACCESS_CODEC_I2S_DIS();
  307. #endif
  308. //#endif   // Jeff_061016
  310. break;
  312. case CDC_LINE_IN_AUD_OUT:
  314. #if(CDC_WM_8750)
  315. CdcCtrl(CDC_VOL_DOWN);    //set volume
  316. CdcWriteCmd(WM_ADCL_PATH,0x00); //LINPUT0 to ADC, boost off //Renshuo050322#A
  317. CdcWriteCmd(WM_ADCR_PATH,0x00); //RINPUT0 to ADC, boost off
  318. CdcWriteCmd(WM_LR_LINE_IN,0x17);//Analogue vol 0dB
  319. CdcWriteCmd(WM_RL_LINE_IN,0x17);//Analogue vol 0dB
  320. CdcWriteCmd(WM_L_OUT_MIX1_0,0xa0); //LINPUT1 to Lout
  321. CdcWriteCmd(WM_R_OUT_MIX1_0,0xa0); //RINPUT1 to Rout
  322. #endif          // Jeff_061016 start
  324. #if(CDC_WM_8731)
  325. /* CdcWriteCmd(WM_L_LINE_IN,0x1F);
  326. CdcWriteCmd(WM_R_LINE_IN,0x1F);
  327. CdcWriteCmd(WM_ANG_CTRL,0x0A);
  328. CdcWriteCmd(WM_PW_CTRL,0x7A);
  329. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  330. CdcWriteCmd(WM_DIG_CTRL,0x19);*/
  332. /* CdcWriteCmd(WM_DIG_FORMAT,0x11);OK
  333. CdcWriteCmd(WM_LR_PHONE_OUT,0x00);
  334. CdcWriteCmd(WM_L_LINE_IN,0x1F);
  335. CdcWriteCmd(WM_R_LINE_IN,0x1F);
  336. CdcWriteCmd(WM_ANG_CTRL,0x0A);
  337. CdcWriteCmd(WM_PW_CTRL,0x7A);
  338. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  339. CdcWriteCmd(WM_DIG_CTRL,0x19);*/
  341. CdcWriteCmd(WM_ACTIVE_CTRL,0x00);
  342. CdcWriteCmd(WM_DIG_FORMAT,0x11);
  343. CdcWriteCmd(WM_L_LINE_IN,0x1C);
  344. CdcWriteCmd(WM_R_LINE_IN,0x1C);
  345. CdcWriteCmd(WM_L_PHONE_OUT,0x0);
  346. CdcWriteCmd(WM_R_PHONE_OUT,0x0);
  347. CdcWriteCmd(WM_ANG_CTRL,0x02);
  348. CdcWriteCmd(WM_PW_CTRL,0x7A);
  349. CdcWriteCmd(WM_DIG_CTRL,0x19);
  350. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  351. /* CdcWriteCmd(WM_L_LINE_IN,0x1E);
  352. CdcWriteCmd(WM_R_LINE_IN,0x1E);
  353. CdcWriteCmd(WM_L_PHONE_OUT,0x2F);
  354. CdcWriteCmd(WM_R_PHONE_OUT,0x2F);
  355. CdcWriteCmd(WM_ANG_CTRL,0x02);
  356. CdcWriteCmd(WM_DIG_CTRL,0x09);
  357. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  358. CdcWriteCmd(WM_PW_CTRL,0x6A);*/
  359. #endif            // Jeff_061016 end
  361. #if(!EXT_ADC)
  362. IntCdcCtrl(CDC_LINE_IN_AUD_OUT);
  363. #else
  364. MCU_ACCESS_CODEC_I2S_EN();
  365. obI2S2CTRL1REG |= 0x80; //En I2S IRQ
  366. MCU_ACCESS_CODEC_I2S_DIS();
  367. #endif
  369. // #endif  // Jeff_061016
  371. break;
  373. case CDC_MIC_IN_NO_AUD_OUT:
  375. #if(CDC_WM_8750)
  376. CdcWriteCmd(WM_PW1_0,0xfe);
  377. CdcWriteCmd(WM_PW2_0,0x00);
  378. CdcWriteCmd(WM_ADCL_PATH,0xb0); //LINPUT3 to ADC, 29dB boost //Renshuo050322#A
  379. CdcWriteCmd(WM_ADCR_PATH,0xb0); //RINPUT3 to ADC, 29dB boost
  380. CdcWriteCmd(WM_LR_LINE_IN,0x3f);//Analogue vol +30dB
  381. CdcWriteCmd(WM_RL_LINE_IN,0x3f);//Analogue vol +30dB
  382. //CdcWriteCmd(WM_AD_DA_CTRL,0x01);//dis HP filter
  383. #endif          // Jeff_061016 start
  385. #if(CDC_WM_8731)
  386. CdcWriteCmd(WM_ACTIVE_CTRL,0x00);
  387. CdcWriteCmd(WM_ANG_CTRL,0xE5);
  388. CdcWriteCmd(WM_DIG_CTRL,0x08);
  389. CdcWriteCmd(WM_DIG_FORMAT,0x11); //16 bits, MSB Left justified
  390. CdcWriteCmd(WM_ACTIVE_CTRL,0x01);
  391. CdcWriteCmd(WM_PW_CTRL,0x69);
  392. #endif          // Jeff_061016 end
  394. #if(!EXT_ADC)
  395. IntCdcCtrl(CDC_MIC_IN_NO_AUD_OUT);
  396. #else
  397. MCU_ACCESS_CODEC_I2S_EN();
  398. obI2S2CTRL1REG |= 0x80; //En I2S IRQ
  399. MCU_ACCESS_CODEC_I2S_DIS();
  400. #endif
  401. //#endif  // Jeff_061016
  403. break;
  404. #endif // not _PM_PLAY_ endif
  406. }
  407. }
  408. //#endif
  409. #endif
  412. #if((EXT_ADC | EXT_DAC | EXT_PA) & !_PM_INIT_)
  413. API void ExtCdcSetSampleRate(void)
  414. {
  415. if((gxwSampleRate%1000)==0) //48K domain
  416. {
  417. obDCVARRD=0x14; //DCV power 
  418. obDCVWRDATA=0x90; //48K domain, Audio clock=73.7143M //D1003#9
  419. }
  420. else //44.1K domain
  421. {
  422. obDCVARRD=0x14; //DCV power 
  423. obDCVWRDATA=0x98; //44.1K domain, Audio clock=67.7143M //D1003#9
  425. }
  426. MCU_ACCESS_CODEC_I2S_EN();
  427. //obMODSEL1 |=  0x02; //Enable MS //Vicky050411#1
  428. //obCLKI2S2DIVF=6;
  429. //obCLKI2S2CTRL=0xB8; //I2S2 clock, Audio Clock/8=9.214M or 8.464M
  430. //obCLKI2S2CTRL=0xD0; //I2S2 clock, 12 MHz //always use AUD clk
  431. obSYSSOFTRSTCTRL2&=0xfd;//I2S2 reset
  432. obSYSSOFTRSTCTRL2|=0x02;//I2S2 Normal
  434. switch(gxwSampleRate)
  435. {
  436. #if(CDC_WM_8750)
  438. case 48000:
  439. CdcWriteCmd(WM_SAMPLE_RATE,0x02);//48k, not USB mode;
  440. obI2S2SCLKDIV=12; //I2S BCLK 18.432M/12 = (48k*32)
  441. break;
  442. case 32000:
  443. CdcWriteCmd(WM_SAMPLE_RATE,0x1A); //32k, not USB mode;
  444. obI2S2SCLKDIV=18; //I2S BCLK 18.432M/18 = (32k*32)
  445. break;
  446. case 24000: 
  447. CdcWriteCmd(WM_SAMPLE_RATE,0x3A);//24k, not USB mode;
  448. obI2S2SCLKDIV=24; //I2S BCLK 18.432M/24 = (24k*32)
  449. break;
  450. case 16000:
  451. CdcWriteCmd(WM_SAMPLE_RATE,0x16);//16k, not USB mode;
  452. obI2S2SCLKDIV=36; //I2S BCLK 18.432M/36 = (16k*32)
  453. break;
  454. case 12000:
  455. CdcWriteCmd(WM_SAMPLE_RATE,0x12);//16k, not USB mode;
  456. obI2S2SCLKDIV=48; //I2S BCLK 18.432M/48 = (12k*32)
  457. break;
  458. case 8000:
  459. CdcWriteCmd(WM_SAMPLE_RATE,0x0E); //8k, not USB mode
  460. obI2S2SCLKDIV=72; //I2S BCLK 18.432M/72 = (8k*32)
  461. break;
  462. case 11025:
  463. CdcWriteCmd(WM_SAMPLE_RATE,0x32);//11.025k, not USB mode;
  464. obI2S2SCLKDIV=48; //I2S BCLK 16.9344M/48 = (11.025k*32)
  465. break;
  466. case 22050:
  467. CdcWriteCmd(WM_SAMPLE_RATE,0x36);//22.05k, not USB mode;
  468. //obI2S2SCLKDIV=12; //I2S BCLK 705KHz
  469. obI2S2SCLKDIV=24; //I2S BCLK 16.9344M/24 = (22.05k*32)
  470. break;
  471. case 44100:
  472. default:
  473. CdcWriteCmd(WM_SAMPLE_RATE,0x22);//44.1k, not USB mode;
  474. obI2S2SCLKDIV=12; //I2S BCLK 16.9344M/12 = (44.1k*32)
  475. break;
  476. #endif       // Jeff_061016 start
  478. #if(CDC_WM_8731)//add by william lian 
  479. case 48000:
  480. CdcWriteCmd(WM_SAMPLE_CTRL,0x02);//48k, not USB mode;
  481. obI2S2SCLKDIV=12; //I2S BCLK 18.432M/12 = (48k*32)
  482. break;
  483. case 32000:
  484. CdcWriteCmd(WM_SAMPLE_CTRL,0x1A); //32k, not USB mode;
  485. obI2S2SCLKDIV=18; //I2S BCLK 18.432M/18 = (32k*32)
  486. break;
  487. case 8000:
  488. CdcWriteCmd(WM_SAMPLE_CTRL,0x0E); //8k, not USB mode
  489. obI2S2SCLKDIV=72; //I2S BCLK 18.432M/72 = (8k*32)
  490. break;
  491. case 96000:
  492. CdcWriteCmd(WM_SAMPLE_CTRL,0x1E);//96k,not USB mode
  493. obI2S2SCLKDIV=6; //I2S BCLK 18.432M/6 = (96k*32)
  494. break;
  495. case 88200:
  496. CdcWriteCmd(WM_SAMPLE_CTRL,0x3E);//88.2k,not USB mode
  497. obI2S2SCLKDIV=6; //I2S BCLK 16.9344M/6 = (88.2k*32)
  498. break;
  499. case 24000:
  500. CdcWriteCmd(WM_SAMPLE_CTRL,0x42);//24k, not USB mode;
  501. obI2S2SCLKDIV=24; //I2S BCLK 18.432M/24 = (24k*32)
  502. break;
  503. case 16000:
  504. CdcWriteCmd(WM_SAMPLE_CTRL,0x5A); //16k, not USB mode;
  505. obI2S2SCLKDIV=36; //I2S BCLK 18.432M/36 = (16k*32)
  506. break;
  507. case 12000:
  508. CdcWriteCmd(WM_SAMPLE_CTRL,0x02);//12k, not USB mode;
  509. obI2S2SCLKDIV=48; //I2S BCLK 18.432M/48 = (12k*32)
  510. break;
  511. case 11025:
  512. CdcWriteCmd(WM_SAMPLE_CTRL,0x22);//11.025k, not USB mode;
  513. obI2S2SCLKDIV=48; //I2S BCLK 16.9344M/48 = (11.025k*32)
  514. break;
  515. case 22050:
  516. CdcWriteCmd(WM_SAMPLE_CTRL,0x62);//22.050k, not USB mode;
  517. obI2S2SCLKDIV=24; //I2S BCLK 16.9344M/24 = (22.050k*32)
  518. break;
  519. case 44100:
  520. default:
  521. CdcWriteCmd(WM_SAMPLE_CTRL,0x22);//44.1k, not USB mode;
  522. obI2S2SCLKDIV=12; //I2S BCLK 16.9344M/12 = (44.1k*32)
  523. break;          // Jeff_061016 end
  524. #endif
  525. }
  526. #if(CDC_WM_8750|CDC_WM_8731) // Jeff_061016
  527. obI2S2CTRL3REG=0x08; //Audio data mode, PIO data
  528. obI2S2FIFOCTL=0x88; //Clear buffer
  529. obI2S2FIFOCTL=0x00;
  530. obI2S2CTRL1REG=0x97; //INT EN, WCLK EN, SDATA_OUT EN, 2 Channel, BCLK EN
  531. #endif
  532. MCU_ACCESS_CODEC_I2S_DIS();
  533. }
  534. #endif
  536. #if((EXT_ADC | EXT_DAC | EXT_PA) & !_PM_INIT_)
  537. void CdcWriteCmd(BYTE bAddr, BYTE bData) large
  538. {
  540. obCLKI2CMCTRL |= 0x80; //clock Enable
  541. obMODSEL2 |= 0x08; //I2CM Enable
  542. #define ReTry bAddr
  543. obI2CMAADDR=CDC_DEVICE_ADDRESS;
  544. obI2CSLADDR=bAddr;
  545. obI2CFIFO=bData;
  546. obI2CMACMD=0x11;
  547. ReTry=0xFF;
  548. while(obI2CSERSTS&0x80) //wait busy
  549. {
  550. ReTry--;
  551. if(ReTry==0)
  552. break;
  553. }
  554. obMODSEL2 &= 0xF7; //I2CM Disable
  555. obCLKI2CMCTRL &= 0x7F; //clock Disable
  556. }
  558. #endif
  560. #if(_PM_REC_)
  561. //tne 2005/08/17 //release IntCode
  562. void ClearExtCdcBuffer(void) large //This function would be called by Record Engine (ReInit)
  563. {
  564. #if(EXT_ADC) //Ren050312#1
  565. MCU_ACCESS_CODEC_I2S_EN();
  566. obI2S2FIFOCTL=0x88; //Clear buffer
  567. obI2S2FIFOCTL=0x00;
  568. MCU_ACCESS_CODEC_I2S_DIS();
  569. #else
  570. // ...do nothing
  571. #endif
  572. }
  573. #endif