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shubio.h：源码内容

/* $Id: shubio.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
*/
#ifndef _ASM_IA64_SN_SN2_SHUBIO_H
#define _ASM_IA64_SN_SN2_SHUBIO_H
#include <asm/sn/arch.h>
#define HUB_WIDGET_ID_MAX 0xf
#define IIO_NUM_ITTES 7
#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1)
#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */
/* This register is also accessible from
* Crosstalk at address 0x0. */
#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */
#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */
#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */
#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */
#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */
#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */
#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */
#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */
#define IIO_ILLR 0x00400130 /* IO LLP Log Register */
#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */
#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */
#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */
#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */
#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */
#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */
#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */
#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */
#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */
#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */
#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */
#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */
#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */
#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */
#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */
#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */
#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */
#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */
#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */
#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */
#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */
#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */
#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */
#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */
#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */
#define IIO_IBCR 0x00400200 /* IO BTE Control Register */
#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */
#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */
#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */
#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */
#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */
#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */
#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */
#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */
#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */
#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */
#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */
#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */
#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */
#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */
#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */
#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */
#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */
#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */
#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */
#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */
#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */
#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */
#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */
#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */
#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */
#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */
#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */
#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */
#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */
#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */
#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */
#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */
#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */
#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */
#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */
#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */
#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */
#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */
#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */
#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */
#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */
#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */
#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */
#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */
#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */
#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */
#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */
#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */
#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */
#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */
#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */
#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */
#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */
#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */
#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */
#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */
#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */
#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */
#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */
#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */
#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */
#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */
#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */
#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */
#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */
#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */
#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */
#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */
#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */
#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */
#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */
#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */
#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */
#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */
#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */
#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */
#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */
#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */
#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */
#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */
#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */
#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */
#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */
#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */
#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */
#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */
#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */
#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */
#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */
#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */
#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */
#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */
#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */
#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */
#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */
#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */
#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */
#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */
#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */
#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */
#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */
#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */
#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */
#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */
#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */
#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */
#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */
#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */
#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */
#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */
#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */
#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */
#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */
#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */
#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */
#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */
#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */
#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */
#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */
#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */
#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */
#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */
#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */
#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */
#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */
#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */
#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */
#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */
#define IIO_IPCR 0x00430000 /* IO Performance Control */
#define IIO_IPPR 0x00430008 /* IO Performance Profiling */
#ifndef __ASSEMBLY__
/************************************************************************
* *
* Description: This register echoes some information from the *
* LB_REV_ID register. It is available through Crosstalk as described *
* above. The REV_NUM and MFG_NUM fields receive their values from *
* the REVISION and MANUFACTURER fields in the LB_REV_ID register. *
* The PART_NUM field's value is the Crosstalk device ID number that *
* Steve Miller assigned to the SHub chip. *
* *
************************************************************************/
typedef union ii_wid_u {
shubreg_t ii_wid_regval;
struct {
shubreg_t w_rsvd_1 : 1;
shubreg_t w_mfg_num : 11;
shubreg_t w_part_num : 16;
shubreg_t w_rev_num : 4;
shubreg_t w_rsvd : 32;
} ii_wid_fld_s;
} ii_wid_u_t;
/************************************************************************
* *
* The fields in this register are set upon detection of an error *
* and cleared by various mechanisms, as explained in the *
* description. *
* *
************************************************************************/
typedef union ii_wstat_u {
shubreg_t ii_wstat_regval;
struct {
shubreg_t w_pending : 4;
shubreg_t w_xt_crd_to : 1;
shubreg_t w_xt_tail_to : 1;
shubreg_t w_rsvd_3 : 3;
shubreg_t w_tx_mx_rty : 1;
shubreg_t w_rsvd_2 : 6;
shubreg_t w_llp_tx_cnt : 8;
shubreg_t w_rsvd_1 : 8;
shubreg_t w_crazy : 1;
shubreg_t w_rsvd : 31;
} ii_wstat_fld_s;
} ii_wstat_u_t;
/************************************************************************
* *
* Description: This is a read-write enabled register. It controls *
* various aspects of the Crosstalk flow control. *
* *
************************************************************************/
typedef union ii_wcr_u {
shubreg_t ii_wcr_regval;
struct {
shubreg_t w_wid : 4;
shubreg_t w_tag : 1;
shubreg_t w_rsvd_1 : 8;
shubreg_t w_dst_crd : 3;
shubreg_t w_f_bad_pkt : 1;
shubreg_t w_dir_con : 1;
shubreg_t w_e_thresh : 5;
shubreg_t w_rsvd : 41;
} ii_wcr_fld_s;
} ii_wcr_u_t;
/************************************************************************
* *
* Description: This register's value is a bit vector that guards *
* access to local registers within the II as well as to external *
* Crosstalk widgets. Each bit in the register corresponds to a *
* particular region in the system; a region consists of one, two or *
* four nodes (depending on the value of the REGION_SIZE field in the *
* LB_REV_ID register, which is documented in Section 8.3.1.1). The *
* protection provided by this register applies to PIO read *
* operations as well as PIO write operations. The II will perform a *
* PIO read or write request only if the bit for the requestor's *
* region is set; otherwise, the II will not perform the requested *
* operation and will return an error response. When a PIO read or *
* write request targets an external Crosstalk widget, then not only *
* must the bit for the requestor's region be set in the ILAPR, but *
* also the target widget's bit in the IOWA register must be set in *
* order for the II to perform the requested operation; otherwise, *
* the II will return an error response. Hence, the protection *
* provided by the IOWA register supplements the protection provided *
* by the ILAPR for requests that target external Crosstalk widgets. *
* This register itself can be accessed only by the nodes whose *
* region ID bits are enabled in this same register. It can also be *
* accessed through the IAlias space by the local processors. *
* The reset value of this register allows access by all nodes. *
* *
************************************************************************/
typedef union ii_ilapr_u {
shubreg_t ii_ilapr_regval;
struct {
shubreg_t i_region : 64;
} ii_ilapr_fld_s;
} ii_ilapr_u_t;
/************************************************************************
* *
* Description: A write to this register of the 64-bit value *
* "SGIrules" in ASCII, will cause the bit in the ILAPR register *
* corresponding to the region of the requestor to be set (allow *
* access). A write of any other value will be ignored. Access *
* protection for this register is "SGIrules". *
* This register can also be accessed through the IAlias space. *
* However, this access will not change the access permissions in the *
* ILAPR. *
* *
************************************************************************/
typedef union ii_ilapo_u {
shubreg_t ii_ilapo_regval;
struct {
shubreg_t i_io_ovrride : 64;
} ii_ilapo_fld_s;
} ii_ilapo_u_t;
/************************************************************************
* *
* This register qualifies all the PIO and Graphics writes launched *
* from the SHUB towards a widget. *
* *
************************************************************************/
typedef union ii_iowa_u {
shubreg_t ii_iowa_regval;
struct {
shubreg_t i_w0_oac : 1;
shubreg_t i_rsvd_1 : 7;
shubreg_t i_wx_oac : 8;
shubreg_t i_rsvd : 48;
} ii_iowa_fld_s;
} ii_iowa_u_t;
/************************************************************************
* *
* Description: This register qualifies all the requests launched *
* from a widget towards the Shub. This register is intended to be *
* used by software in case of misbehaving widgets. *
* *
* *
************************************************************************/
typedef union ii_iiwa_u {
shubreg_t ii_iiwa_regval;
struct {
shubreg_t i_w0_iac : 1;
shubreg_t i_rsvd_1 : 7;
shubreg_t i_wx_iac : 8;
shubreg_t i_rsvd : 48;
} ii_iiwa_fld_s;
} ii_iiwa_u_t;
/************************************************************************
* *
* Description: This register qualifies all the operations launched *
* from a widget towards the SHub. It allows individual access *
* control for up to 8 devices per widget. A device refers to *
* individual DMA master hosted by a widget. *
* The bits in each field of this register are cleared by the Shub *
* upon detection of an error which requires the device to be *
* disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric *
* Crosstalk). Whether or not a device has access rights to this *
* Shub is determined by an AND of the device enable bit in the *
* appropriate field of this register and the corresponding bit in *
* the Wx_IAC field (for the widget which this device belongs to). *
* The bits in this field are set by writing a 1 to them. Incoming *
* replies from Crosstalk are not subject to this access control *
* mechanism. *
* *
************************************************************************/
typedef union ii_iidem_u {
shubreg_t ii_iidem_regval;
struct {
shubreg_t i_w8_dxs : 8;
shubreg_t i_w9_dxs : 8;
shubreg_t i_wa_dxs : 8;
shubreg_t i_wb_dxs : 8;
shubreg_t i_wc_dxs : 8;
shubreg_t i_wd_dxs : 8;
shubreg_t i_we_dxs : 8;
shubreg_t i_wf_dxs : 8;
} ii_iidem_fld_s;
} ii_iidem_u_t;
/************************************************************************
* *
* This register contains the various programmable fields necessary *
* for controlling and observing the LLP signals. *
* *
************************************************************************/
typedef union ii_ilcsr_u {
shubreg_t ii_ilcsr_regval;
struct {
shubreg_t i_nullto : 6;
shubreg_t i_rsvd_4 : 2;
shubreg_t i_wrmrst : 1;
shubreg_t i_rsvd_3 : 1;
shubreg_t i_llp_en : 1;
shubreg_t i_bm8 : 1;
shubreg_t i_llp_stat : 2;
shubreg_t i_remote_power : 1;
shubreg_t i_rsvd_2 : 1;
shubreg_t i_maxrtry : 10;
shubreg_t i_d_avail_sel : 2;
shubreg_t i_rsvd_1 : 4;
shubreg_t i_maxbrst : 10;
shubreg_t i_rsvd : 22;
} ii_ilcsr_fld_s;
} ii_ilcsr_u_t;
/************************************************************************
* *
* This is simply a status registers that monitors the LLP error *
* rate. *
* *
************************************************************************/
typedef union ii_illr_u {
shubreg_t ii_illr_regval;
struct {
shubreg_t i_sn_cnt : 16;
shubreg_t i_cb_cnt : 16;
shubreg_t i_rsvd : 32;
} ii_illr_fld_s;
} ii_illr_u_t;
/************************************************************************
* *
* Description: All II-detected non-BTE error interrupts are *
* specified via this register. *
* NOTE: The PI interrupt register address is hardcoded in the II. If *
* PI_ID==0, then the II sends an interrupt request (Duplonet PWRI *
* packet) to address offset 0x0180_0090 within the local register *
* address space of PI0 on the node specified by the NODE field. If *
* PI_ID==1, then the II sends the interrupt request to address *
* offset 0x01A0_0090 within the local register address space of PI1 *
* on the node specified by the NODE field. *
* *
************************************************************************/
typedef union ii_iidsr_u {
shubreg_t ii_iidsr_regval;
struct {
shubreg_t i_level : 8;
shubreg_t i_pi_id : 1;
shubreg_t i_node : 11;
shubreg_t i_rsvd_3 : 4;
shubreg_t i_enable : 1;
shubreg_t i_rsvd_2 : 3;
shubreg_t i_int_sent : 2;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_pi0_forward_int : 1;
shubreg_t i_pi1_forward_int : 1;
shubreg_t i_rsvd : 30;
} ii_iidsr_fld_s;
} ii_iidsr_u_t;
/************************************************************************
* *
* There are two instances of this register. This register is used *
* for matching up the incoming responses from the graphics widget to *
* the processor that initiated the graphics operation. The *
* write-responses are converted to graphics credits and returned to *
* the processor so that the processor interface can manage the flow *
* control. *
* *
************************************************************************/
typedef union ii_igfx0_u {
shubreg_t ii_igfx0_regval;
struct {
shubreg_t i_w_num : 4;
shubreg_t i_pi_id : 1;
shubreg_t i_n_num : 12;
shubreg_t i_p_num : 1;
shubreg_t i_rsvd : 46;
} ii_igfx0_fld_s;
} ii_igfx0_u_t;
/************************************************************************
* *
* There are two instances of this register. This register is used *
* for matching up the incoming responses from the graphics widget to *
* the processor that initiated the graphics operation. The *
* write-responses are converted to graphics credits and returned to *
* the processor so that the processor interface can manage the flow *
* control. *
* *
************************************************************************/
typedef union ii_igfx1_u {
shubreg_t ii_igfx1_regval;
struct {
shubreg_t i_w_num : 4;
shubreg_t i_pi_id : 1;
shubreg_t i_n_num : 12;
shubreg_t i_p_num : 1;
shubreg_t i_rsvd : 46;
} ii_igfx1_fld_s;
} ii_igfx1_u_t;
/************************************************************************
* *
* There are two instances of this registers. These registers are *
* used as scratch registers for software use. *
* *
************************************************************************/
typedef union ii_iscr0_u {
shubreg_t ii_iscr0_regval;
struct {
shubreg_t i_scratch : 64;
} ii_iscr0_fld_s;
} ii_iscr0_u_t;
/************************************************************************
* *
* There are two instances of this registers. These registers are *
* used as scratch registers for software use. *
* *
************************************************************************/
typedef union ii_iscr1_u {
shubreg_t ii_iscr1_regval;
struct {
shubreg_t i_scratch : 64;
} ii_iscr1_fld_s;
} ii_iscr1_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Shub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the SHub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Shub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte1_u {
shubreg_t ii_itte1_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte1_fld_s;
} ii_itte1_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Shub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Shub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Shub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte2_u {
shubreg_t ii_itte2_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte2_fld_s;
} ii_itte2_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Shub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Shub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the SHub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte3_u {
shubreg_t ii_itte3_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte3_fld_s;
} ii_itte3_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a SHub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the SHub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the SHub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte4_u {
shubreg_t ii_itte4_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte4_fld_s;
} ii_itte4_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a SHub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Shub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Shub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte5_u {
shubreg_t ii_itte5_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte5_fld_s;
} ii_itte5_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Shub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Shub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the Shub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte6_u {
shubreg_t ii_itte6_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte6_fld_s;
} ii_itte6_u_t;
/************************************************************************
* *
* Description: There are seven instances of translation table entry *
* registers. Each register maps a Shub Big Window to a 48-bit *
* address on Crosstalk. *
* For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window *
* number) are used to select one of these 7 registers. The Widget *
* number field is then derived from the W_NUM field for synthesizing *
* a Crosstalk packet. The 5 bits of OFFSET are concatenated with *
* SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] *
* are padded with zeros. Although the maximum Crosstalk space *
* addressable by the Shub is thus the lower 16 GBytes per widget *
* (M-mode), however only 7/32nds of this *
* space can be accessed. *
* For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big *
* Window number) are used to select one of these 7 registers. The *
* Widget number field is then derived from the W_NUM field for *
* synthesizing a Crosstalk packet. The 5 bits of OFFSET are *
* concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP *
* field is used as Crosstalk[47], and remainder of the Crosstalk *
* address bits (Crosstalk[46:34]) are always zero. While the maximum *
* Crosstalk space addressable by the SHub is thus the lower *
* 8-GBytes per widget (N-mode), only 7/32nds *
* of this space can be accessed. *
* *
************************************************************************/
typedef union ii_itte7_u {
shubreg_t ii_itte7_regval;
struct {
shubreg_t i_offset : 5;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_w_num : 4;
shubreg_t i_iosp : 1;
shubreg_t i_rsvd : 51;
} ii_itte7_fld_s;
} ii_itte7_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprb0_u {
shubreg_t ii_iprb0_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprb0_fld_s;
} ii_iprb0_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprb8_u {
shubreg_t ii_iprb8_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprb8_fld_s;
} ii_iprb8_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprb9_u {
shubreg_t ii_iprb9_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprb9_fld_s;
} ii_iprb9_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* *
* *
************************************************************************/
typedef union ii_iprba_u {
shubreg_t ii_iprba_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprba_fld_s;
} ii_iprba_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprbb_u {
shubreg_t ii_iprbb_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprbb_fld_s;
} ii_iprbb_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprbc_u {
shubreg_t ii_iprbc_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprbc_fld_s;
} ii_iprbc_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprbd_u {
shubreg_t ii_iprbd_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprbd_fld_s;
} ii_iprbd_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of SHub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprbe_u {
shubreg_t ii_iprbe_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprbe_fld_s;
} ii_iprbe_u_t;
/************************************************************************
* *
* Description: There are 9 instances of this register, one per *
* actual widget in this implementation of Shub and Crossbow. *
* Note: Crossbow only has ports for Widgets 8 through F, widget 0 *
* refers to Crossbow's internal space. *
* This register contains the state elements per widget that are *
* necessary to manage the PIO flow control on Crosstalk and on the *
* Router Network. See the PIO Flow Control chapter for a complete *
* description of this register *
* The SPUR_WR bit requires some explanation. When this register is *
* written, the new value of the C field is captured in an internal *
* register so the hardware can remember what the programmer wrote *
* into the credit counter. The SPUR_WR bit sets whenever the C field *
* increments above this stored value, which indicates that there *
* have been more responses received than requests sent. The SPUR_WR *
* bit cannot be cleared until a value is written to the IPRBx *
* register; the write will correct the C field and capture its new *
* value in the internal register. Even if IECLR[E_PRB_x] is set, the *
* SPUR_WR bit will persist if IPRBx hasn't yet been written. *
* . *
* *
************************************************************************/
typedef union ii_iprbf_u {
shubreg_t ii_iprbf_regval;
struct {
shubreg_t i_c : 8;
shubreg_t i_na : 14;
shubreg_t i_rsvd_2 : 2;
shubreg_t i_nb : 14;
shubreg_t i_rsvd_1 : 2;
shubreg_t i_m : 2;
shubreg_t i_f : 1;
shubreg_t i_of_cnt : 5;
shubreg_t i_error : 1;
shubreg_t i_rd_to : 1;
shubreg_t i_spur_wr : 1;
shubreg_t i_spur_rd : 1;
shubreg_t i_rsvd : 11;
shubreg_t i_mult_err : 1;
} ii_iprbe_fld_s;
} ii_iprbf_u_t;
/************************************************************************
* *
* This register specifies the timeout value to use for monitoring *
* Crosstalk credits which are used outbound to Crosstalk. An *
* internal counter called the Crosstalk Credit Timeout Counter *
* increments every 128 II clocks. The counter starts counting *
* anytime the credit count drops below a threshold, and resets to *
* zero (stops counting) anytime the credit count is at or above the *
* threshold. The threshold is 1 credit in direct connect mode and 2 *
* in Crossbow connect mode. When the internal Crosstalk Credit *
* Timeout Counter reaches the value programmed in this register, a *
* Crosstalk Credit Timeout has occurred. The internal counter is not *
* readable from software, and stops counting at its maximum value, *
* so it cannot cause more than one interrupt. *
* *
************************************************************************/
typedef union ii_ixcc_u {
shubreg_t ii_ixcc_regval;
struct {
shubreg_t i_time_out : 26;
shubreg_t i_rsvd : 38;
} ii_ixcc_fld_s;
} ii_ixcc_u_t;
/************************************************************************
* *
* Description: This register qualifies all the PIO and DMA *
* operations launched from widget 0 towards the SHub. In *
* addition, it also qualifies accesses by the BTE streams. *
* The bits in each field of this register are cleared by the SHub *
* upon detection of an error which requires widget 0 or the BTE *
* streams to be terminated. Whether or not widget x has access *
* rights to this SHub is determined by an AND of the device *
* enable bit in the appropriate field of this register and bit 0 in *
* the Wx_IAC field. The bits in this field are set by writing a 1 to *
* them. Incoming replies from Crosstalk are not subject to this *
* access control mechanism. *
* *
************************************************************************/
typedef union ii_imem_u {
shubreg_t ii_imem_regval;
struct {
shubreg_t i_w0_esd : 1;
shubreg_t i_rsvd_3 : 3;
shubreg_t i_b0_esd : 1;
shubreg_t i_rsvd_2 : 3;
shubreg_t i_b1_esd : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_clr_precise : 1;
shubreg_t i_rsvd : 51;
} ii_imem_fld_s;
} ii_imem_u_t;
/************************************************************************
* *
* Description: This register specifies the timeout value to use for *
* monitoring Crosstalk tail flits coming into the Shub in the *
* TAIL_TO field. An internal counter associated with this register *
* is incremented every 128 II internal clocks (7 bits). The counter *
* starts counting anytime a header micropacket is received and stops *
* counting (and resets to zero) any time a micropacket with a Tail *
* bit is received. Once the counter reaches the threshold value *
* programmed in this register, it generates an interrupt to the *
* processor that is programmed into the IIDSR. The counter saturates *
* (does not roll over) at its maximum value, so it cannot cause *
* another interrupt until after it is cleared. *
* The register also contains the Read Response Timeout values. The *
* Prescalar is 23 bits, and counts II clocks. An internal counter *
* increments on every II clock and when it reaches the value in the *
* Prescalar field, all IPRTE registers with their valid bits set *
* have their Read Response timers bumped. Whenever any of them match *
* the value in the RRSP_TO field, a Read Response Timeout has *
* occurred, and error handling occurs as described in the Error *
* Handling section of this document. *
* *
************************************************************************/
typedef union ii_ixtt_u {
shubreg_t ii_ixtt_regval;
struct {
shubreg_t i_tail_to : 26;
shubreg_t i_rsvd_1 : 6;
shubreg_t i_rrsp_ps : 23;
shubreg_t i_rrsp_to : 5;
shubreg_t i_rsvd : 4;
} ii_ixtt_fld_s;
} ii_ixtt_u_t;
/************************************************************************
* *
* Writing a 1 to the fields of this register clears the appropriate *
* error bits in other areas of SHub. Note that when the *
* E_PRB_x bits are used to clear error bits in PRB registers, *
* SPUR_RD and SPUR_WR may persist, because they require additional *
* action to clear them. See the IPRBx and IXSS Register *
* specifications. *
* *
************************************************************************/
typedef union ii_ieclr_u {
shubreg_t ii_ieclr_regval;
struct {
shubreg_t i_e_prb_0 : 1;
shubreg_t i_rsvd : 7;
shubreg_t i_e_prb_8 : 1;
shubreg_t i_e_prb_9 : 1;
shubreg_t i_e_prb_a : 1;
shubreg_t i_e_prb_b : 1;
shubreg_t i_e_prb_c : 1;
shubreg_t i_e_prb_d : 1;
shubreg_t i_e_prb_e : 1;
shubreg_t i_e_prb_f : 1;
shubreg_t i_e_crazy : 1;
shubreg_t i_e_bte_0 : 1;
shubreg_t i_e_bte_1 : 1;
shubreg_t i_reserved_1 : 10;
shubreg_t i_spur_rd_hdr : 1;
shubreg_t i_cam_intr_to : 1;
shubreg_t i_cam_overflow : 1;
shubreg_t i_cam_read_miss : 1;
shubreg_t i_ioq_rep_underflow : 1;
shubreg_t i_ioq_req_underflow : 1;
shubreg_t i_ioq_rep_overflow : 1;
shubreg_t i_ioq_req_overflow : 1;
shubreg_t i_iiq_rep_overflow : 1;
shubreg_t i_iiq_req_overflow : 1;
shubreg_t i_ii_xn_rep_cred_overflow : 1;
shubreg_t i_ii_xn_req_cred_overflow : 1;
shubreg_t i_ii_xn_invalid_cmd : 1;
shubreg_t i_xn_ii_invalid_cmd : 1;
shubreg_t i_reserved_2 : 21;
} ii_ieclr_fld_s;
} ii_ieclr_u_t;
/************************************************************************
* *
* This register controls both BTEs. SOFT_RESET is intended for *
* recovery after an error. COUNT controls the total number of CRBs *
* that both BTEs (combined) can use, which affects total BTE *
* bandwidth. *
* *
************************************************************************/
typedef union ii_ibcr_u {
shubreg_t ii_ibcr_regval;
struct {
shubreg_t i_count : 4;
shubreg_t i_rsvd_1 : 4;
shubreg_t i_soft_reset : 1;
shubreg_t i_rsvd : 55;
} ii_ibcr_fld_s;
} ii_ibcr_u_t;
/************************************************************************
* *
* This register contains the header of a spurious read response *
* received from Crosstalk. A spurious read response is defined as a *
* read response received by II from a widget for which (1) the SIDN *
* has a value between 1 and 7, inclusive (II never sends requests to *
* these widgets (2) there is no valid IPRTE register which *
* corresponds to the TNUM, or (3) the widget indicated in SIDN is *
* not the same as the widget recorded in the IPRTE register *
* referenced by the TNUM. If this condition is true, and if the *
* IXSS[VALID] bit is clear, then the header of the spurious read *
* response is capture in IXSM and IXSS, and IXSS[VALID] is set. The *
* errant header is thereby captured, and no further spurious read *
* respones are captured until IXSS[VALID] is cleared by setting the *
* appropriate bit in IECLR.Everytime a spurious read response is *
* detected, the SPUR_RD bit of the PRB corresponding to the incoming *
* message's SIDN field is set. This always happens, regarless of *
* whether a header is captured. The programmer should check *
* IXSM[SIDN] to determine which widget sent the spurious response, *
* because there may be more than one SPUR_RD bit set in the PRB *
* registers. The widget indicated by IXSM[SIDN] was the first *
* spurious read response to be received since the last time *
* IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB *
* will be set. Any SPUR_RD bits in any other PRB registers indicate *
* spurious messages from other widets which were detected after the *
* header was captured.. *
* *
************************************************************************/
typedef union ii_ixsm_u {
shubreg_t ii_ixsm_regval;
struct {
shubreg_t i_byte_en : 32;
shubreg_t i_reserved : 1;
shubreg_t i_tag : 3;
shubreg_t i_alt_pactyp : 4;
shubreg_t i_bo : 1;
shubreg_t i_error : 1;
shubreg_t i_vbpm : 1;
shubreg_t i_gbr : 1;
shubreg_t i_ds : 2;
shubreg_t i_ct : 1;
shubreg_t i_tnum : 5;
shubreg_t i_pactyp : 4;
shubreg_t i_sidn : 4;
shubreg_t i_didn : 4;
} ii_ixsm_fld_s;
} ii_ixsm_u_t;
/************************************************************************
* *
* This register contains the sideband bits of a spurious read *
* response received from Crosstalk. *
* *
************************************************************************/
typedef union ii_ixss_u {
shubreg_t ii_ixss_regval;
struct {
shubreg_t i_sideband : 8;
shubreg_t i_rsvd : 55;
shubreg_t i_valid : 1;
} ii_ixss_fld_s;
} ii_ixss_u_t;
/************************************************************************
* *
* This register enables software to access the II LLP's test port. *
* Refer to the LLP 2.5 documentation for an explanation of the test *
* port. Software can write to this register to program the values *
* for the control fields (TestErrCapture, TestClear, TestFlit, *
* TestMask and TestSeed). Similarly, software can read from this *
* register to obtain the values of the test port's status outputs *
* (TestCBerr, TestValid and TestData). *
* *
************************************************************************/
typedef union ii_ilct_u {
shubreg_t ii_ilct_regval;
struct {
shubreg_t i_test_seed : 20;
shubreg_t i_test_mask : 8;
shubreg_t i_test_data : 20;
shubreg_t i_test_valid : 1;
shubreg_t i_test_cberr : 1;
shubreg_t i_test_flit : 3;
shubreg_t i_test_clear : 1;
shubreg_t i_test_err_capture : 1;
shubreg_t i_rsvd : 9;
} ii_ilct_fld_s;
} ii_ilct_u_t;
/************************************************************************
* *
* If the II detects an illegal incoming Duplonet packet (request or *
* reply) when VALID==0 in the IIEPH1 register, then it saves the *
* contents of the packet's header flit in the IIEPH1 and IIEPH2 *
* registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, *
* and assigns a value to the ERR_TYPE field which indicates the *
* specific nature of the error. The II recognizes four different *
* types of errors: short request packets (ERR_TYPE==2), short reply *
* packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long *
* reply packets (ERR_TYPE==5). The encodings for these types of *
* errors were chosen to be consistent with the same types of errors *
* indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in *
* the LB unit). If the II detects an illegal incoming Duplonet *
* packet when VALID==1 in the IIEPH1 register, then it merely sets *
* the OVERRUN bit to indicate that a subsequent error has happened, *
* and does nothing further. *
* *
************************************************************************/
typedef union ii_iieph1_u {
shubreg_t ii_iieph1_regval;
struct {
shubreg_t i_command : 7;
shubreg_t i_rsvd_5 : 1;
shubreg_t i_suppl : 14;
shubreg_t i_rsvd_4 : 1;
shubreg_t i_source : 14;
shubreg_t i_rsvd_3 : 1;
shubreg_t i_err_type : 4;
shubreg_t i_rsvd_2 : 4;
shubreg_t i_overrun : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_valid : 1;
shubreg_t i_rsvd : 13;
} ii_iieph1_fld_s;
} ii_iieph1_u_t;
/************************************************************************
* *
* This register holds the Address field from the header flit of an *
* incoming erroneous Duplonet packet, along with the tail bit which *
* accompanied this header flit. This register is essentially an *
* extension of IIEPH1. Two registers were necessary because the 64 *
* bits available in only a single register were insufficient to *
* capture the entire header flit of an erroneous packet. *
* *
************************************************************************/
typedef union ii_iieph2_u {
shubreg_t ii_iieph2_regval;
struct {
shubreg_t i_rsvd_0 : 3;
shubreg_t i_address : 47;
shubreg_t i_rsvd_1 : 10;
shubreg_t i_tail : 1;
shubreg_t i_rsvd : 3;
} ii_iieph2_fld_s;
} ii_iieph2_u_t;
/******************************/
/************************************************************************
* *
* This register's value is a bit vector that guards access from SXBs *
* to local registers within the II as well as to external Crosstalk *
* widgets *
* *
************************************************************************/
typedef union ii_islapr_u {
shubreg_t ii_islapr_regval;
struct {
shubreg_t i_region : 64;
} ii_islapr_fld_s;
} ii_islapr_u_t;
/************************************************************************
* *
* A write to this register of the 56-bit value "Pup+Bun" will cause *
* the bit in the ISLAPR register corresponding to the region of the *
* requestor to be set (access allowed). (
* *
************************************************************************/
typedef union ii_islapo_u {
shubreg_t ii_islapo_regval;
struct {
shubreg_t i_io_sbx_ovrride : 56;
shubreg_t i_rsvd : 8;
} ii_islapo_fld_s;
} ii_islapo_u_t;
/************************************************************************
* *
* Determines how long the wrapper will wait aftr an interrupt is *
* initially issued from the II before it times out the outstanding *
* interrupt and drops it from the interrupt queue. *
* *
************************************************************************/
typedef union ii_iwi_u {
shubreg_t ii_iwi_regval;
struct {
shubreg_t i_prescale : 24;
shubreg_t i_rsvd : 8;
shubreg_t i_timeout : 8;
shubreg_t i_rsvd1 : 8;
shubreg_t i_intrpt_retry_period : 8;
shubreg_t i_rsvd2 : 8;
} ii_iwi_fld_s;
} ii_iwi_u_t;
/************************************************************************
* *
* Log errors which have occurred in the II wrapper. The errors are *
* cleared by writing to the IECLR register. *
* *
************************************************************************/
typedef union ii_iwel_u {
shubreg_t ii_iwel_regval;
struct {
shubreg_t i_intr_timed_out : 1;
shubreg_t i_rsvd : 7;
shubreg_t i_cam_overflow : 1;
shubreg_t i_cam_read_miss : 1;
shubreg_t i_rsvd1 : 2;
shubreg_t i_ioq_rep_underflow : 1;
shubreg_t i_ioq_req_underflow : 1;
shubreg_t i_ioq_rep_overflow : 1;
shubreg_t i_ioq_req_overflow : 1;
shubreg_t i_iiq_rep_overflow : 1;
shubreg_t i_iiq_req_overflow : 1;
shubreg_t i_rsvd2 : 6;
shubreg_t i_ii_xn_rep_cred_over_under: 1;
shubreg_t i_ii_xn_req_cred_over_under: 1;
shubreg_t i_rsvd3 : 6;
shubreg_t i_ii_xn_invalid_cmd : 1;
shubreg_t i_xn_ii_invalid_cmd : 1;
shubreg_t i_rsvd4 : 30;
} ii_iwel_fld_s;
} ii_iwel_u_t;
/************************************************************************
* *
* Controls the II wrapper. *
* *
************************************************************************/
typedef union ii_iwc_u {
shubreg_t ii_iwc_regval;
struct {
shubreg_t i_dma_byte_swap : 1;
shubreg_t i_rsvd : 3;
shubreg_t i_cam_read_lines_reset : 1;
shubreg_t i_rsvd1 : 3;
shubreg_t i_ii_xn_cred_over_under_log: 1;
shubreg_t i_rsvd2 : 19;
shubreg_t i_xn_rep_iq_depth : 5;
shubreg_t i_rsvd3 : 3;
shubreg_t i_xn_req_iq_depth : 5;
shubreg_t i_rsvd4 : 3;
shubreg_t i_iiq_depth : 6;
shubreg_t i_rsvd5 : 12;
shubreg_t i_force_rep_cred : 1;
shubreg_t i_force_req_cred : 1;
} ii_iwc_fld_s;
} ii_iwc_u_t;
/************************************************************************
* *
* Status in the II wrapper. *
* *
************************************************************************/
typedef union ii_iws_u {
shubreg_t ii_iws_regval;
struct {
shubreg_t i_xn_rep_iq_credits : 5;
shubreg_t i_rsvd : 3;
shubreg_t i_xn_req_iq_credits : 5;
shubreg_t i_rsvd1 : 51;
} ii_iws_fld_s;
} ii_iws_u_t;
/************************************************************************
* *
* Masks errors in the IWEL register. *
* *
************************************************************************/
typedef union ii_iweim_u {
shubreg_t ii_iweim_regval;
struct {
shubreg_t i_intr_timed_out : 1;
shubreg_t i_rsvd : 7;
shubreg_t i_cam_overflow : 1;
shubreg_t i_cam_read_miss : 1;
shubreg_t i_rsvd1 : 2;
shubreg_t i_ioq_rep_underflow : 1;
shubreg_t i_ioq_req_underflow : 1;
shubreg_t i_ioq_rep_overflow : 1;
shubreg_t i_ioq_req_overflow : 1;
shubreg_t i_iiq_rep_overflow : 1;
shubreg_t i_iiq_req_overflow : 1;
shubreg_t i_rsvd2 : 6;
shubreg_t i_ii_xn_rep_cred_overflow : 1;
shubreg_t i_ii_xn_req_cred_overflow : 1;
shubreg_t i_rsvd3 : 6;
shubreg_t i_ii_xn_invalid_cmd : 1;
shubreg_t i_xn_ii_invalid_cmd : 1;
shubreg_t i_rsvd4 : 30;
} ii_iweim_fld_s;
} ii_iweim_u_t;
/************************************************************************
* *
* A write to this register causes a particular field in the *
* corresponding widget's PRB entry to be adjusted up or down by 1. *
* This counter should be used when recovering from error and reset *
* conditions. Note that software would be capable of causing *
* inadvertent overflow or underflow of these counters. *
* *
************************************************************************/
typedef union ii_ipca_u {
shubreg_t ii_ipca_regval;
struct {
shubreg_t i_wid : 4;
shubreg_t i_adjust : 1;
shubreg_t i_rsvd_1 : 3;
shubreg_t i_field : 2;
shubreg_t i_rsvd : 54;
} ii_ipca_fld_s;
} ii_ipca_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte0a_u {
shubreg_t ii_iprte0a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte0a_fld_s;
} ii_iprte0a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte1a_u {
shubreg_t ii_iprte1a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;
} ii_iprte1a_fld_s;
} ii_iprte1a_u_t;
/************************************************************************
* *
* There are 8 instances of this register. This register contains *
* the information that the II has to remember once it has launched a *
* PIO Read operation. The contents are used to form the correct *
* Router Network packet and direct the Crosstalk reply to the *
* appropriate processor. *
* *
************************************************************************/
typedef union ii_iprte2a_u {
shubreg_t ii_iprte2a_regval;
struct {
shubreg_t i_rsvd_1 : 54;
shubreg_t i_widget : 4;
shubreg_t i_to_cnt : 5;
shubreg_t i_vld : 1;