VHDL/FPGA/Verilog

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MultiPlatform

TRAFFIC_MUX.VHD：源码内容

							LIBRARY IEEE;   
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;   
USE IEEE.std_logic_arith.all;
entity traffic_mux is
  port(reset: in std_logic;
       clk:in std_logic;
       ena_scan:in std_logic;
       recount:in std_logic; 
       sign_state: in std_logic_vector(1 downto 0);
       load: out std_logic_vector(7 downto 0));
end;   
--define the signal_structure and flow of the device
architecture BEHAVIOR of traffic_mux is
CONSTANT yellow0_time: integer := 5; 
CONSTANT green0_time: integer := 20;
CONSTANT yellow1_time: integer := 5;
CONSTANT green1_time : integer := 20; 
begin
  load_time:process(reset,clk)
  begin
     if reset='1' then
        load<="00000000"; 
     elsif (clk'event and clk='1') then
        if (ena_scan='1' and recount = '1') then
           CASE sign_state IS
            	WHEN "00" =>
                   load <= CONV_STD_LOGIC_VECTOR(green1_time,8);
        	    WHEN "01" =>
                   load <= CONV_STD_LOGIC_VECTOR(yellow0_time,8);
        	    WHEN "10" =>
                   load <= CONV_STD_LOGIC_VECTOR(green0_time,8);
        	    WHEN OTHERS =>
                   load <= CONV_STD_LOGIC_VECTOR(yellow1_time,8);
           END CASE;
        end if;
     end if;
  end process;
end BEHAVIOR;

						