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pci_conf_space(1).v：源码内容

latency_timer <= 8'h00 ; cache_line_size_reg <= 8'h00 ;
// ALL pci_base address registers are the same as pci_baX registers !
interrupt_line <= 8'h00 ;
`ifdef HOST
`ifdef NO_CNF_IMAGE // if PCI bridge is HOST and IMAGE0 is assigned as general image space
`ifdef PCI_IMAGE0
pci_img_ctrl0_bit2_1 <= {`PCI_AT_EN0, 1'b0} ;
pci_ba0_bit31_8 <= 24'h0000_00 ;
pci_ba0_bit0 <= `PCI_BA0_MEM_IO ;
pci_am0 <= `PCI_AM0 ;
pci_ta0 <= `PCI_TA0 ;//fr2201 translation address
`endif
`else
pci_ba0_bit31_8 <= 24'h0000_00 ;
`endif
`endif
`ifdef GUEST
pci_ba0_bit31_8 <= 24'h0000_00 ;
`endif
pci_img_ctrl1_bit2_1 <= {`PCI_AT_EN1, 1'b0} ;
pci_ba1_bit31_8 <= 24'h0000_00 ;
`ifdef HOST
pci_ba1_bit0 <= `PCI_BA1_MEM_IO ;
`endif
pci_am1 <= `PCI_AM1;
pci_ta1 <= `PCI_TA1 ;//FR2201 translation address ;
`ifdef PCI_IMAGE2
pci_img_ctrl2_bit2_1 <= {`PCI_AT_EN2, 1'b0} ;
pci_ba2_bit31_8 <= 24'h0000_00 ;
`ifdef HOST
pci_ba2_bit0 <= `PCI_BA2_MEM_IO ;
`endif
pci_am2 <= `PCI_AM2;
pci_ta2 <= `PCI_TA2 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE3
pci_img_ctrl3_bit2_1 <= {`PCI_AT_EN3, 1'b0} ; //FR2201 when defined enabled
pci_ba3_bit31_8 <= 24'h0000_00 ;
`ifdef HOST
pci_ba3_bit0 <= `PCI_BA3_MEM_IO ;
`endif
pci_am3 <= `PCI_AM3;
pci_ta3 <= `PCI_TA3 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE4
pci_img_ctrl4_bit2_1 <= {`PCI_AT_EN4, 1'b0} ; //FR2201 when defined enabled
pci_ba4_bit31_8 <= 24'h0000_00 ;
`ifdef HOST
pci_ba4_bit0 <= `PCI_BA4_MEM_IO ;
`endif
pci_am4 <= `PCI_AM4;
pci_ta4 <= `PCI_TA4 ;//FR2201 translation address ;
`endif
`ifdef PCI_IMAGE5
pci_img_ctrl5_bit2_1 <= {`PCI_AT_EN5, 1'b0} ; //FR2201 when defined enabled
pci_ba5_bit31_8 <= 24'h0000_00 ;
`ifdef HOST
pci_ba5_bit0 <= `PCI_BA5_MEM_IO ;
`endif
pci_am5 <= `PCI_AM5; //FR2201 pci_am0
pci_ta5 <= `PCI_TA5 ;//FR2201 translation address ;
`endif
/*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ;
/*pci_err_addr ;*/
/*pci_err_data ;*/
//
wb_img_ctrl1_bit2_0 <= {`WB_AT_EN1, 2'b00} ;
wb_ba1_bit31_12 <=`WB_BA1; //FR2201 Address bar
wb_ba1_bit0 <=`WB_BA1_MEM_IO;//
wb_am1 <= `WB_AM1 ;//FR2201 Address mask
wb_ta1 <= `WB_TA1 ;//FR2201 20'h0000_0 ;
`ifdef WB_IMAGE2
wb_img_ctrl2_bit2_0 <= {`WB_AT_EN2, 2'b00} ;
wb_ba2_bit31_12 <=`WB_BA2; //FR2201 Address bar
wb_ba2_bit0 <=`WB_BA2_MEM_IO;//
wb_am2 <=`WB_AM2 ;//FR2201 Address mask
wb_ta2 <=`WB_TA2 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE3
wb_img_ctrl3_bit2_0 <= {`WB_AT_EN3, 2'b00} ;
wb_ba3_bit31_12 <=`WB_BA3; //FR2201 Address bar
wb_ba3_bit0 <=`WB_BA3_MEM_IO;//
wb_am3 <=`WB_AM3 ;//FR2201 Address mask
wb_ta3 <=`WB_TA3 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE4
wb_img_ctrl4_bit2_0 <= {`WB_AT_EN4, 2'b00} ;
wb_ba4_bit31_12 <=`WB_BA4; //FR2201 Address bar
wb_ba4_bit0 <=`WB_BA4_MEM_IO;//
wb_am4 <=`WB_AM4 ;//FR2201 Address mask
wb_ta4 <=`WB_TA4 ;//FR2201 translation address ;
`endif
`ifdef WB_IMAGE5
wb_img_ctrl5_bit2_0 <= {`WB_AT_EN5, 2'b00} ;
wb_ba5_bit31_12 <=`WB_BA5; //FR2201 Address bar ;
wb_ba5_bit0 <=`WB_BA5_MEM_IO;//FR2201 1'h0 ;
wb_am5 <=`WB_AM5 ;//FR2201 Address mask
wb_ta5 <=`WB_TA5 ;//FR2201 translation address ;
`endif
/*wb_err_cs_bit31_24 ; wb_err_cs_bit10 ; wb_err_cs_bit9 ; wb_err_cs_bit8 ;*/ wb_err_cs_bit0 <= 1'h0 ;
/*wb_err_addr ;*/
/*wb_err_data ;*/
`ifdef HOST
cnf_addr_bit23_2 <= 22'h0000_00 ; cnf_addr_bit0 <= 1'h0 ;
`endif
icr_bit31 <= 1'h0 ;
`ifdef HOST
icr_bit2_0 <= 3'h0 ;
icr_bit4_3 <= 2'h0 ;
`else
icr_bit2_0[2:0] <= 3'h0 ;
`endif
/*isr_bit4_3 ; isr_bit2_0 ;*/
// Not register bit; used only internally after reset!
init_complete <= 1'b0 ;
`ifdef GUEST
rst_inactive_sync <= 1'b0 ;
rst_inactive <= 1'b0 ;
`endif
`ifdef PCI_CPCI_HS_IMPLEMENT
/*hs_ins hs_ext*/ hs_loo <= 1'b0; hs_eim <= 1'b0;
// Not register bits; used only internally after reset!
/*hs_ins_armed hs_ext_armed*/
`endif
end
/* -----------------------------------------------------------------------------------------------------------
Following register bits should have asynchronous RESET & SET! That is why they are IMPLEMENTED separately
after this ALWAYS block!!! (for every register bit, there are two D-FF implemented)
status_bit15_11[15] <= 1'b1 ;
status_bit15_11[14] <= 1'b1 ;
status_bit15_11[13] <= 1'b1 ;
status_bit15_11[12] <= 1'b1 ;
status_bit15_11[11] <= 1'b1 ;
status_bit8 <= 1'b1 ;
pci_err_cs_bit10 <= 1'b1 ;
pci_err_cs_bit9 <= 1'b1 ;
pci_err_cs_bit8 <= 1'b1 ;
pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ;
pci_err_addr <= pci_error_addr ;
pci_err_data <= pci_error_data ;
wb_err_cs_bit10 <= 1'b1 ;
wb_err_cs_bit9 <= 1'b1 ;
wb_err_cs_bit8 <= 1'b1 ;
wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ;
wb_err_addr <= wb_error_addr ;
wb_err_data <= wb_error_data ;
isr_bit4_0[4] <= 1'b1 & icr_bit4_0[4] ;
isr_bit4_0[3] <= 1'b1 & icr_bit4_0[3] ;
isr_bit4_0[2] <= 1'b1 & icr_bit4_0[2] ;
isr_bit4_0[1] <= 1'b1 & icr_bit4_0[1] ;
isr_bit4_0[0] <= 1'b1 & icr_bit4_0[0] ;
hs_ins; hs_ext;
-----------------------------------------------------------------------------------------------------------*/
// Here follows normal writting to registers (only to their valid bits) !
else
begin
if (w_we)
begin
// PCI header - configuration space
if (w_reg_select_dec[0]) // w_conf_address[5:2] = 4'h1:
begin
if (~w_byte_en[1])
command_bit8 <= w_conf_data[8] ;
if (~w_byte_en[0])
begin
command_bit6 <= w_conf_data[6] ;
command_bit2_0 <= w_conf_data[2:0] ;
end
end
if (w_reg_select_dec[1]) // w_conf_address[5:2] = 4'h3:
begin
if (~w_byte_en[1])
latency_timer <= w_conf_data[15:8] ;
if (~w_byte_en[0])
cache_line_size_reg <= w_conf_data[7:0] ;
end
// if (w_reg_select_dec[4]) // w_conf_address[5:2] = 4'h4:
// Also used with IMAGE0
// if (w_reg_select_dec[8]) // w_conf_address[5:2] = 4'h5:
// Also used with IMAGE1
// if (w_reg_select_dec[12]) // w_conf_address[5:2] = 4'h6:
// Also used with IMAGE2
// if (w_reg_select_dec[16]) // w_conf_address[5:2] = 4'h7:
// Also used with IMAGE3
// if (w_reg_select_dec[20]) // w_conf_address[5:2] = 4'h8:
// Also used with IMAGE4
// if (w_reg_select_dec[24]) // w_conf_address[5:2] = 4'h9:
// Also used with IMAGE5 and IMAGE6
if (w_reg_select_dec[2]) // w_conf_address[5:2] = 4'hf:
begin
if (~w_byte_en[0])
interrupt_line <= w_conf_data[7:0] ;
end
// PCI target - configuration space
`ifdef HOST
`ifdef NO_CNF_IMAGE
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
if (w_reg_select_dec[3]) // case (w_conf_address[7:2]) = `P_IMG_CTRL0_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl0_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR:
begin
if (~w_byte_en[3])
pci_ba0_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba0_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba0_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
if (~w_byte_en[0])
pci_ba0_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[5]) // case (w_conf_address[7:2]) = `P_AM0_ADDR:
begin
if (~w_byte_en[3])
pci_am0[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am0[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am0[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[6]) // case (w_conf_address[7:2]) = `P_TA0_ADDR:
begin
if (~w_byte_en[3])
pci_ta0[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta0[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta0[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`endif
`else
if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR:
begin
if (~w_byte_en[3])
pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ;
if (~w_byte_en[2])
pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ;
if (~w_byte_en[1])
pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ;
end
`endif
`endif
`ifdef GUEST
if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR:
begin
if (~w_byte_en[3])
pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ;
if (~w_byte_en[2])
pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ;
if (~w_byte_en[1])
pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ;
end
`endif
if (w_reg_select_dec[7]) // case (w_conf_address[7:2]) = `P_IMG_CTRL1_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl1_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[8]) // case (w_conf_address[7:2]) = `P_BA1_ADDR:
begin
if (~w_byte_en[3])
pci_ba1_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba1_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba1_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
`ifdef HOST
if (~w_byte_en[0])
pci_ba1_bit0 <= w_conf_data[0] ;
`endif
end
if (w_reg_select_dec[9]) // case (w_conf_address[7:2]) = `P_AM1_ADDR:
begin
if (~w_byte_en[3])
pci_am1[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am1[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am1[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[10]) // case (w_conf_address[7:2]) = `P_TA1_ADDR:
begin
if (~w_byte_en[3])
pci_ta1[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta1[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta1[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`ifdef PCI_IMAGE2
if (w_reg_select_dec[11]) // case (w_conf_address[7:2]) = `P_IMG_CTRL2_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl2_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[12]) // case (w_conf_address[7:2]) = `P_BA2_ADDR:
begin
if (~w_byte_en[3])
pci_ba2_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba2_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba2_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
`ifdef HOST
if (~w_byte_en[0])
pci_ba2_bit0 <= w_conf_data[0] ;
`endif
end
if (w_reg_select_dec[13]) // case (w_conf_address[7:2]) = `P_AM2_ADDR:
begin
if (~w_byte_en[3])
pci_am2[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am2[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am2[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[14]) // case (w_conf_address[7:2]) = `P_TA2_ADDR:
begin
if (~w_byte_en[3])
pci_ta2[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta2[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta2[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`endif
`ifdef PCI_IMAGE3
if (w_reg_select_dec[15]) // case (w_conf_address[7:2]) = `P_IMG_CTRL3_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl3_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[16]) // case (w_conf_address[7:2]) = `P_BA3_ADDR:
begin
if (~w_byte_en[3])
pci_ba3_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba3_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba3_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
`ifdef HOST
if (~w_byte_en[0])
pci_ba3_bit0 <= w_conf_data[0] ;
`endif
end
if (w_reg_select_dec[17]) // case (w_conf_address[7:2]) = `P_AM3_ADDR:
begin
if (~w_byte_en[3])
pci_am3[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am3[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am3[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[18]) // case (w_conf_address[7:2]) = `P_TA3_ADDR:
begin
if (~w_byte_en[3])
pci_ta3[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta3[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta3[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`endif
`ifdef PCI_IMAGE4
if (w_reg_select_dec[19]) // case (w_conf_address[7:2]) = `P_IMG_CTRL4_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl4_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[20]) // case (w_conf_address[7:2]) = `P_BA4_ADDR:
begin
if (~w_byte_en[3])
pci_ba4_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba4_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba4_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
`ifdef HOST
if (~w_byte_en[0])
pci_ba4_bit0 <= w_conf_data[0] ;
`endif
end
if (w_reg_select_dec[21]) // case (w_conf_address[7:2]) = `P_AM4_ADDR:
begin
if (~w_byte_en[3])
pci_am4[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am4[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am4[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[22]) // case (w_conf_address[7:2]) = `P_TA4_ADDR:
begin
if (~w_byte_en[3])
pci_ta4[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta4[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta4[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`endif
`ifdef PCI_IMAGE5
if (w_reg_select_dec[23]) // case (w_conf_address[7:2]) = `P_IMG_CTRL5_ADDR:
begin
if (~w_byte_en[0])
pci_img_ctrl5_bit2_1 <= w_conf_data[2:1] ;
end
if (w_reg_select_dec[24]) // case (w_conf_address[7:2]) = `P_BA5_ADDR:
begin
if (~w_byte_en[3])
pci_ba5_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ba5_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ba5_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ;
`ifdef HOST
if (~w_byte_en[0])
pci_ba5_bit0 <= w_conf_data[0] ;
`endif
end
if (w_reg_select_dec[25]) // case (w_conf_address[7:2]) = `P_AM5_ADDR:
begin
if (~w_byte_en[3])
pci_am5[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_am5[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_am5[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
if (w_reg_select_dec[26]) // case (w_conf_address[7:2]) = `P_TA5_ADDR:
begin
if (~w_byte_en[3])
pci_ta5[31:24] <= w_conf_pdata_reduced[31:24] ;
if (~w_byte_en[2])
pci_ta5[23:16] <= w_conf_pdata_reduced[23:16] ;
if (~w_byte_en[1])
pci_ta5[15: 8] <= w_conf_pdata_reduced[15: 8] ;
end
`endif
if (w_reg_select_dec[27]) // case (w_conf_address[7:2]) = `P_ERR_CS_ADDR:
begin
if (~w_byte_en[0])
pci_err_cs_bit0 <= w_conf_data[0] ;
end
// WB slave - configuration space
if (w_reg_select_dec[30]) // case (w_conf_address[7:2]) = `W_IMG_CTRL1_ADDR:
begin
if (~w_byte_en[0])
wb_img_ctrl1_bit2_0 <= w_conf_data[2:0] ;
end
if (w_reg_select_dec[31]) // case (w_conf_address[7:2]) = `W_BA1_ADDR:
begin
if (~w_byte_en[3])
wb_ba1_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ba1_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ba1_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ;
if (~w_byte_en[0])
wb_ba1_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[32]) // case (w_conf_address[7:2]) = `W_AM1_ADDR:
begin
if (~w_byte_en[3])
wb_am1[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_am1[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_am1[15:12] <= w_conf_wdata_reduced[15:12] ;
end
if (w_reg_select_dec[33]) // case (w_conf_address[7:2]) = `W_TA1_ADDR:
begin
if (~w_byte_en[3])
wb_ta1[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ta1[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ta1[15:12] <= w_conf_wdata_reduced[15:12] ;
end
`ifdef WB_IMAGE2
if (w_reg_select_dec[34]) // case (w_conf_address[7:2]) = `W_IMG_CTRL2_ADDR:
begin
if (~w_byte_en[0])
wb_img_ctrl2_bit2_0 <= w_conf_data[2:0] ;
end
if (w_reg_select_dec[35]) // case (w_conf_address[7:2]) = `W_BA2_ADDR:
begin
if (~w_byte_en[3])
wb_ba2_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ba2_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ba2_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ;
if (~w_byte_en[0])
wb_ba2_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[36]) // case (w_conf_address[7:2]) = `W_AM2_ADDR:
begin
if (~w_byte_en[3])
wb_am2[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_am2[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_am2[15:12] <= w_conf_wdata_reduced[15:12] ;
end
if (w_reg_select_dec[37]) // case (w_conf_address[7:2]) = `W_TA2_ADDR:
begin
if (~w_byte_en[3])
wb_ta2[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ta2[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ta2[15:12] <= w_conf_wdata_reduced[15:12] ;
end
`endif
`ifdef WB_IMAGE3
if (w_reg_select_dec[38]) // case (w_conf_address[7:2]) = `W_IMG_CTRL3_ADDR:
begin
if (~w_byte_en[0])
wb_img_ctrl3_bit2_0 <= w_conf_data[2:0] ;
end
if (w_reg_select_dec[39]) // case (w_conf_address[7:2]) = `W_BA3_ADDR:
begin
if (~w_byte_en[3])
wb_ba3_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ba3_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ba3_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ;
if (~w_byte_en[0])
wb_ba3_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[40]) // case (w_conf_address[7:2]) = `W_AM3_ADDR:
begin
if (~w_byte_en[3])
wb_am3[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_am3[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_am3[15:12] <= w_conf_wdata_reduced[15:12] ;
end
if (w_reg_select_dec[41]) // case (w_conf_address[7:2]) = `W_TA3_ADDR:
begin
if (~w_byte_en[3])
wb_ta3[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ta3[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ta3[15:12] <= w_conf_wdata_reduced[15:12] ;
end
`endif
`ifdef WB_IMAGE4
if (w_reg_select_dec[42]) // case (w_conf_address[7:2]) = `W_IMG_CTRL4_ADDR:
begin
if (~w_byte_en[0])
wb_img_ctrl4_bit2_0 <= w_conf_data[2:0] ;
end
if (w_reg_select_dec[43]) // case (w_conf_address[7:2]) = `W_BA4_ADDR:
begin
if (~w_byte_en[3])
wb_ba4_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ba4_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ba4_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ;
if (~w_byte_en[0])
wb_ba4_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[44]) // case (w_conf_address[7:2]) = `W_AM4_ADDR:
begin
if (~w_byte_en[3])
wb_am4[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_am4[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_am4[15:12] <= w_conf_wdata_reduced[15:12] ;
end
if (w_reg_select_dec[45]) // case (w_conf_address[7:2]) = `W_TA4_ADDR:
begin
if (~w_byte_en[3])
wb_ta4[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ta4[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ta4[15:12] <= w_conf_wdata_reduced[15:12] ;
end
`endif
`ifdef WB_IMAGE5
if (w_reg_select_dec[46]) // case (w_conf_address[7:2]) = `W_IMG_CTRL5_ADDR:
begin
if (~w_byte_en[0])
wb_img_ctrl5_bit2_0 <= w_conf_data[2:0] ;
end
if (w_reg_select_dec[47]) // case (w_conf_address[7:2]) = `W_BA5_ADDR:
begin
if (~w_byte_en[3])
wb_ba5_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ba5_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ba5_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ;
if (~w_byte_en[0])
wb_ba5_bit0 <= w_conf_data[0] ;
end
if (w_reg_select_dec[48]) // case (w_conf_address[7:2]) = `W_AM5_ADDR:
begin
if (~w_byte_en[3])
wb_am5[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_am5[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_am5[15:12] <= w_conf_wdata_reduced[15:12] ;
end
if (w_reg_select_dec[49]) // case (w_conf_address[7:2]) = `W_TA5_ADDR:
begin
if (~w_byte_en[3])
wb_ta5[31:24] <= w_conf_wdata_reduced[31:24] ;
if (~w_byte_en[2])
wb_ta5[23:16] <= w_conf_wdata_reduced[23:16] ;
if (~w_byte_en[1])
wb_ta5[15:12] <= w_conf_wdata_reduced[15:12] ;
end
`endif
if (w_reg_select_dec[50]) // case (w_conf_address[7:2]) = `W_ERR_CS_ADDR:
begin
if (~w_byte_en[0])
wb_err_cs_bit0 <= w_conf_data[0] ;
end
`ifdef HOST
if (w_reg_select_dec[53]) // case (w_conf_address[7:2]) = `CNF_ADDR_ADDR:
begin
if (~w_byte_en[2])
cnf_addr_bit23_2[23:16] <= w_conf_data[23:16] ;
if (~w_byte_en[1])
cnf_addr_bit23_2[15:8] <= w_conf_data[15:8] ;
if (~w_byte_en[0])
begin
cnf_addr_bit23_2[7:2] <= w_conf_data[7:2] ;
cnf_addr_bit0 <= w_conf_data[0] ;
end
end
`endif
// `CNF_DATA_ADDR: implemented elsewhere !!!
// `INT_ACK_ADDR : implemented elsewhere !!!
if (w_reg_select_dec[54]) // case (w_conf_address[7:2]) = `ICR_ADDR:
begin
if (~w_byte_en[3])
icr_bit31 <= w_conf_data[31] ;
if (~w_byte_en[0])
begin
`ifdef HOST
icr_bit4_3 <= w_conf_data[4:3] ;
icr_bit2_0 <= w_conf_data[2:0] ;
`else
icr_bit2_0[2:0] <= w_conf_data[2:0] ;
`endif
end
end
`ifdef PCI_CPCI_HS_IMPLEMENT
if (w_reg_select_dec[56])
begin
if (~w_byte_en[2])
begin
hs_loo <= w_conf_data[19];
hs_eim <= w_conf_data[17];
end
end
`endif
end // end of we
// Not register bits; used only internally after reset!
`ifdef GUEST
rst_inactive_sync <= 1'b1 ;
rst_inactive <= rst_inactive_sync ;
`endif
if (rst_inactive & ~init_complete & init_cfg_done)
init_complete <= 1'b1 ;
end
end
// implementation of read only device identification registers
always@(posedge w_clock or posedge reset)
begin
if (reset)
begin
r_vendor_id <= `HEADER_VENDOR_ID ;
r_device_id <= `HEADER_DEVICE_ID ;
r_revision_id <= `HEADER_REVISION_ID ;
r_subsys_vendor_id <= `HEADER_SUBSYS_VENDOR_ID ;
r_subsys_id <= `HEADER_SUBSYS_ID ;
r_max_lat <= `HEADER_MAX_LAT ;
r_min_gnt <= `HEADER_MIN_GNT ;
end else
begin
if (init_we)
begin
if (spoci_reg_num == 'h0)
begin
r_vendor_id <= spoci_dat[15: 0] ;
r_device_id <= spoci_dat[31:16] ;
end
if (spoci_reg_num == 'hB)
begin
r_subsys_vendor_id <= spoci_dat[15: 0] ;
r_subsys_id <= spoci_dat[31:16] ;
end
if (spoci_reg_num == 'h2)
begin
r_revision_id <= spoci_dat[ 7: 0] ;
end
if (spoci_reg_num == 'hF)
begin
r_max_lat <= spoci_dat[31:24] ;
r_min_gnt <= spoci_dat[23:16] ;
end
end
end
end
// This signals are synchronous resets for registers, whic occures when asynchronous RESET is '1' or
// data '1' is synchronously written into them!
reg delete_status_bit15 ;
reg delete_status_bit14 ;
reg delete_status_bit13 ;
reg delete_status_bit12 ;
reg delete_status_bit11 ;
reg delete_status_bit8 ;
reg delete_pci_err_cs_bit8 ;
reg delete_wb_err_cs_bit8 ;
reg delete_isr_bit4 ;
reg delete_isr_bit3 ;
reg delete_isr_bit2 ;
reg delete_isr_bit1 ;
// This are aditional register bits, which are resets when their value is '1' !!!
always@(w_we or w_reg_select_dec or w_conf_data or w_byte_en)
begin
// I' is written into, then it also sets signals to '1'
delete_status_bit15 = w_conf_data[31] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit14 = w_conf_data[30] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit13 = w_conf_data[29] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit12 = w_conf_data[28] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit11 = w_conf_data[27] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_status_bit8 = w_conf_data[24] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ;
delete_pci_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[27] ;
delete_wb_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[50] ;
delete_isr_bit4 = w_conf_data[4] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit3 = w_conf_data[3] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit2 = w_conf_data[2] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
delete_isr_bit1 = w_conf_data[1] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ;
end
// STATUS BITS of PCI Header status register
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[15] <= 1'b0 ;
else
begin
if (perr_in) // Synchronous set
status_bit15_11[15] <= 1'b1 ;
else if (delete_status_bit15) // Synchronous reset
status_bit15_11[15] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[14] <= 1'b0 ;
else
begin
if (serr_in) // Synchronous set
status_bit15_11[14] <= 1'b1 ;
else if (delete_status_bit14) // Synchronous reset
status_bit15_11[14] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[13] <= 1'b0 ;
else
begin
if (master_abort_recv) // Synchronous set
status_bit15_11[13] <= 1'b1 ;
else if (delete_status_bit13) // Synchronous reset
status_bit15_11[13] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[12] <= 1'b0 ;
else
begin
if (target_abort_recv) // Synchronous set
status_bit15_11[12] <= 1'b1 ;
else if (delete_status_bit12) // Synchronous reset
status_bit15_11[12] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[11] <= 1'b0 ;
else
begin
if (target_abort_set) // Synchronous set
status_bit15_11[11] <= 1'b1 ;
else if (delete_status_bit11) // Synchronous reset
status_bit15_11[11] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit8 <= 1'b0 ;
else
begin
if (master_data_par_err) // Synchronous set
status_bit8 <= 1'b1 ;
else if (delete_status_bit8) // Synchronous reset
status_bit8 <= 1'b0 ;
end
end
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
reg [15:11] set_status_bit15_11;
reg set_status_bit8;
wire delete_set_status_bit15;
wire delete_set_status_bit14;
wire delete_set_status_bit13;
wire delete_set_status_bit12;
wire delete_set_status_bit11;
wire delete_set_status_bit8;
wire block_set_status_bit15;
wire block_set_status_bit14;
wire block_set_status_bit13;
wire block_set_status_bit12;
wire block_set_status_bit11;
wire block_set_status_bit8;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_15
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit15),
.block_set_out (block_set_status_bit15),
.delete_in (delete_status_bit15)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit15_11[15] <= 1'b0 ;
else
begin
if (perr_in) // Synchronous set
set_status_bit15_11[15] <= 1'b1 ;
else if (delete_set_status_bit15) // Synchronous reset
set_status_bit15_11[15] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_14
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit14),
.block_set_out (block_set_status_bit14),
.delete_in (delete_status_bit14)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit15_11[14] <= 1'b0 ;
else
begin
if (serr_in) // Synchronous set
set_status_bit15_11[14] <= 1'b1 ;
else if (delete_set_status_bit14) // Synchronous reset
set_status_bit15_11[14] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_13
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit13),
.block_set_out (block_set_status_bit13),
.delete_in (delete_status_bit13)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit15_11[13] <= 1'b0 ;
else
begin
if (master_abort_recv) // Synchronous set
set_status_bit15_11[13] <= 1'b1 ;
else if (delete_set_status_bit13) // Synchronous reset
set_status_bit15_11[13] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_12
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit12),
.block_set_out (block_set_status_bit12),
.delete_in (delete_status_bit12)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit15_11[12] <= 1'b0 ;
else
begin
if (target_abort_recv) // Synchronous set
set_status_bit15_11[12] <= 1'b1 ;
else if (delete_set_status_bit12) // Synchronous reset
set_status_bit15_11[12] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_11
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit11),
.block_set_out (block_set_status_bit11),
.delete_in (delete_status_bit11)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit15_11[11] <= 1'b0 ;
else
begin
if (target_abort_set) // Synchronous set
set_status_bit15_11[11] <= 1'b1 ;
else if (delete_set_status_bit11) // Synchronous reset
set_status_bit15_11[11] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_status_8
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_status_bit8),
.block_set_out (block_set_status_bit8),
.delete_in (delete_status_bit8)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_status_bit8 <= 1'b0 ;
else
begin
if (master_data_par_err) // Synchronous set
set_status_bit8 <= 1'b1 ;
else if (delete_set_status_bit8) // Synchronous reset
set_status_bit8 <= 1'b0 ;
end
end
wire [5:0] status_bits = {set_status_bit15_11[15] && !block_set_status_bit15,
set_status_bit15_11[14] && !block_set_status_bit14,
set_status_bit15_11[13] && !block_set_status_bit13,
set_status_bit15_11[12] && !block_set_status_bit12,
set_status_bit15_11[11] && !block_set_status_bit11,
set_status_bit8 && !block_set_status_bit8 } ;
wire [5:0] meta_status_bits ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(6, 0) status_bits_sync
(
.data_in (status_bits),
.clk_out (wb_clk),
.sync_data_out (meta_status_bits),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
begin
status_bit15_11[15:11] <= 5'b0 ;
status_bit8 <= 1'b0 ;
end
else
begin
status_bit15_11[15:11] <= meta_status_bits[5:1] ;
status_bit8 <= meta_status_bits[0] ;
end
end
`else // GUEST
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[15] <= 1'b0 ;
else
begin
if (perr_in) // Synchronous set
status_bit15_11[15] <= 1'b1 ;
else if (delete_status_bit15) // Synchronous reset
status_bit15_11[15] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[14] <= 1'b0 ;
else
begin
if (serr_in) // Synchronous set
status_bit15_11[14] <= 1'b1 ;
else if (delete_status_bit14) // Synchronous reset
status_bit15_11[14] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[13] <= 1'b0 ;
else
begin
if (master_abort_recv) // Synchronous set
status_bit15_11[13] <= 1'b1 ;
else if (delete_status_bit13) // Synchronous reset
status_bit15_11[13] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[12] <= 1'b0 ;
else
begin
if (target_abort_recv) // Synchronous set
status_bit15_11[12] <= 1'b1 ;
else if (delete_status_bit12) // Synchronous reset
status_bit15_11[12] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit15_11[11] <= 1'b0 ;
else
begin
if (target_abort_set) // Synchronous set
status_bit15_11[11] <= 1'b1 ;
else if (delete_status_bit11) // Synchronous reset
status_bit15_11[11] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
status_bit8 <= 1'b0 ;
else
begin
if (master_data_par_err) // Synchronous set
status_bit8 <= 1'b1 ;
else if (delete_status_bit8) // Synchronous reset
status_bit8 <= 1'b0 ;
end
end
`endif
`endif
// STATUS BITS of P_ERR_CS - PCI error control and status register
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
pci_err_cs_bit8 <= 1'b0 ;
else
begin
if (pci_error_sig && pci_err_cs_bit0) // Synchronous set
pci_err_cs_bit8 <= 1'b1 ;
else if (delete_pci_err_cs_bit8) // Synchronous reset
pci_err_cs_bit8 <= 1'b0 ;
end
end
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
// Set and clear FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
pci_err_cs_bit8 <= 1'b0 ;
else
begin
if (pci_error_sig && pci_err_cs_bit0) // Synchronous set
pci_err_cs_bit8 <= 1'b1 ;
else if (delete_pci_err_cs_bit8) // Synchronous reset
pci_err_cs_bit8 <= 1'b0 ;
end
end
`else // GUEST
reg set_pci_err_cs_bit8;
wire delete_set_pci_err_cs_bit8;
wire block_set_pci_err_cs_bit8;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_pci_err_cs_8
(
.set_clk_in (wb_clk),
.delete_clk_in (pci_clk),
.reset_in (reset),
.delete_set_out (delete_set_pci_err_cs_bit8),
.block_set_out (block_set_pci_err_cs_bit8),
.delete_in (delete_pci_err_cs_bit8)
);
// Setting FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_pci_err_cs_bit8 <= 1'b0 ;
else
begin
if (pci_error_sig && pci_err_cs_bit0) // Synchronous set
set_pci_err_cs_bit8 <= 1'b1 ;
else if (delete_set_pci_err_cs_bit8) // Synchronous reset
set_pci_err_cs_bit8 <= 1'b0 ;
end
end
wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ;
wire meta_pci_err_cs_bits ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1,0) pci_err_cs_bits_sync
(
.data_in (pci_err_cs_bits),
.clk_out (pci_clk),
.sync_data_out (meta_pci_err_cs_bits),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
pci_err_cs_bit8 <= 1'b0 ;
else
pci_err_cs_bit8 <= meta_pci_err_cs_bits ;
end
`endif
`endif
// Set and clear FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
pci_err_cs_bit10 <= 1'b0 ;
else
begin
if (pci_error_sig) // Synchronous report
pci_err_cs_bit10 <= pci_error_rty_exp ;
end
end
// Set and clear FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
pci_err_cs_bit9 <= 1'b0 ;
else
begin
if (pci_error_sig) // Synchronous report
pci_err_cs_bit9 <= pci_error_es ;
end
end
// Set and clear FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
begin
pci_err_cs_bit31_24 <= 8'h00 ;
pci_err_addr <= 32'h0000_0000 ;
pci_err_data <= 32'h0000_0000 ;
end
else
if (pci_error_sig) // Synchronous report
begin
pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ;
pci_err_addr <= pci_error_addr ;
pci_err_data <= pci_error_data ;
end
end
// STATUS BITS of W_ERR_CS - WB error control and status register
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
wb_err_cs_bit8 <= 1'b0 ;
else
begin
if (wb_error_sig && wb_err_cs_bit0) // Synchronous set
wb_err_cs_bit8 <= 1'b1 ;
else if (delete_wb_err_cs_bit8) // Synchronous reset
wb_err_cs_bit8 <= 1'b0 ;
end
end
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
reg set_wb_err_cs_bit8;
wire delete_set_wb_err_cs_bit8;
wire block_set_wb_err_cs_bit8;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_wb_err_cs_8
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_wb_err_cs_bit8),
.block_set_out (block_set_wb_err_cs_bit8),
.delete_in (delete_wb_err_cs_bit8)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_wb_err_cs_bit8 <= 1'b0 ;
else
begin
if (wb_error_sig && wb_err_cs_bit0) // Synchronous set
set_wb_err_cs_bit8 <= 1'b1 ;
else if (delete_set_wb_err_cs_bit8) // Synchronous reset
set_wb_err_cs_bit8 <= 1'b0 ;
end
end
wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ;
wire meta_wb_err_cs_bits ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1,0) wb_err_cs_bits_sync
(
.data_in (wb_err_cs_bits),
.clk_out (wb_clk),
.sync_data_out (meta_wb_err_cs_bits),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
wb_err_cs_bit8 <= 1'b0 ;
else
wb_err_cs_bit8 <= meta_wb_err_cs_bits ;
end
`else // GUEST
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
wb_err_cs_bit8 <= 1'b0 ;
else
begin
if (wb_error_sig && wb_err_cs_bit0) // Synchronous set
wb_err_cs_bit8 <= 1'b1 ;
else if (delete_wb_err_cs_bit8) // Synchronous reset
wb_err_cs_bit8 <= 1'b0 ;
end
end
`endif
`endif
/* // Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
wb_err_cs_bit10 <= 1'b0 ;
else
begin
if (wb_error_sig) // Synchronous report
wb_err_cs_bit10 <= wb_error_rty_exp ;
end
end */
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
wb_err_cs_bit9 <= 1'b0 ;
else
begin
if (wb_error_sig) // Synchronous report
wb_err_cs_bit9 <= wb_error_es ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
begin
wb_err_cs_bit31_24 <= 8'h00 ;
wb_err_addr <= 32'h0000_0000 ;
wb_err_data <= 32'h0000_0000 ;
end
else
if (wb_error_sig)
begin
wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ;
wb_err_addr <= wb_error_addr ;
wb_err_data <= wb_error_data ;
end
end
// SERR_INT and PERR_INT STATUS BITS of ISR - interrupt status register
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit4_3[4] <= 1'b0 ;
else
begin
if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set
isr_bit4_3[4] <= 1'b1 ;
else if (delete_isr_bit4) // Synchronous reset
isr_bit4_3[4] <= 1'b0 ;
end
end
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit4_3[3] <= 1'b0 ;
else
begin
if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set
isr_bit4_3[3] <= 1'b1 ;
else if (delete_isr_bit3) // Synchronous reset
isr_bit4_3[3] <= 1'b0 ;
end
end
`endif
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
reg [4:3] set_isr_bit4_3;
wire delete_set_isr_bit4;
wire delete_set_isr_bit3;
wire block_set_isr_bit4;
wire block_set_isr_bit3;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_isr_4
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_isr_bit4),
.block_set_out (block_set_isr_bit4),
.delete_in (delete_isr_bit4)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_isr_bit4_3[4] <= 1'b0 ;
else
begin
if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set
set_isr_bit4_3[4] <= 1'b1 ;
else if (delete_set_isr_bit4) // Synchronous reset
set_isr_bit4_3[4] <= 1'b0 ;
end
end
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_isr_3
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_isr_bit3),
.block_set_out (block_set_isr_bit3),
.delete_in (delete_isr_bit3)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_isr_bit4_3[3] <= 1'b0 ;
else
begin
if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set
set_isr_bit4_3[3] <= 1'b1 ;
else if (delete_set_isr_bit3) // Synchronous reset
set_isr_bit4_3[3] <= 1'b0 ;
end
end
wire [4:3] isr_bits4_3 = {set_isr_bit4_3[4] && !block_set_isr_bit4,
set_isr_bit4_3[3] && !block_set_isr_bit3 } ;
wire [4:3] meta_isr_bits4_3 ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(2, 0) isr_bits_sync
(
.data_in (isr_bits4_3),
.clk_out (wb_clk),
.sync_data_out (meta_isr_bits4_3),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
isr_bit4_3[4:3] <= 2'b0 ;
else
isr_bit4_3[4:3] <= meta_isr_bits4_3[4:3] ;
end
`endif
`endif
// PCI_EINT and WB_EINT STATUS BITS of ISR - interrupt status register
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
// WB_EINT STATUS BIT
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit2_0[1] <= 1'b0 ;
else
begin
if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set
isr_bit2_0[1] <= 1'b1 ;
else if (delete_isr_bit1) // Synchronous reset
isr_bit2_0[1] <= 1'b0 ;
end
end
// PCI_EINT STATUS BIT
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit2_0[2] <= 1'b0 ;
else
begin
if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set
isr_bit2_0[2] <= 1'b1 ;
else if (delete_isr_bit2) // Synchronous reset
isr_bit2_0[2] <= 1'b0 ;
end
end
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
`ifdef HOST
// WB_EINT STATUS BIT
reg set_isr_bit1;
wire delete_set_isr_bit1;
wire block_set_isr_bit1;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_isr_1
(
.set_clk_in (pci_clk),
.delete_clk_in (wb_clk),
.reset_in (reset),
.delete_set_out (delete_set_isr_bit1),
.block_set_out (block_set_isr_bit1),
.delete_in (delete_isr_bit1)
);
// Setting FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_isr_bit1 <= 1'b0 ;
else
begin
if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set
set_isr_bit1 <= 1'b1 ;
else if (delete_set_isr_bit1) // Synchronous reset
set_isr_bit1 <= 1'b0 ;
end
end
wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ;
wire meta_isr_bit1 ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) isr_bit1_sync
(
.data_in (isr_bit1),
.clk_out (wb_clk),
.sync_data_out (meta_isr_bit1),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
isr_bit2_0[1] <= 1'b0 ;
else
isr_bit2_0[1] <= meta_isr_bit1 ;
end
// PCI_EINT STATUS BIT
// Set and clear FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit2_0[2] <= 1'b0 ;
else
begin
if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set
isr_bit2_0[2] <= 1'b1 ;
else if (delete_isr_bit2) // Synchronous reset
isr_bit2_0[2] <= 1'b0 ;
end
end
`else // GUEST
// WB_EINT STATUS BIT
// Set and clear FF
always@(posedge pci_clk or posedge reset)
begin
if (reset) // Asynchronous reset
isr_bit2_0[1] <= 1'b0 ;
else
begin
if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set
isr_bit2_0[1] <= 1'b1 ;
else if (delete_isr_bit1) // Synchronous reset
isr_bit2_0[1] <= 1'b0 ;
end
end
// PCI_EINT STATUS BIT
reg set_isr_bit2;
wire delete_set_isr_bit2;
wire block_set_isr_bit2;
// Synchronization module for clearing FF between two clock domains
pci_sync_module sync_isr_2
(
.set_clk_in (wb_clk),
.delete_clk_in (pci_clk),
.reset_in (reset),
.delete_set_out (delete_set_isr_bit2),
.block_set_out (block_set_isr_bit2),
.delete_in (delete_isr_bit2)
);
// Setting FF
always@(posedge wb_clk or posedge reset)
begin
if (reset) // Asynchronous reset
set_isr_bit2 <= 1'b0 ;
else
begin
if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set
set_isr_bit2 <= 1'b1 ;
else if (delete_set_isr_bit2) // Synchronous reset
set_isr_bit2 <= 1'b0 ;
end
end
wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ;
wire meta_isr_bit2 ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) isr_bit2_sync
(
.data_in (isr_bit2),
.clk_out (pci_clk),
.sync_data_out (meta_isr_bit2),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
isr_bit2_0[2] <= 1'b0 ;
else
isr_bit2_0[2] <= meta_isr_bit2 ;
end
`endif
`endif
// INT BIT of ISR - interrupt status register
`ifdef HOST
wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
wire meta_isr_int_prop_bit ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) isr_bit0_sync
(
.data_in (isr_int_prop_bit),
.clk_out (wb_clk),
.sync_data_out (meta_isr_int_prop_bit),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
isr_bit2_0[0] <= 1'b0 ;
else
isr_bit2_0[0] <= meta_isr_int_prop_bit ;
end
`else // GUEST
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
isr_bit2_0[0] <= 1'b0 ;
else
isr_bit2_0[0] <= isr_int_prop_bit ;
end
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ;
wire meta_isr_int_prop_bit ;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) isr_bit0_sync
(
.data_in (isr_int_prop_bit),
.clk_out (pci_clk),
.sync_data_out (meta_isr_int_prop_bit),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
isr_bit2_0[0] <= 1'b0 ;
else
isr_bit2_0[0] <= meta_isr_int_prop_bit ;
end
`endif
`endif
// INT PIN
wire int_in;
wire int_meta;
reg interrupt_out;
`ifdef HOST
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2] || isr_bit4_3[3] || isr_bit4_3[4];
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4];
`endif
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) int_pin_sync
(
.data_in (int_in),
.clk_out (wb_clk),
.sync_data_out (int_meta),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
interrupt_out <= 1'b0 ;
else
interrupt_out <= int_meta ;
end
`else // GUEST
`ifdef SYNCHRONEOUS_CLOCK_DOMAINS
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2];
`else // not SYNCHRONEOUS_CLOCK_DOMAINS
assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2;
`endif
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) int_pin_sync
(
.data_in (int_in),
.clk_out (pci_clk),
.sync_data_out (int_meta),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
interrupt_out <= 1'b0 ;
else
interrupt_out <= int_meta ;
end
`endif
`ifdef PCI_CPCI_HS_IMPLEMENT
reg [hs_es_cnt_width - 1:0] hs_es_cnt ; // debounce counter
reg hs_es_in_state, // current state of ejector switch input - synchronized
hs_es_sync, // synchronization flop for ejector switch input
hs_es_cur_state ; // current valid state of ejector switch
`ifdef ACTIVE_HIGH_OE
wire oe_active_val = 1'b1 ;
`endif
`ifdef ACTIVE_LOW_OE
wire oe_active_val = 1'b0 ;
`endif
always@(posedge pci_clk or posedge reset)
begin
if (reset)
begin
hs_ins <= 1'b0 ;
hs_ins_armed <= 1'b1 ;
hs_ext <= 1'b0 ;
hs_ext_armed <= 1'b0 ;
hs_es_in_state <= 1'b0 ;
hs_es_sync <= 1'b0 ;
hs_es_cur_state <= 1'b0 ;
hs_es_cnt <= 'h0 ;
`ifdef ACTIVE_LOW_OE
pci_cpci_hs_enum_oe_o <= 1'b1 ;
pci_cpci_hs_led_oe_o <= 1'b0 ;
`endif
`ifdef ACTIVE_HIGH_OE
pci_cpci_hs_enum_oe_o <= 1'b0 ;
pci_cpci_hs_led_oe_o <= 1'b1 ;
`endif
end
else
begin
// INS
if (hs_ins)
begin
if (w_conf_data[23] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) // clear
hs_ins <= 1'b0 ;
end
else if (hs_ins_armed) // set
hs_ins <= init_complete & (hs_es_cur_state == 1'b1) ;
// INS armed
if (~hs_ins & hs_ins_armed & init_complete & (hs_es_cur_state == 1'b1)) // clear
hs_ins_armed <= 1'b0 ;
else if (hs_ext) // set
hs_ins_armed <= w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56] ;
// EXT
if (hs_ext) // clear
begin
if (w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56])
hs_ext <= 1'b0 ;
end
else if (hs_ext_armed) // set
hs_ext <= (hs_es_cur_state == 1'b0) ;
// EXT armed
if (~hs_ext & hs_ext_armed & (hs_es_cur_state == 1'b0)) // clear
hs_ext_armed <= 1'b0 ;
else if (hs_ins) // set
hs_ext_armed <= w_conf_data[23] & !w_byte_en[2] & w_we & w_reg_select_dec[56] ;
// ejector switch debounce counter logic
hs_es_sync <= pci_cpci_hs_es_i ;
hs_es_in_state <= hs_es_sync ;
if (hs_es_in_state == hs_es_cur_state)
hs_es_cnt <= 'h0 ;
else
hs_es_cnt <= hs_es_cnt + 1'b1 ;
if (hs_es_cnt == {hs_es_cnt_width{1'b1}})
hs_es_cur_state <= hs_es_in_state ;
if ((hs_ins | hs_ext) & ~hs_eim)
pci_cpci_hs_enum_oe_o <= oe_active_val ;
else
pci_cpci_hs_enum_oe_o <= ~oe_active_val ;
if (~init_complete | hs_loo)
pci_cpci_hs_led_oe_o <= oe_active_val ;
else
pci_cpci_hs_led_oe_o <= ~oe_active_val ;
end
end
`endif
`ifdef PCI_SPOCI
wire spoci_write_done,
spoci_dat_rdy ,
spoci_no_ack ;
wire [ 7: 0] spoci_wdat ;
wire [ 7: 0] spoci_rdat ;
// power on configuration control and status register
always@(posedge pci_clk or posedge reset)
begin
if (reset)
begin
spoci_cs_nack <= 1'b0 ;
spoci_cs_write <= 1'b0 ;
spoci_cs_read <= 1'b0 ;
spoci_cs_adr <= 'h0 ;
spoci_cs_dat <= 'h0 ;
end
else
begin
if (spoci_cs_write)
begin
if (spoci_write_done | spoci_no_ack)
spoci_cs_write <= 1'b0 ;
end
else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3])
spoci_cs_write <= w_conf_data[25] ;
if (spoci_cs_read)
begin
if (spoci_dat_rdy | spoci_no_ack)
spoci_cs_read <= 1'b0 ;
end
else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] )
spoci_cs_read <= w_conf_data[24] ;
if (spoci_cs_nack)
begin
if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] & w_conf_data[31] )
spoci_cs_nack <= 1'b0 ;
end
else if (spoci_cs_write | spoci_cs_read | ~init_cfg_done)
begin
spoci_cs_nack <= spoci_no_ack ;
end
if ( w_we & (w_conf_address[9:2] == 8'hFF) )
begin
if (~w_byte_en[2])
spoci_cs_adr[10: 8] <= w_conf_data[18:16] ;
if (~w_byte_en[1])
spoci_cs_adr[ 7: 0] <= w_conf_data[15: 8] ;
end
if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[0] )
spoci_cs_dat <= w_conf_data[ 7: 0] ;
else if (spoci_cs_read & spoci_dat_rdy)
spoci_cs_dat <= spoci_rdat ;
end
end
reg [ 2 : 0] bytes_received ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
begin
init_we <= 1'b0 ;
init_cfg_done <= 1'b0 ;
bytes_received <= 1'b0 ;
spoci_dat <= 'h0 ;
spoci_reg_num <= 'h0 ;
end
else if (~init_cfg_done)
begin
if (spoci_dat_rdy)
begin
case (bytes_received)
'h0:spoci_reg_num <= spoci_rdat ;
'h1:spoci_dat[ 7: 0] <= spoci_rdat ;
'h2:spoci_dat[15: 8] <= spoci_rdat ;
'h3:spoci_dat[23:16] <= spoci_rdat ;
'h4:spoci_dat[31:24] <= spoci_rdat ;
default:
begin
spoci_dat <= 32'hxxxx_xxxx ;
spoci_reg_num <= 'hxx ;
end
endcase
end
if (init_we)
bytes_received <= 'h0 ;
else if (spoci_dat_rdy)
bytes_received <= bytes_received + 1'b1 ;
if (init_we)
init_we <= 1'b0 ;
else if (bytes_received == 'h5)
init_we <= 1'b1 ;
if (spoci_no_ack | ((bytes_received == 'h1) & (spoci_reg_num == 'hff)) )
init_cfg_done <= 1'b1 ;
end
end
assign spoci_wdat = spoci_cs_dat ;
pci_spoci_ctrl i_pci_spoci_ctrl
(
.reset_i (reset ),
.clk_i (pci_clk ),
.do_rnd_read_i (spoci_cs_read ),
.do_seq_read_i (rst_inactive & ~init_cfg_done ),
.do_write_i (spoci_cs_write ),
.write_done_o (spoci_write_done ),
.dat_rdy_o (spoci_dat_rdy ),
.no_ack_o (spoci_no_ack ),
.adr_i (spoci_cs_adr ),
.dat_i (spoci_wdat ),
.dat_o (spoci_rdat ),
.pci_spoci_sda_i (spoci_sda_i ),
.pci_spoci_sda_oe_o (spoci_sda_oe_o ),
.pci_spoci_scl_oe_o (spoci_scl_oe_o )
);
`endif
/*-----------------------------------------------------------------------------------------------------------
OUTPUTs from registers !!!
-----------------------------------------------------------------------------------------------------------*/
// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done
`ifdef HOST
wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ;
wire [3:0] meta_command_bits ;
reg [3:0] sync_command_bits ;
pci_synchronizer_flop #(4, 0) command_bits_sync
(
.data_in (command_bits),
.clk_out (pci_clk),
.sync_data_out (meta_command_bits),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
sync_command_bits <= 4'b0 ;
else
sync_command_bits <= meta_command_bits ;
end
wire sync_command_bit8 = sync_command_bits[3] ;
wire sync_command_bit6 = sync_command_bits[2] ;
wire sync_command_bit1 = sync_command_bits[1] ;
wire sync_command_bit0 = sync_command_bits[0] ;
wire sync_command_bit2 = command_bit2_0[2] ;
`else // GUEST
wire command_bit = command_bit2_0[2] ;
wire meta_command_bit ;
reg sync_command_bit ;
pci_synchronizer_flop #(1, 0) command_bit_sync
(
.data_in (command_bit),
.clk_out (pci_clk),
.sync_data_out (meta_command_bit),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
sync_command_bit <= 1'b0 ;
else
sync_command_bit <= meta_command_bit ;
end
wire sync_command_bit8 = command_bit8 ;
wire sync_command_bit6 = command_bit6 ;
wire sync_command_bit1 = command_bit2_0[1] ;
wire sync_command_bit0 = command_bit2_0[0] ;
wire sync_command_bit2 = sync_command_bit ;
`endif
// PCI header outputs from command register
assign serr_enable = sync_command_bit8 & pci_init_complete_out ; // to PCI clock
assign perr_response = sync_command_bit6 & pci_init_complete_out ; // to PCI clock
assign pci_master_enable = sync_command_bit2 & wb_init_complete_out ; // to WB clock
assign memory_space_enable = sync_command_bit1 & pci_init_complete_out ; // to PCI clock
assign io_space_enable = sync_command_bit0 & pci_init_complete_out ; // to PCI clock
// if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done
// We don't support cache line sizes smaller that 4 and it must have last two bits zero!!!
wire cache_lsize_not_zero = ((cache_line_size_reg[7] || cache_line_size_reg[6] || cache_line_size_reg[5] ||
cache_line_size_reg[4] || cache_line_size_reg[3] || cache_line_size_reg[2]) &&
(!cache_line_size_reg[1] && !cache_line_size_reg[0]) );
`ifdef HOST
wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ;
wire [7:2] meta_cache_lsize_to_pci_bits ;
reg [7:2] sync_cache_lsize_to_pci_bits ;
pci_synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync
(
.data_in (cache_lsize_to_pci_bits),
.clk_out (pci_clk),
.sync_data_out (meta_cache_lsize_to_pci_bits),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
sync_cache_lsize_to_pci_bits <= 6'b0 ;
else
sync_cache_lsize_to_pci_bits <= meta_cache_lsize_to_pci_bits ;
end
wire [7:2] sync_cache_line_size_to_pci_reg = sync_cache_lsize_to_pci_bits[7:2] ;
wire [7:2] sync_cache_line_size_to_wb_reg = cache_line_size_reg[7:2] ;
wire sync_cache_lsize_not_zero_to_wb = cache_lsize_not_zero ;
// Latency timer is sinchronized only to PCI clock when bridge implementation is HOST
wire [7:0] latency_timer_bits = latency_timer ;
wire [7:0] meta_latency_timer_bits ;
reg [7:0] sync_latency_timer_bits ;
pci_synchronizer_flop #(8, 0) latency_timer_bits_sync
(
.data_in (latency_timer_bits),
.clk_out (pci_clk),
.sync_data_out (meta_latency_timer_bits),
.async_reset (reset)
) ;
always@(posedge pci_clk or posedge reset)
begin
if (reset)
sync_latency_timer_bits <= 8'b0 ;
else
sync_latency_timer_bits <= meta_latency_timer_bits ;
end
wire [7:0] sync_latency_timer = sync_latency_timer_bits ;
`else // GUEST
wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ;
wire [8:2] meta_cache_lsize_to_wb_bits ;
reg [8:2] sync_cache_lsize_to_wb_bits ;
pci_synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync
(
.data_in (cache_lsize_to_wb_bits),
.clk_out (wb_clk),
.sync_data_out (meta_cache_lsize_to_wb_bits),
.async_reset (reset)
) ;
always@(posedge wb_clk or posedge reset)
begin
if (reset)
sync_cache_lsize_to_wb_bits <= 7'b0 ;
else
sync_cache_lsize_to_wb_bits <= meta_cache_lsize_to_wb_bits ;
end
wire [7:2] sync_cache_line_size_to_pci_reg = cache_line_size_reg[7:2] ;
wire [7:2] sync_cache_line_size_to_wb_reg = sync_cache_lsize_to_wb_bits[7:2] ;
wire sync_cache_lsize_not_zero_to_wb = sync_cache_lsize_to_wb_bits[8] ;
// Latency timer
wire [7:0] sync_latency_timer = latency_timer ;
`endif
// PCI header output from cache_line_size, latency timer and interrupt pin
assign cache_line_size_to_pci = {sync_cache_line_size_to_pci_reg, 2'h0} ; // [7 : 0] to PCI clock
assign cache_line_size_to_wb = {sync_cache_line_size_to_wb_reg, 2'h0} ; // [7 : 0] to WB clock
assign cache_lsize_not_zero_to_wb = sync_cache_lsize_not_zero_to_wb ;
assign latency_tim[7 : 0] = sync_latency_timer ; // to PCI clock
//assign int_pin[2 : 0] = r_interrupt_pin ;
assign int_out = interrupt_out ;
// PCI output from image registers
// base address, address mask, translation address and control registers are sinchronized in PCI_DECODER.V module
`ifdef HOST
`ifdef NO_CNF_IMAGE
assign pci_base_addr0 = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
`else
assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ;
`endif
`endif
`ifdef GUEST
assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ;
`endif
assign pci_base_addr1 = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_base_addr2 = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_base_addr3 = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_base_addr4 = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_base_addr5 = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_memory_io0 = pci_ba0_bit0 ;
assign pci_memory_io1 = pci_ba1_bit0 ;
assign pci_memory_io2 = pci_ba2_bit0 ;
assign pci_memory_io3 = pci_ba3_bit0 ;
assign pci_memory_io4 = pci_ba4_bit0 ;
assign pci_memory_io5 = pci_ba5_bit0 ;
assign pci_addr_mask0 = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_addr_mask1 = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_addr_mask2 = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_addr_mask3 = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_addr_mask4 = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_addr_mask5 = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr0 = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr1 = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr2 = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr3 = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr4 = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_tran_addr5 = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
assign pci_img_ctrl0[2 : 1] = pci_img_ctrl0_bit2_1 ;
assign pci_img_ctrl1[2 : 1] = pci_img_ctrl1_bit2_1 ;
assign pci_img_ctrl2[2 : 1] = pci_img_ctrl2_bit2_1 ;
assign pci_img_ctrl3[2 : 1] = pci_img_ctrl3_bit2_1 ;
assign pci_img_ctrl4[2 : 1] = pci_img_ctrl4_bit2_1 ;
assign pci_img_ctrl5[2 : 1] = pci_img_ctrl5_bit2_1 ;
// WISHBONE output from image registers
// base address, address mask, translation address and control registers are sinchronized in DECODER.V module
assign wb_base_addr0 = wb_ba0_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_base_addr1 = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_base_addr2 = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_base_addr3 = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_base_addr4 = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_base_addr5 = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_memory_io0 = wb_ba0_bit0 ;
assign wb_memory_io1 = wb_ba1_bit0 ;
assign wb_memory_io2 = wb_ba2_bit0 ;
assign wb_memory_io3 = wb_ba3_bit0 ;
assign wb_memory_io4 = wb_ba4_bit0 ;
assign wb_memory_io5 = wb_ba5_bit0 ;
assign wb_addr_mask0 = wb_am0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_addr_mask1 = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_addr_mask2 = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_addr_mask3 = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_addr_mask4 = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_addr_mask5 = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr0 = wb_ta0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr1 = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr2 = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr3 = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr4 = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_tran_addr5 = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ;
assign wb_img_ctrl0[2 : 0] = wb_img_ctrl0_bit2_0 ;
assign wb_img_ctrl1[2 : 0] = wb_img_ctrl1_bit2_0 ;
assign wb_img_ctrl2[2 : 0] = wb_img_ctrl2_bit2_0 ;
assign wb_img_ctrl3[2 : 0] = wb_img_ctrl3_bit2_0 ;
assign wb_img_ctrl4[2 : 0] = wb_img_ctrl4_bit2_0 ;
assign wb_img_ctrl5[2 : 0] = wb_img_ctrl5_bit2_0 ;
// GENERAL output from conf. cycle generation register & int. control register
assign config_addr[23 : 0] = { cnf_addr_bit23_2, 1'b0, cnf_addr_bit0 } ;
assign icr_soft_res = icr_bit31 ;
endmodule
</pre>
<hr />
<address><span style="font-size: smaller">FreeBSD-CVSweb <<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>></span></address>
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