VxWorks

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bcm1250Lib.h：源码内容

/* bcm1250Lib.h - BCM1250 systems-on-chip header file */
/*********************************************************************
*
*
* This software is furnished under license to Wind River Systems, Inc.
* and may be used only in accordance with the terms and conditions
* of this license. No title or ownership is transferred hereby.
********************************************************************* */
/*
* This file has been developed or significantly modified by the
* MIPS Center of Excellence Dedicated Engineering Staff.
* This notice is as per the MIPS Center of Excellence Master Partner
* Agreement, do not remove this notice without checking first with
* WR/Platforms MIPS Center of Excellence engineering management.
*/
/*
modification history
--------------------
01d,31may02,pgh Fix the address definitions for R_MAC_CHLO0_BASE and
R_MAC_CHUP0_BASE.
01c,10may02,tlc Add C++ header protection.
01b,17dec01,agf Replace __ASSEMBLER__ with _ASMLANGUAGE
01a,05dec01,agf created
*/
/*
DESCRIPTION
This file contains constants for the BCM 1250. Register address
definitions for the various subsystems are provided, and most (but
not all) register field definitions are provided.
Naming schemes for the BCM 1250 constants are:
M_xxx MASK constant (identifies bits in a register).
For multi-bit fields, all bits in the field will
be set.
K_xxx "Code" constant (value for data in a multi-bit
field). The value is right justified.
V_xxx "Value" constant. This is the same as the
corresponding "K_xxx" constant, except it is
shifted to the correct position in the register.
S_xxx SHIFT constant. This is the number of bits that
a field value (code) needs to be shifted
(towards the left) to put the value in the right
position for the register.
A_xxx ADDRESS constant. This will be a physical
address. Use the PHYS_TO_K1 macro to generate
a K1SEG address.
R_xxx RELATIVE offset constant. This is an offset from
an A_xxx constant (usually the first register in
a group).
G_xxx(X) GET value. This macro obtains a multi-bit field
from a register, masks it, and shifts it to
the bottom of the register (retrieving a K_xxx
value, for example).
V_xxx(X) VALUE. This macro computes the value of a
K_xxx constant shifted to the correct position
in the register.
*/
#ifndef __INCbcm1250Libh
#define __INCbcm1250Libh
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
/* macros */
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
*/
#if !defined(_ASMLANGUAGE)
#define _SB_MAKE64(x) ((UINT64)(x))
#define _SB_MAKE32(x) ((UINT32)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif
/*
* Make a mask for 1 bit at position 'n'
*/
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
/*
* Make a mask for 'v' bits at position 'n'
*/
#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
/*
* Make a value at 'v' at bit position 'n'
*/
#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
/*
* Macros to read/write on-chip registers
*/
#if !defined(_ASMLANGUAGE)
#define SBWRITECSR(csr,val) *((volatile UINT64 *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile UINT64 *) PHYS_TO_K1(csr)))
#endif /* _ASMLANGUAGE*/
/* defines */
/* *********************************************************************
* Some general notes:
*
* For the most part, when there is more than one peripheral
* of the same type on the SOC, the constants below will be
* offsets from the base of each peripheral. For example,
* the MAC registers are described as offsets from the first
* MAC register, and there will be a MAC_REGISTER() macro
* to calculate the base address of a given MAC.
*
* The information in this file is based on the BCM1250 SOC
* manual version 0.2, July 2000.
********************************************************************* */
/* *********************************************************************
* Memory Controller Registers
********************************************************************* */
#define A_MC_BASE_0 0x0010051000
#define A_MC_BASE_1 0x0010052000
#define MC_REGISTER_SPACING 0x1000
#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg))
#define R_MC_CONFIG 0x0000000100
#define R_MC_DRAMCMD 0x0000000120
#define R_MC_DRAMMODE 0x0000000140
#define R_MC_TIMING1 0x0000000160
#define R_MC_TIMING2 0x0000000180
#define R_MC_CS_START 0x00000001A0
#define R_MC_CS_END 0x00000001C0
#define R_MC_CS_INTERLEAVE 0x00000001E0
#define S_MC_CS_STARTEND 16
#define R_MC_CSX_BASE 0x0000000200
#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */
#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */
#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */
#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */
#define R_MC_CS0_ROW 0x0000000200
#define R_MC_CS0_COL 0x0000000220
#define R_MC_CS0_BA 0x0000000240
#define R_MC_CS1_ROW 0x0000000260
#define R_MC_CS1_COL 0x0000000280
#define R_MC_CS1_BA 0x00000002A0
#define R_MC_CS2_ROW 0x00000002C0
#define R_MC_CS2_COL 0x00000002E0
#define R_MC_CS2_BA 0x0000000300
#define R_MC_CS3_ROW 0x0000000320
#define R_MC_CS3_COL 0x0000000340
#define R_MC_CS3_BA 0x0000000360
#define R_MC_CS_ATTR 0x0000000380
#define R_MC_TEST_DATA 0x0000000400
#define R_MC_TEST_ECC 0x0000000420
#define R_MC_MCLK_CFG 0x0000000500
/* *********************************************************************
* L2 Cache Control Registers
********************************************************************* */
#define A_L2_READ_ADDRESS 0x0010040018
#define A_L2_EEC_ADDRESS 0x0010040038
#define A_L2_WAY_DISABLE 0x0010041000
#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE 0x00D0000000
/* *********************************************************************
* PCI Interface Registers
********************************************************************* */
#define A_PCI_TYPE00_HEADER 0x00DE000000
#define A_PCI_TYPE01_HEADER 0x00DE000800
/* *********************************************************************
* Ethernet DMA and MACs
********************************************************************* */
#define A_MAC_BASE_0 0x0010064000
#define A_MAC_BASE_1 0x0010065000
#define A_MAC_BASE_2 0x0010066000
#define MAC_SPACING 0x1000
#define MAC_DMA_TXRX_SPACING 0x0400
#define MAC_DMA_CHANNEL_SPACING 0x0100
#define DMA_RX 0
#define DMA_TX 1
#define MAC_NUM_DMACHAN 2 /* channels per direction */
#define MAC_NUM_PORTS 3
#define A_MAC_CHANNEL_BASE(macnum)
(A_MAC_BASE_0 +
MAC_SPACING*(macnum))
#define A_MAC_REGISTER(macnum,reg)
(A_MAC_BASE_0 +
MAC_SPACING*(macnum) + (reg))
#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan)
((A_MAC_CHANNEL_BASE(macnum)) +
R_MAC_DMA_CHANNELS +
(MAC_DMA_TXRX_SPACING*(txrx)) +
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define R_MAC_DMA_CHANNEL_BASE(txrx,chan)
(R_MAC_DMA_CHANNELS +
(MAC_DMA_TXRX_SPACING*(txrx)) +
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg)
(A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) +
(reg))
#define R_MAC_DMA_REGISTER(txrx,chan,reg)
(R_MAC_DMA_CHANNEL_BASE(txrx,chan) +
(reg))
/*
* DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
*/
#define R_MAC_DMA_CONFIG0 0x00000000
#define R_MAC_DMA_CONFIG1 0x00000008
#define R_MAC_DMA_DSCR_BASE 0x00000010
#define R_MAC_DMA_DSCR_CNT 0x00000018
#define R_MAC_DMA_CUR_DSCRA 0x00000020
#define R_MAC_DMA_CUR_DSCRB 0x00000028
#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
/*
* RMON Counters
*/
#define R_MAC_RMON_TX_BYTES 0x00000000
#define R_MAC_RMON_COLLISIONS 0x00000008
#define R_MAC_RMON_LATE_COL 0x00000010
#define R_MAC_RMON_EX_COL 0x00000018
#define R_MAC_RMON_FCS_ERROR 0x00000020
#define R_MAC_RMON_TX_ABORT 0x00000028
/* Counter #6 (0x30) now reserved */
#define R_MAC_RMON_TX_BAD 0x00000038
#define R_MAC_RMON_TX_GOOD 0x00000040
#define R_MAC_RMON_TX_RUNT 0x00000048
#define R_MAC_RMON_TX_OVERSIZE 0x00000050
#define R_MAC_RMON_RX_BYTES 0x00000080
#define R_MAC_RMON_RX_MCAST 0x00000088
#define R_MAC_RMON_RX_BCAST 0x00000090
#define R_MAC_RMON_RX_BAD 0x00000098
#define R_MAC_RMON_RX_GOOD 0x000000A0
#define R_MAC_RMON_RX_RUNT 0x000000A8
#define R_MAC_RMON_RX_OVERSIZE 0x000000B0
#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8
#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0
#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8
#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0
/* Updated to spec 0.2 */
#define R_MAC_CFG 0x00000100
#define R_MAC_THRSH_CFG 0x00000108
#define R_MAC_VLANTAG 0x00000110
#define R_MAC_FRAMECFG 0x00000118
#define R_MAC_EOPCNT 0x00000120
#define R_MAC_FIFO_PTRS 0x00000130
#define R_MAC_ADFILTER_CFG 0x00000200
#define R_MAC_ETHERNET_ADDR 0x00000208
#define R_MAC_PKT_TYPE 0x00000210
#define R_MAC_HASH_BASE 0x00000240
#define R_MAC_ADDR_BASE 0x00000280
#define R_MAC_CHUP0_BASE 0x00000300
#define R_MAC_CHLO0_BASE 0x00000320
#define R_MAC_ENABLE 0x00000400
#define R_MAC_STATUS 0x00000408
#define R_MAC_INT_MASK 0x00000410
#define R_MAC_TXD_CTL 0x00000420
#define R_MAC_MDIO 0x00000428
#define R_MAC_DEBUG_STATUS 0x00000448
#define MAC_HASH_COUNT 8
#define MAC_ADDR_COUNT 8
#define MAC_CHMAP_COUNT 4
/* *********************************************************************
* DUART Registers
********************************************************************* */
#define R_DUART_NUM_PORTS 2
#define A_DUART 0x0010060000
#define A_DUART_REG(r)
#define DUART_CHANREG_SPACING 0x100
#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg))
#define R_DUART_MODE_REG_1 0x100
#define R_DUART_MODE_REG_2 0x110
#define R_DUART_STATUS 0x120
#define R_DUART_CLK_SEL 0x130
#define R_DUART_CMD 0x150
#define R_DUART_RX_HOLD 0x160
#define R_DUART_TX_HOLD 0x170
/*
* The IMR and ISR can't be addressed with A_DUART_CHANREG,
* so use this macro instead.
*/
#define R_DUART_AUX_CTRL 0x310
#define R_DUART_ISR_A 0x320
#define R_DUART_IMR_A 0x330
#define R_DUART_ISR_B 0x340
#define R_DUART_IMR_B 0x350
#define R_DUART_OUT_PORT 0x360
#define R_DUART_OPCR 0x370
#define R_DUART_SET_OPR 0x3B0
#define R_DUART_CLEAR_OPR 0x3C0
#define DUART_IMRISR_SPACING 0x20
#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan))
#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan))
/*
* These constants are the absolute addresses.
*/
#define A_DUART_MODE_REG_1_A 0x0010060100
#define A_DUART_MODE_REG_2_A 0x0010060110
#define A_DUART_STATUS_A 0x0010060120
#define A_DUART_CLK_SEL_A 0x0010060130
#define A_DUART_CMD_A 0x0010060150
#define A_DUART_RX_HOLD_A 0x0010060160
#define A_DUART_TX_HOLD_A 0x0010060170
#define A_DUART_MODE_REG_1_B 0x0010060200
#define A_DUART_MODE_REG_2_B 0x0010060210
#define A_DUART_STATUS_B 0x0010060220
#define A_DUART_CLK_SEL_B 0x0010060230
#define A_DUART_CMD_B 0x0010060250
#define A_DUART_RX_HOLD_B 0x0010060260
#define A_DUART_TX_HOLD_B 0x0010060270
#define A_DUART_INPORT_CHNG 0x0010060300
#define A_DUART_AUX_CTRL 0x0010060310
#define A_DUART_ISR_A 0x0010060320
#define A_DUART_IMR_A 0x0010060330
#define A_DUART_ISR_B 0x0010060340
#define A_DUART_IMR_B 0x0010060350
#define A_DUART_OUT_PORT 0x0010060360
#define A_DUART_OPCR 0x0010060370
#define A_DUART_IN_PORT 0x0010060380
#define A_DUART_ISR 0x0010060390
#define A_DUART_IMR 0x00100603A0
#define A_DUART_SET_OPR 0x00100603B0
#define A_DUART_CLEAR_OPR 0x00100603C0
#define A_DUART_INPORT_CHNG_A 0x00100603D0
#define A_DUART_INPORT_CHNG_B 0x00100603E0
/* *********************************************************************
* Synchronous Serial Registers
********************************************************************* */
#define A_SER_BASE_0 0x0010060400
#define A_SER_BASE_1 0x0010060800
#define SER_SPACING 0x400
#define SER_DMA_TXRX_SPACING 0x80
#define SER_NUM_PORTS 2
#define A_SER_CHANNEL_BASE(sernum)
(A_SER_BASE_0 +
SER_SPACING*(sernum))
#define A_SER_REGISTER(sernum,reg)
(A_SER_BASE_0 +
SER_SPACING*(sernum) + (reg))
#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */
#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)
((A_SER_CHANNEL_BASE(sernum)) +
R_SER_DMA_CHANNELS +
(SER_DMA_TXRX_SPACING*(txrx)))
#define A_SER_DMA_REGISTER(sernum,txrx,reg)
(A_SER_DMA_CHANNEL_BASE(sernum,txrx) +
(reg))
/*
* DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
*/
#define R_SER_DMA_CONFIG0 0x00000000
#define R_SER_DMA_CONFIG1 0x00000008
#define R_SER_DMA_DSCR_BASE 0x00000010
#define R_SER_DMA_DSCR_CNT 0x00000018
#define R_SER_DMA_CUR_DSCRA 0x00000020
#define R_SER_DMA_CUR_DSCRB 0x00000028
#define R_SER_DMA_CUR_DSCRADDR 0x00000030
#define R_SER_DMA_CONFIG0_RX 0x00000000
#define R_SER_DMA_CONFIG1_RX 0x00000008
#define R_SER_DMA_DSCR_BASE_RX 0x00000010
#define R_SER_DMA_DSCR_COUNT_RX 0x00000018
#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020
#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028
#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030
#define R_SER_DMA_CONFIG0_TX 0x00000080
#define R_SER_DMA_CONFIG1_TX 0x00000088
#define R_SER_DMA_DSCR_BASE_TX 0x00000090
#define R_SER_DMA_DSCR_COUNT_TX 0x00000098
#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0
#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8
#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0
#define R_SER_MODE 0x00000100
#define R_SER_MINFRM_SZ 0x00000108
#define R_SER_MAXFRM_SZ 0x00000110
#define R_SER_ADDR 0x00000118
#define R_SER_USR0_ADDR 0x00000120
#define R_SER_USR1_ADDR 0x00000128
#define R_SER_USR2_ADDR 0x00000130
#define R_SER_USR3_ADDR 0x00000138
#define R_SER_CMD 0x00000140
#define R_SER_TX_RD_THRSH 0x00000160
#define R_SER_TX_WR_THRSH 0x00000168
#define R_SER_RX_RD_THRSH 0x00000170
#define R_SER_LINE_MODE 0x00000178
#define R_SER_DMA_ENABLE 0x00000180
#define R_SER_INT_MASK 0x00000190
#define R_SER_STATUS 0x00000188
#define R_SER_STATUS_DEBUG 0x000001A8
#define R_SER_RX_TABLE_BASE 0x00000200
#define SER_RX_TABLE_COUNT 16
#define R_SER_TX_TABLE_BASE 0x00000300
#define SER_TX_TABLE_COUNT 16
/* RMON Counters */
#define R_SER_RMON_TX_BYTE_LO 0x000001C0
#define R_SER_RMON_TX_BYTE_HI 0x000001C8
#define R_SER_RMON_RX_BYTE_LO 0x000001D0
#define R_SER_RMON_RX_BYTE_HI 0x000001D8
#define R_SER_RMON_TX_UNDERRUN 0x000001E0
#define R_SER_RMON_RX_OVERFLOW 0x000001E8
#define R_SER_RMON_RX_ERRORS 0x000001F0
#define R_SER_RMON_RX_BADADDR 0x000001F8
/* *********************************************************************
* Generic Bus Registers
********************************************************************* */
#define IO_EXT_CFG_COUNT 8
#define A_IO_EXT_BASE 0x0010061000
#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r))
#define A_IO_EXT_CFG_BASE 0x0010061000
#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100
#define A_IO_EXT_START_ADDR_BASE 0x0010061200
#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600
#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700
#define IO_EXT_REGISTER_SPACING 8
#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))
#define R_IO_EXT_CFG 0x0000
#define R_IO_EXT_MULT_SIZE 0x0100
#define R_IO_EXT_START_ADDR 0x0200
#define R_IO_EXT_TIME_CFG0 0x0600
#define R_IO_EXT_TIME_CFG1 0x0700
#define A_IO_INTERRUPT_STATUS 0x0010061A00
#define A_IO_INTERRUPT_DATA0 0x0010061A10
#define A_IO_INTERRUPT_DATA1 0x0010061A18
#define A_IO_INTERRUPT_DATA2 0x0010061A20
#define A_IO_INTERRUPT_DATA3 0x0010061A28
#define A_IO_INTERRUPT_ADDR0 0x0010061A30
#define A_IO_INTERRUPT_ADDR1 0x0010061A40
#define A_IO_INTERRUPT_PARITY 0x0010061A50
#define A_IO_PCMCIA_CFG 0x0010061A60
#define A_IO_PCMCIA_STATUS 0x0010061A70
#define A_IO_DRIVE_0 0x0010061300
#define A_IO_DRIVE_1 0x0010061308
#define A_IO_DRIVE_2 0x0010061310
#define A_IO_DRIVE_3 0x0010061318
#define R_IO_INTERRUPT_STATUS 0x0A00
#define R_IO_INTERRUPT_DATA0 0x0A10
#define R_IO_INTERRUPT_DATA1 0x0A18
#define R_IO_INTERRUPT_DATA2 0x0A20
#define R_IO_INTERRUPT_DATA3 0x0A28
#define R_IO_INTERRUPT_ADDR0 0x0A30
#define R_IO_INTERRUPT_ADDR1 0x0A40
#define R_IO_INTERRUPT_PARITY 0x0A50
#define R_IO_PCMCIA_CFG 0x0A60
#define R_IO_PCMCIA_STATUS 0x0A70
/* *********************************************************************
* GPIO Registers
********************************************************************* */
#define A_GPIO_CLR_EDGE 0x0010061A80
#define A_GPIO_INT_TYPE 0x0010061A88
#define A_GPIO_INPUT_INVERT 0x0010061A90
#define A_GPIO_GLITCH 0x0010061A98
#define A_GPIO_READ 0x0010061AA0
#define A_GPIO_DIRECTION 0x0010061AA8
#define A_GPIO_PIN_CLR 0x0010061AB0
#define A_GPIO_PIN_SET 0x0010061AB8
#define A_GPIO_BASE 0x0010061A80
#define R_GPIO_CLR_EDGE 0x00
#define R_GPIO_INT_TYPE 0x08
#define R_GPIO_INPUT_INVERT 0x10
#define R_GPIO_GLITCH 0x18
#define R_GPIO_READ 0x20
#define R_GPIO_DIRECTION 0x28
#define R_GPIO_PIN_CLR 0x30
#define R_GPIO_PIN_SET 0x38
/* *********************************************************************
* SMBus Registers
********************************************************************* */
#define A_SMB_XTRA_0 0x0010060000
#define A_SMB_XTRA_1 0x0010060008
#define A_SMB_FREQ_0 0x0010060010
#define A_SMB_FREQ_1 0x0010060018
#define A_SMB_STATUS_0 0x0010060020
#define A_SMB_STATUS_1 0x0010060028
#define A_SMB_CMD_0 0x0010060030
#define A_SMB_CMD_1 0x0010060038
#define A_SMB_START_0 0x0010060040
#define A_SMB_START_1 0x0010060048
#define A_SMB_DATA_0 0x0010060050
#define A_SMB_DATA_1 0x0010060058
#define A_SMB_CONTROL_0 0x0010060060
#define A_SMB_CONTROL_1 0x0010060068
#define A_SMB_PEC_0 0x0010060070
#define A_SMB_PEC_1 0x0010060078
#define A_SMB_0 0x0010060000
#define A_SMB_1 0x0010060008
#define SMB_REGISTER_SPACING 0x8
#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg))
#define R_SMB_XTRA 0x0000000000
#define R_SMB_FREQ 0x0000000010
#define R_SMB_STATUS 0x0000000020
#define R_SMB_CMD 0x0000000030
#define R_SMB_START 0x0000000040
#define R_SMB_DATA 0x0000000050
#define R_SMB_CONTROL 0x0000000060
#define R_SMB_PEC 0x0000000070
/* *********************************************************************
* Timer Registers
********************************************************************* */
/*
* Watchdog timers
*/
#define A_SCD_WDOG_0 0x0010020050
#define A_SCD_WDOG_1 0x0010020150
#define SCD_WDOG_SPACING 0x100
#define SCD_NUM_WDOGS 2
#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r))
#define R_SCD_WDOG_INIT 0x0000000000
#define R_SCD_WDOG_CNT 0x0000000008
#define R_SCD_WDOG_CFG 0x0000000010
#define A_SCD_WDOG_INIT_0 0x0010020050
#define A_SCD_WDOG_CNT_0 0x0010020058
#define A_SCD_WDOG_CFG_0 0x0010020060
#define A_SCD_WDOG_INIT_1 0x0010020150
#define A_SCD_WDOG_CNT_1 0x0010020158
#define A_SCD_WDOG_CFG_1 0x0010020160
/*
* Generic timers
*/
#define A_SCD_TIMER_0 0x0010020070
#define A_SCD_TIMER_1 0x0010020078
#define A_SCD_TIMER_2 0x0010020170
#define A_SCD_TIMER_3 0x0010020178
#define SCD_NUM_TIMERS 4
#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r))
#define R_SCD_TIMER_INIT 0x0000000000
#define R_SCD_TIMER_CNT 0x0000000010
#define R_SCD_TIMER_CFG 0x0000000020
#define A_SCD_TIMER_INIT_0 0x0010020070
#define A_SCD_TIMER_CNT_0 0x0010020080
#define A_SCD_TIMER_CFG_0 0x0010020090
#define A_SCD_TIMER_INIT_1 0x0010020078
#define A_SCD_TIMER_CNT_1 0x0010020088
#define A_SCD_TIMER_CFG_1 0x0010020098
#define A_SCD_TIMER_INIT_2 0x0010020170
#define A_SCD_TIMER_CNT_2 0x0010020180
#define A_SCD_TIMER_CFG_2 0x0010020190
#define A_SCD_TIMER_INIT_3 0x0010020178
#define A_SCD_TIMER_CNT_3 0x0010020188
#define A_SCD_TIMER_CFG_3 0x0010020198
/* *********************************************************************
* System Control Registers
********************************************************************* */
#define A_SCD_SYSTEM_REVISION 0x0010020000
#define A_SCD_SYSTEM_CFG 0x0010020008
#define A_SCD_SCRATCH 0x0010020C10 /* PASS2 */
/* *********************************************************************
* System Address Trap Registers
********************************************************************* */
#define A_ADDR_TRAP_INDEX 0x00100200B0
#define A_ADDR_TRAP_REG 0x00100200B8
#define A_ADDR_TRAP_UP_0 0x0010020400
#define A_ADDR_TRAP_UP_1 0x0010020408
#define A_ADDR_TRAP_UP_2 0x0010020410
#define A_ADDR_TRAP_UP_3 0x0010020418
#define A_ADDR_TRAP_DOWN_0 0x0010020420
#define A_ADDR_TRAP_DOWN_1 0x0010020428
#define A_ADDR_TRAP_DOWN_2 0x0010020430
#define A_ADDR_TRAP_DOWN_3 0x0010020438
#define A_ADDR_TRAP_CFG_0 0x0010020440
#define A_ADDR_TRAP_CFG_1 0x0010020448
#define A_ADDR_TRAP_CFG_2 0x0010020450
#define A_ADDR_TRAP_CFG_3 0x0010020458
/* *********************************************************************
* System Interrupt Mapper Registers
********************************************************************* */
#define A_IMR_CPU0_BASE 0x0010020000
#define A_IMR_CPU1_BASE 0x0010022000
#define IMR_REGISTER_SPACING 0x2000
#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
#define R_IMR_INTERRUPT_DIAG 0x0010
#define R_IMR_INTERRUPT_MASK 0x0028
#define R_IMR_INTERRUPT_TRACE 0x0038
#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
#define R_IMR_LDT_INTERRUPT_SET 0x0048
#define R_IMR_LDT_INTERRUPT 0x0018
#define R_IMR_LDT_INTERRUPT_CLR 0x0020
#define R_IMR_MAILBOX_CPU 0x00c0
#define R_IMR_ALIAS_MAILBOX_CPU 0x1000
#define R_IMR_MAILBOX_SET_CPU 0x00C8
#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008
#define R_IMR_MAILBOX_CLR_CPU 0x00D0
#define R_IMR_INTERRUPT_STATUS_BASE 0x0100
#define R_IMR_INTERRUPT_STATUS_COUNT 7
#define R_IMR_INTERRUPT_MAP_BASE 0x0200
#define R_IMR_INTERRUPT_MAP_COUNT 64
/* *********************************************************************
* System Performance Counter Registers
********************************************************************* */
#define A_SCD_PERF_CNT_CFG 0x00100204C0
#define A_SCD_PERF_CNT_0 0x00100204D0
#define A_SCD_PERF_CNT_1 0x00100204D8
#define A_SCD_PERF_CNT_2 0x00100204E0
#define A_SCD_PERF_CNT_3 0x00100204E8
/* *********************************************************************
* System Bus Watcher Registers
********************************************************************* */
#define A_SCD_BUS_ERR_STATUS 0x0010020880
#define A_BUS_ERR_DATA_0 0x00100208A0
#define A_BUS_ERR_DATA_1 0x00100208A8
#define A_BUS_ERR_DATA_2 0x00100208B0
#define A_BUS_ERR_DATA_3 0x00100208B8
#define A_BUS_L2_ERRORS 0x00100208C0
#define A_BUS_MEM_IO_ERRORS 0x00100208C8
/* *********************************************************************
* System Debug Controller Registers
********************************************************************* */
#define A_SCD_JTAG_BASE 0x0010000000
/* *********************************************************************
* System Trace Buffer Registers
********************************************************************* */
#define A_SCD_TRACE_CFG 0x0010020A00
#define A_SCD_TRACE_READ 0x0010020A08
#define A_SCD_TRACE_EVENT_0 0x0010020A20
#define A_SCD_TRACE_EVENT_1 0x0010020A28
#define A_SCD_TRACE_EVENT_2 0x0010020A30
#define A_SCD_TRACE_EVENT_3 0x0010020A38
#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40
#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48
#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50
#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58
#define A_SCD_TRACE_EVENT_4 0x0010020A60
#define A_SCD_TRACE_EVENT_5 0x0010020A68
#define A_SCD_TRACE_EVENT_6 0x0010020A70
#define A_SCD_TRACE_EVENT_7 0x0010020A78
#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80
#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88
#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
/* *********************************************************************
* System Generic DMA Registers
********************************************************************* */
#define A_DM_0 0x0010020B00
#define A_DM_1 0x0010020B20
#define A_DM_2 0x0010020B40
#define A_DM_3 0x0010020B60
#define DM_REGISTER_SPACING 0x20
#define DM_NUM_CHANNELS 4
#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))
#define R_DM_DSCR_BASE 0x0000000000
#define R_DM_DSCR_COUNT 0x0000000008
#define R_DM_CUR_DSCR_ADDR 0x0000000010
#define R_DM_DSCR_BASE_DEBUG 0x0000000018
/* *********************************************************************
* Physical Address Map
********************************************************************* */
#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000)
#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000)
#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000)
#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000)
#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000)
#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000)
#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
#define PHYS_L2CACHE_NUM_WAYS 4
#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000)
#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000)
#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)
/* *********************************************************************
*
* The remainder are field definitions within the SOC registers
*
* The information in this file is based on the BCM1250 SOC
* manual version 0.2, July 2000.
********************************************************************* */
/* *********************************************************************
* System control/debug register constants
********************************************************************* */
/*
* System Revision Register (Table 4-1)
*/
#define M_SYS_RESERVED _SB_MAKEMASK(8,0)
#define S_SYS_REVISION _SB_MAKE64(8)
#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)
#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
#define K_SYS_REVISION_PASS1 1
#define K_SYS_REVISION_PASS2 3
#define K_SYS_REVISION_PASS3 4 /* XXX Unknown */
#define S_SYS_PART _SB_MAKE64(16)
#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
#define K_SYS_PART_BCM1250 0x1250
#define K_SYS_PART_SB1125 0x1125
#define S_SYS_WID _SB_MAKE64(32)
#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
/*
* System Config Register (Table 4-2)
* Register: SCD_SYSTEM_CFG
*/
#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
#define S_SYS_PLL_DIV _SB_MAKE64(7)
#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)
#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
#define S_SYS_BOOT_MODE _SB_MAKE64(17)
#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
#define K_SYS_BOOT_MODE_ROM32 0
#define K_SYS_BOOT_MODE_ROM8 1
#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
#define K_SYS_BOOT_MODE_SMBUS_BIG 3
#define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
#define S_SYS_CONFIG 26
#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)
#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
/* The following bits are writeable by JTAG only. */
#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
#define S_SYS_CLKCOUNT 34
#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
#define S_SYS_PLL_IREF 43
#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)
#define S_SYS_PLL_VCO 45
#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)
#define S_SYS_PLL_VREG 47
#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)
#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
#define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
/* End of bits writable by JTAG only. */
#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
#define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
#define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
#define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
/*
* Mailbox Registers (Table 4-3)
* Registers: SCD_MBOX_CPU_x
*/
#define S_MBOX_INT_3 0
#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)
#define S_MBOX_INT_2 16
#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)
#define S_MBOX_INT_1 32
#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)
#define S_MBOX_INT_0 48
#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)
/*
* Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
* Registers: SCD_WDOG_INIT_CNT_x
*/
#define V_SCD_WDOG_FREQ 1000000
#define S_SCD_WDOG_INIT 0
#define M_SCD_WDOG_INIT _SB_MAKEMASK(13,S_SCD_WDOG_INIT)
#define S_SCD_WDOG_CNT 0
#define M_SCD_WDOG_CNT _SB_MAKEMASK(13,S_SCD_WDOG_CNT)
#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
/*
* Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
*/
#define V_SCD_TIMER_FREQ 1000000
#define S_SCD_TIMER_INIT 0
#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
#define S_SCD_TIMER_CNT 0
#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
/*
* System Performance Counters
*/
#define S_SPC_CFG_SRC0 0
#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
#define S_SPC_CFG_SRC1 8
#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
#define S_SPC_CFG_SRC2 16
#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
#define S_SPC_CFG_SRC3 24
#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
/*
* Bus Watcher
*/
#define S_SCD_BERR_TID 8
#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID)
#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID)
#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
#define S_SCD_BERR_RID 18
#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID)
#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
#define S_SCD_BERR_DCODE 22
#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
#define S_SCD_L2ECC_CORR_D 0
#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
#define S_SCD_L2ECC_BAD_D 8
#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
#define S_SCD_L2ECC_CORR_T 16
#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
#define S_SCD_L2ECC_BAD_T 24
#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
#define S_SCD_MEM_ECC_CORR 0
#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
#define S_SCD_MEM_ECC_BAD 16
#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
#define S_SCD_MEM_BUSERR 24
#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
/*
* Address Trap Registers
*/
#define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
#define S_ATRAP_CFG_CNT 0
#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
#define S_ATRAP_CFG_AGENTID 8
#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
#define K_BUS_AGENT_CPU0 0
#define K_BUS_AGENT_CPU1 1
#define K_BUS_AGENT_IOB0 2
#define K_BUS_AGENT_IOB1 3
#define K_BUS_AGENT_SCD 4
#define K_BUS_AGENT_RESERVED 5
#define K_BUS_AGENT_L2C 6
#define K_BUS_AGENT_MC 7
#define S_ATRAP_CFG_CATTR 12
#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
#define K_ATRAP_CFG_CATTR_IGNORE 0
#define K_ATRAP_CFG_CATTR_UNC 1
#define K_ATRAP_CFG_CATTR_CACHEABLE 2
#define K_ATRAP_CFG_CATTR_NONCOH 3
#define K_ATRAP_CFG_CATTR_COHERENT 4
#define K_ATRAP_CFG_CATTR_NOTUNC 5
#define K_ATRAP_CFG_CATTR_NOTNONCOH 6
#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
/*
* Trace Buffer Config register
*/
#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
#define S_SCD_TRACE_CFG_CUR_ADDR 10
#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
/*
* Trace Event registers
*/
#define S_SCD_TREVT_ADDR_MATCH 0
#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
#define S_SCD_TREVT_REQID 12
#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
#define S_SCD_TREVT_RESPID 16
#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
#define S_SCD_TREVT_DATAID 20
#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
#define S_SCD_TREVT_COUNT 24
#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
/*
* Trace Sequence registers
*/
#define S_SCD_TRSEQ_EVENT4 0
#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
#define S_SCD_TRSEQ_EVENT3 4
#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
#define S_SCD_TRSEQ_EVENT2 8
#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
#define S_SCD_TRSEQ_EVENT1 12
#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
#define K_SCD_TRSEQ_E0 0
#define K_SCD_TRSEQ_E1 1
#define K_SCD_TRSEQ_E2 2
#define K_SCD_TRSEQ_E3 3
#define K_SCD_TRSEQ_E0_E1 4
#define K_SCD_TRSEQ_E1_E2 5
#define K_SCD_TRSEQ_E2_E3 6
#define K_SCD_TRSEQ_E0_E1_E2 7
#define K_SCD_TRSEQ_E0_E1_E2_E3 8
#define K_SCD_TRSEQ_E0E1 9
#define K_SCD_TRSEQ_E0E1E2 10
#define K_SCD_TRSEQ_E0E1E2E3 11
#define K_SCD_TRSEQ_E0E1_E2 12
#define K_SCD_TRSEQ_E0E1_E2E3 13
#define K_SCD_TRSEQ_E0E1_E2_E3 14
#define K_SCD_TRSEQ_IGNORED 15
#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) |
V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) |
V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) |
V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
#define S_SCD_TRSEQ_FUNCTION 16
#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
#define K_SCD_TRSEQ_FUNC_NOP 0
#define K_SCD_TRSEQ_FUNC_START 1
#define K_SCD_TRSEQ_FUNC_STOP 2
#define K_SCD_TRSEQ_FUNC_FREEZE 3
#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
* First, the interrupt numbers.
*/
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2
#define K_INT_TIMER_1 3
#define K_INT_TIMER_2 4
#define K_INT_TIMER_3 5
#define K_INT_SMB_0 6
#define K_INT_SMB_1 7
#define K_INT_UART_0 8
#define K_INT_UART_1 9
#define K_INT_SER_0 10
#define K_INT_SER_1 11
#define K_INT_PCMCIA 12
#define K_INT_ADDR_TRAP 13
#define K_INT_PERF_CNT 14
#define K_INT_TRACE_FREEZE 15
#define K_INT_BAD_ECC 16
#define K_INT_COR_ECC 17
#define K_INT_IO_BUS 18
#define K_INT_MAC_0 19
#define K_INT_MAC_1 20
#define K_INT_MAC_2 21
#define K_INT_DM_CH_0 22
#define K_INT_DM_CH_1 23
#define K_INT_DM_CH_2 24
#define K_INT_DM_CH_3 25
#define K_INT_MBOX_0 26
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#define K_INT_SPARE_0 30
#define K_INT_SPARE_1 31
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
#define K_INT_GPIO_3 35
#define K_INT_GPIO_4 36
#define K_INT_GPIO_5 37
#define K_INT_GPIO_6 38
#define K_INT_GPIO_7 39
#define K_INT_GPIO_8 40
#define K_INT_GPIO_9 41
#define K_INT_GPIO_10 42
#define K_INT_GPIO_11 43
#define K_INT_GPIO_12 44
#define K_INT_GPIO_13 45
#define K_INT_GPIO_14 46
#define K_INT_GPIO_15 47
#define K_INT_LDT_FATAL 48
#define K_INT_LDT_NONFATAL 49
#define K_INT_LDT_SMI 50
#define K_INT_LDT_NMI 51
#define K_INT_LDT_INIT 52
#define K_INT_LDT_STARTUP 53
#define K_INT_LDT_EXT 54
#define K_INT_PCI_ERROR 55
#define K_INT_PCI_INTA 56
#define K_INT_PCI_INTB 57
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#define K_INT_SPARE_3 61
#define K_INT_SPARE_4 62
#define K_INT_SPARE_5 63
/*
* Mask values for each interrupt
*/
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_SPARE_0 _SB_MAKEMASK1(K_INT_SPARE_0)
#define M_INT_SPARE_1 _SB_MAKEMASK1(K_INT_SPARE_1)
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#define M_INT_SPARE_3 _SB_MAKEMASK1(K_INT_SPARE_3)
#define M_INT_SPARE_4 _SB_MAKEMASK1(K_INT_SPARE_4)
#define M_INT_SPARE_5 _SB_MAKEMASK1(K_INT_SPARE_5)
/*
* Interrupt mappings
*/
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6 /* nonmaskable */
#define K_INT_MAP_DINT 7 /* debug interrupt */
/*
* LDT Interrupt Set Register (table 4-5)
*/
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
#define K_INT_LDT_INTMSG_FIXED 0
#define K_INT_LDT_INTMSG_ARBITRATED 1
#define K_INT_LDT_INTMSG_SMI 2
#define K_INT_LDT_INTMSG_NMI 3
#define K_INT_LDT_INTMSG_INIT 4
#define K_INT_LDT_INTMSG_STARTUP 5
#define K_INT_LDT_INTMSG_EXTINT 6
#define K_INT_LDT_INTMSG_RESERVED 7
#define M_INT_LDT_EDGETRIGGER 0
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_PHYSICALDEST 0
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define S_INT_LDT_INTDEST 5
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
#define S_INT_LDT_VECTOR 13
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
/*
* Vector format (Table 4-6)
*/
#define M_LDTVECT_RAISEINT 0x00
#define M_LDTVECT_RAISEMBOX 0x40
/* *********************************************************************
* Level 2 Cache constants
********************************************************************* */
/*
* Level 2 Cache Tag register (Table 5-3)
*/
#define S_L2C_TAG_MBZ 0
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
#define S_L2C_TAG_INDEX 5
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
#define S_L2C_TAG_TAG 17
#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG)
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
#define S_L2C_TAG_ECC 40
#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC)
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
#define S_L2C_TAG_WAY 46
#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY)
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
/*
* Format of level 2 cache management address (table 5-2)
*/
#define S_L2C_MGMT_INDEX 5
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
#define S_L2C_MGMT_WAY 17
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
#define S_L2C_MGMT_TAG 21
#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
/* *********************************************************************
* Memory Channel constants
********************************************************************* */
/*
* Memory Channel Config Register (table 6-14)
*/
#define S_MC_RESERVED0 0
#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0)
#define S_MC_CHANNEL_SEL 8
#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL)
#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL)
#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL)
#define S_MC_BANK0_MAP 16
#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP)
#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP)
#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP)
#define K_MC_BANK0_MAP_DEFAULT 0x00
#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
#define S_MC_BANK1_MAP 20
#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP)
#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP)
#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP)
#define K_MC_BANK1_MAP_DEFAULT 0x08
#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
#define S_MC_BANK2_MAP 24
#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP)
#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP)
#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP)
#define K_MC_BANK2_MAP_DEFAULT 0x09
#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
#define S_MC_BANK3_MAP 28
#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP)
#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP)
#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP)
#define K_MC_BANK3_MAP_DEFAULT 0x0C
#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
#define M_MC_RESERVED1 _SB_MAKEMASK(8,32)
#define S_MC_QUEUE_SIZE 40
#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE)
#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE)
#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE)
#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
#define S_MC_AGE_LIMIT 44
#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT)
#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT)
#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT)
#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
#define S_MC_WR_LIMIT 48
#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT)
#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT)
#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT)
#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
#define M_MC_RESERVED2 _SB_MAKEMASK(3,53)
#define S_MC_CS_MODE 56
#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE)
#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE)
#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE)
#define K_MC_CS_MODE_MSB_CS 0
#define K_MC_CS_MODE_INTLV_CS 15
#define K_MC_CS_MODE_MIXED_CS_10 12
#define K_MC_CS_MODE_MIXED_CS_30 6
#define K_MC_CS_MODE_MIXED_CS_32 3
#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
#define M_MC_DEBUG _SB_MAKEMASK1(63)
#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT |
V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT |
V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) |
M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
/*
* Memory clock config register (Table 6-15)
*
* Note: this field has been updated to be consistent with the errata to 0.2
*/
#define S_MC_CLK_RATIO 0
#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO)
#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO)
#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO)
#define K_MC_CLK_RATIO_2X 4
#define K_MC_CLK_RATIO_25X 5
#define K_MC_CLK_RATIO_3X 6
#define K_MC_CLK_RATIO_35X 7
#define K_MC_CLK_RATIO_4X 8
#define K_MC_CLK_RATIO_45X 9
#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
#define S_MC_REF_RATE 8
#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE)
#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE)
#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE)
#define K_MC_REF_RATE_100MHz 0x62
#define K_MC_REF_RATE_133MHz 0x81
#define K_MC_REF_RATE_200MHz 0xC4
#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
#define S_MC_CLOCK_DRIVE 16
#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE)
#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE)
#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE)
#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
#define S_MC_DATA_DRIVE 20
#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE)
#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE)
#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE)
#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
#define S_MC_ADDR_DRIVE 24
#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE)
#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
#define S_MC_DQI_SKEW 32
#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW)
#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW)
#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW)
#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
#define S_MC_DQO_SKEW 40
#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW)
#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW)
#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW)
#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
#define S_MC_ADDR_SKEW 48
#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW)
#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW)
#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW)
#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
#define S_MC_DLL_DEFAULT 56
#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT)
#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT)
#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT)
#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT |
V_MC_ADDR_SKEW_DEFAULT |
V_MC_DQO_SKEW_DEFAULT |
V_MC_DQI_SKEW_DEFAULT |
V_MC_ADDR_DRIVE_DEFAULT |
V_MC_DATA_DRIVE_DEFAULT |
V_MC_CLOCK_DRIVE_DEFAULT |
V_MC_REF_RATE_DEFAULT
/*
* DRAM Command Register (Table 6-13)
*/
#define S_MC_COMMAND 0
#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND)
#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND)
#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND)
#define K_MC_COMMAND_EMRS 0
#define K_MC_COMMAND_MRS 1
#define K_MC_COMMAND_PRE 2
#define K_MC_COMMAND_AR 3
#define K_MC_COMMAND_SETRFSH 4
#define K_MC_COMMAND_CLRRFSH 5
#define K_MC_COMMAND_SETPWRDN 6
#define K_MC_COMMAND_CLRPWRDN 7
#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
#define M_MC_CS0 _SB_MAKEMASK1(4)
#define M_MC_CS1 _SB_MAKEMASK1(5)
#define M_MC_CS2 _SB_MAKEMASK1(6)
#define M_MC_CS3 _SB_MAKEMASK1(7)
/*
* DRAM Mode Register (Table 6-14)
*/