扫描程序

开发平台：

VHDL

examp1.tan.rpt：源码内容

; Not operational: Clock Skew > Data Delay ; 74160:inst14|7 ; 74160:inst14|8 ; SIGNAL ; SIGNAL ; None ; None ; 4.700 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|6 ; 74160:inst7|6 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|8 ; 74160:inst7|9 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|8 ; 74160:inst7|8 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|7 ; 74160:inst7|7 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst8|6 ; 74160:inst8|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst8|9 ; 74160:inst8|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst8|7 ; 74160:inst8|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst12|6 ; 74160:inst12|8 ; SIGNAL ; SIGNAL ; None ; None ; 4.200 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst12|6 ; 74160:inst12|7 ; SIGNAL ; SIGNAL ; None ; None ; 4.200 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst13|7 ; 74160:inst13|8 ; SIGNAL ; SIGNAL ; None ; None ; 4.700 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst13|9 ; 74160:inst13|7 ; SIGNAL ; SIGNAL ; None ; None ; 4.700 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst15|6 ; 74160:inst15|8 ; SIGNAL ; SIGNAL ; None ; None ; 5.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst15|6 ; 74160:inst15|7 ; SIGNAL ; SIGNAL ; None ; None ; 5.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst6|6 ; 74160:inst6|6 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst6|8 ; 74160:inst6|9 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst6|8 ; 74160:inst6|8 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst6|7 ; 74160:inst6|7 ; SIGNAL ; SIGNAL ; None ; None ; 1.800 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|6 ; 74160:inst7|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|9 ; 74160:inst7|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst7|7 ; 74160:inst7|9 ; SIGNAL ; SIGNAL ; None ; None ; 2.300 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst10|6 ; 74160:inst10|8 ; SIGNAL ; SIGNAL ; None ; None ; 4.200 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst10|6 ; 74160:inst10|7 ; SIGNAL ; SIGNAL ; None ; None ; 4.200 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst12|7 ; 74160:inst12|8 ; SIGNAL ; SIGNAL ; None ; None ; 4.700 ns ;
; Not operational: Clock Skew > Data Delay ; 74160:inst12|9 ; 74160:inst12|7 ; SIGNAL ; SIGNAL ; None ; None ; 4.700 ns ;
+------------------------------------------+----------------+----------------+------------+----------+----------------------------+----------------------------+--------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------+----------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------+----------+------------+
; N/A ; None ; 100.800 ns ; 74160:inst15|9 ; co12 ; SIGNAL ;
; N/A ; None ; 100.300 ns ; 74160:inst15|9 ; co12 ; CLK ;
; N/A ; None ; 98.700 ns ; 74160:inst15|6 ; co12 ; SIGNAL ;
; N/A ; None ; 98.200 ns ; 74160:inst15|6 ; co12 ; CLK ;
; N/A ; None ; 96.400 ns ; 74160:inst15|9 ; QC[3] ; SIGNAL ;
; N/A ; None ; 95.900 ns ; 74160:inst15|9 ; QC[3] ; CLK ;
; N/A ; None ; 95.600 ns ; 74160:inst15|6 ; QC[0] ; SIGNAL ;
; N/A ; None ; 95.600 ns ; 74160:inst15|7 ; QC[1] ; SIGNAL ;
; N/A ; None ; 95.600 ns ; 74160:inst15|8 ; QC[2] ; SIGNAL ;
; N/A ; None ; 95.100 ns ; 74160:inst15|6 ; QC[0] ; CLK ;
; N/A ; None ; 95.100 ns ; 74160:inst15|7 ; QC[1] ; CLK ;
; N/A ; None ; 95.100 ns ; 74160:inst15|8 ; QC[2] ; CLK ;
; N/A ; None ; 91.300 ns ; 74160:inst14|9 ; co11 ; SIGNAL ;
; N/A ; None ; 90.800 ns ; 74160:inst14|6 ; co11 ; SIGNAL ;
; N/A ; None ; 90.800 ns ; 74160:inst14|9 ; co11 ; CLK ;
; N/A ; None ; 90.300 ns ; 74160:inst14|6 ; co11 ; CLK ;
; N/A ; None ; 88.200 ns ; 74160:inst14|8 ; QB[2] ; SIGNAL ;
; N/A ; None ; 87.700 ns ; 74160:inst14|8 ; QB[2] ; CLK ;
; N/A ; None ; 87.400 ns ; 74160:inst14|9 ; QB[3] ; SIGNAL ;
; N/A ; None ; 87.300 ns ; 74160:inst14|6 ; QB[0] ; SIGNAL ;
; N/A ; None ; 86.900 ns ; 74160:inst14|9 ; QB[3] ; CLK ;
; N/A ; None ; 86.800 ns ; 74160:inst14|6 ; QB[0] ; CLK ;
; N/A ; None ; 86.700 ns ; 74160:inst14|7 ; QB[1] ; SIGNAL ;
; N/A ; None ; 86.200 ns ; 74160:inst14|7 ; QB[1] ; CLK ;
; N/A ; None ; 83.900 ns ; 74160:inst13|9 ; co10 ; SIGNAL ;
; N/A ; None ; 83.400 ns ; 74160:inst13|6 ; co10 ; SIGNAL ;
; N/A ; None ; 83.400 ns ; 74160:inst13|9 ; co10 ; CLK ;
; N/A ; None ; 82.900 ns ; 74160:inst13|6 ; co10 ; CLK ;
; N/A ; None ; 81.700 ns ; 74160:inst13|7 ; QA[1] ; SIGNAL ;
; N/A ; None ; 81.700 ns ; 74160:inst13|9 ; QA[3] ; SIGNAL ;
; N/A ; None ; 81.200 ns ; 74160:inst13|7 ; QA[1] ; CLK ;
; N/A ; None ; 81.200 ns ; 74160:inst13|9 ; QA[3] ; CLK ;
; N/A ; None ; 80.900 ns ; 74160:inst13|8 ; QA[2] ; SIGNAL ;
; N/A ; None ; 80.400 ns ; 74160:inst13|8 ; QA[2] ; CLK ;
; N/A ; None ; 80.300 ns ; 74160:inst13|6 ; QA[0] ; SIGNAL ;
; N/A ; None ; 79.800 ns ; 74160:inst13|6 ; QA[0] ; CLK ;
; N/A ; None ; 78.100 ns ; 74160:inst12|9 ; co9 ; SIGNAL ;
; N/A ; None ; 77.600 ns ; 74160:inst12|6 ; co9 ; SIGNAL ;
; N/A ; None ; 77.600 ns ; 74160:inst12|9 ; co9 ; CLK ;
; N/A ; None ; 77.100 ns ; 74160:inst12|6 ; co9 ; CLK ;
; N/A ; None ; 75.200 ns ; 74160:inst12|7 ; Q9[1] ; SIGNAL ;
; N/A ; None ; 75.100 ns ; 74160:inst12|6 ; Q9[0] ; SIGNAL ;
; N/A ; None ; 74.700 ns ; 74160:inst12|7 ; Q9[1] ; CLK ;
; N/A ; None ; 74.600 ns ; 74160:inst12|6 ; Q9[0] ; CLK ;
; N/A ; None ; 74.300 ns ; 74160:inst12|8 ; Q9[2] ; SIGNAL ;
; N/A ; None ; 74.200 ns ; 74160:inst12|9 ; Q9[3] ; SIGNAL ;
; N/A ; None ; 73.800 ns ; 74160:inst12|8 ; Q9[2] ; CLK ;
; N/A ; None ; 73.700 ns ; 74160:inst12|9 ; Q9[3] ; CLK ;
; N/A ; None ; 69.400 ns ; 74160:inst10|9 ; co8 ; SIGNAL ;
; N/A ; None ; 68.900 ns ; 74160:inst10|6 ; co8 ; SIGNAL ;
; N/A ; None ; 68.900 ns ; 74160:inst10|9 ; co8 ; CLK ;
; N/A ; None ; 68.400 ns ; 74160:inst10|6 ; co8 ; CLK ;
; N/A ; None ; 66.500 ns ; 74160:inst10|6 ; Q8[0] ; SIGNAL ;
; N/A ; None ; 66.500 ns ; 74160:inst10|7 ; Q8[1] ; SIGNAL ;
; N/A ; None ; 66.500 ns ; 74160:inst10|8 ; Q8[2] ; SIGNAL ;
; N/A ; None ; 66.500 ns ; 74160:inst10|9 ; Q8[3] ; SIGNAL ;
; N/A ; None ; 66.000 ns ; 74160:inst10|6 ; Q8[0] ; CLK ;
; N/A ; None ; 66.000 ns ; 74160:inst10|7 ; Q8[1] ; CLK ;
; N/A ; None ; 66.000 ns ; 74160:inst10|8 ; Q8[2] ; CLK ;
; N/A ; None ; 66.000 ns ; 74160:inst10|9 ; Q8[3] ; CLK ;
; N/A ; None ; 64.400 ns ; 74160:inst9|9 ; co7 ; SIGNAL ;
; N/A ; None ; 63.900 ns ; 74160:inst9|6 ; co7 ; SIGNAL ;
; N/A ; None ; 63.900 ns ; 74160:inst9|9 ; co7 ; CLK ;
; N/A ; None ; 63.400 ns ; 74160:inst9|6 ; co7 ; CLK ;
; N/A ; None ; 61.500 ns ; 74160:inst9|7 ; Q7[1] ; SIGNAL ;
; N/A ; None ; 61.500 ns ; 74160:inst9|9 ; Q7[3] ; SIGNAL ;
; N/A ; None ; 61.200 ns ; 74160:inst9|8 ; Q7[2] ; SIGNAL ;
; N/A ; None ; 61.000 ns ; 74160:inst9|7 ; Q7[1] ; CLK ;
; N/A ; None ; 61.000 ns ; 74160:inst9|9 ; Q7[3] ; CLK ;
; N/A ; None ; 60.700 ns ; 74160:inst9|8 ; Q7[2] ; CLK ;
; N/A ; None ; 59.800 ns ; 74160:inst9|6 ; Q7[0] ; SIGNAL ;
; N/A ; None ; 59.300 ns ; 74160:inst9|6 ; Q7[0] ; CLK ;
; N/A ; None ; 57.600 ns ; 74160:inst8|9 ; co6 ; SIGNAL ;
; N/A ; None ; 57.100 ns ; 74160:inst8|9 ; co6 ; CLK ;
; N/A ; None ; 56.800 ns ; 74160:inst8|6 ; co6 ; SIGNAL ;
; N/A ; None ; 56.300 ns ; 74160:inst8|6 ; co6 ; CLK ;
; N/A ; None ; 52.900 ns ; 74160:inst8|9 ; Q6[3] ; SIGNAL ;
; N/A ; None ; 52.400 ns ; 74160:inst8|9 ; Q6[3] ; CLK ;
; N/A ; None ; 51.700 ns ; 74160:inst8|8 ; Q6[2] ; SIGNAL ;
; N/A ; None ; 51.200 ns ; 74160:inst8|8 ; Q6[2] ; CLK ;
; N/A ; None ; 51.100 ns ; 74160:inst8|6 ; Q6[0] ; SIGNAL ;
; N/A ; None ; 51.100 ns ; 74160:inst8|7 ; Q6[1] ; SIGNAL ;
; N/A ; None ; 50.600 ns ; 74160:inst8|6 ; Q6[0] ; CLK ;
; N/A ; None ; 50.600 ns ; 74160:inst8|7 ; Q6[1] ; CLK ;
; N/A ; None ; 47.800 ns ; 74160:inst7|9 ; co5 ; SIGNAL ;
; N/A ; None ; 47.300 ns ; 74160:inst7|6 ; co5 ; SIGNAL ;
; N/A ; None ; 47.300 ns ; 74160:inst7|9 ; co5 ; CLK ;
; N/A ; None ; 46.800 ns ; 74160:inst7|6 ; co5 ; CLK ;
; N/A ; None ; 44.900 ns ; 74160:inst7|6 ; Q5[0] ; SIGNAL ;
; N/A ; None ; 44.400 ns ; 74160:inst7|6 ; Q5[0] ; CLK ;
; N/A ; None ; 44.300 ns ; 74160:inst7|7 ; Q5[1] ; SIGNAL ;
; N/A ; None ; 44.300 ns ; 74160:inst7|8 ; Q5[2] ; SIGNAL ;
; N/A ; None ; 44.300 ns ; 74160:inst7|9 ; Q5[3] ; SIGNAL ;
; N/A ; None ; 43.800 ns ; 74160:inst7|7 ; Q5[1] ; CLK ;
; N/A ; None ; 43.800 ns ; 74160:inst7|8 ; Q5[2] ; CLK ;
; N/A ; None ; 43.800 ns ; 74160:inst7|9 ; Q5[3] ; CLK ;
; N/A ; None ; 39.600 ns ; 74160:inst6|9 ; co4 ; SIGNAL ;
; N/A ; None ; 39.100 ns ; 74160:inst6|6 ; co4 ; SIGNAL ;
; N/A ; None ; 39.100 ns ; 74160:inst6|9 ; co4 ; CLK ;
; N/A ; None ; 38.600 ns ; 74160:inst6|6 ; co4 ; CLK ;
; N/A ; None ; 37.200 ns ; 74160:inst6|7 ; Q4[1] ; SIGNAL ;
; N/A ; None ; 36.700 ns ; 74160:inst6|7 ; Q4[1] ; CLK ;
; N/A ; None ; 36.700 ns ; 74160:inst6|9 ; Q4[3] ; SIGNAL ;
; N/A ; None ; 36.500 ns ; 74160:inst6|6 ; Q4[0] ; SIGNAL ;
; N/A ; None ; 36.500 ns ; 74160:inst6|8 ; Q4[2] ; SIGNAL ;
; N/A ; None ; 36.200 ns ; 74160:inst6|9 ; Q4[3] ; CLK ;
; N/A ; None ; 36.000 ns ; 74160:inst6|6 ; Q4[0] ; CLK ;
; N/A ; None ; 36.000 ns ; 74160:inst6|8 ; Q4[2] ; CLK ;
; N/A ; None ; 34.000 ns ; 74160:inst3|9 ; co3 ; SIGNAL ;
; N/A ; None ; 33.500 ns ; 74160:inst3|6 ; co3 ; SIGNAL ;
; N/A ; None ; 33.500 ns ; 74160:inst3|9 ; co3 ; CLK ;
; N/A ; None ; 33.000 ns ; 74160:inst3|6 ; co3 ; CLK ;
; N/A ; None ; 32.000 ns ; 74160:inst3|8 ; Q3[2] ; SIGNAL ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[0] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[1] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[2] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[3] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[4] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[5] ; CLK ;
; N/A ; None ; 31.900 ns ; xh:inst16|STATE[1] ; DOUT1[6] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[0] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[1] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[2] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[3] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[4] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[5] ; CLK ;
; N/A ; None ; 31.500 ns ; 74273:8|18 ; DOUT1[6] ; CLK ;
; N/A ; None ; 31.500 ns ; 74160:inst3|8 ; Q3[2] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[0] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[1] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[2] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[3] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[4] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[5] ; CLK ;
; N/A ; None ; 31.300 ns ; xh:inst16|STATE[0] ; DOUT1[6] ; CLK ;
; N/A ; None ; 31.100 ns ; 74160:inst3|6 ; Q3[0] ; SIGNAL ;
; N/A ; None ; 31.100 ns ; 74160:inst3|7 ; Q3[1] ; SIGNAL ;
; N/A ; None ; 31.100 ns ; 74160:inst3|9 ; Q3[3] ; SIGNAL ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[0] ; CLK ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[2] ; CLK ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[3] ; CLK ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[4] ; CLK ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[5] ; CLK ;
; N/A ; None ; 30.900 ns ; xh:inst16|STATE[1] ; DOUT2[6] ; CLK ;
; N/A ; None ; 30.800 ns ; xh:inst16|STATE[1] ; DOUT2[1] ; CLK ;
; N/A ; None ; 30.700 ns ; xh:inst16|STATE[0] ; DOUT3[0] ; CLK ;
; N/A ; None ; 30.600 ns ; xh:inst16|STATE[0] ; DOUT3[2] ; CLK ;
; N/A ; None ; 30.600 ns ; xh:inst16|STATE[0] ; DOUT3[3] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[0] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[1] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[2] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[3] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[4] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[5] ; CLK ;
; N/A ; None ; 30.600 ns ; 74273:6|18 ; DOUT1[6] ; CLK ;
; N/A ; None ; 30.600 ns ; 74160:inst3|6 ; Q3[0] ; CLK ;
; N/A ; None ; 30.600 ns ; 74160:inst3|7 ; Q3[1] ; CLK ;
; N/A ; None ; 30.600 ns ; 74160:inst3|9 ; Q3[3] ; CLK ;
; N/A ; None ; 30.300 ns ; xh:inst16|STATE[0] ; DOUT3[1] ; CLK ;
; N/A ; None ; 30.300 ns ; xh:inst16|STATE[0] ; DOUT3[4] ; CLK ;
; N/A ; None ; 30.300 ns ; xh:inst16|STATE[0] ; DOUT3[5] ; CLK ;
; N/A ; None ; 30.300 ns ; xh:inst16|STATE[0] ; DOUT3[6] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[0] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[2] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[3] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[4] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[5] ; CLK ;
; N/A ; None ; 30.200 ns ; xh:inst16|STATE[0] ; DOUT2[6] ; CLK ;
; N/A ; None ; 30.100 ns ; xh:inst16|STATE[0] ; DOUT2[1] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[0] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[2] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[3] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[4] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[5] ; CLK ;
; N/A ; None ; 29.500 ns ; 74273:11|17 ; DOUT2[6] ; CLK ;
; N/A ; None ; 29.400 ns ; 74273:11|17 ; DOUT2[1] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:16|16 ; DOUT3[0] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[0] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[2] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[3] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[4] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[5] ; CLK ;
; N/A ; None ; 29.100 ns ; 74273:11|18 ; DOUT2[6] ; CLK ;
; N/A ; None ; 29.000 ns ; 74273:16|16 ; DOUT3[2] ; CLK ;
; N/A ; None ; 29.000 ns ; 74273:16|16 ; DOUT3[3] ; CLK ;
; N/A ; None ; 29.000 ns ; 74273:11|18 ; DOUT2[1] ; CLK ;
; N/A ; None ; 28.800 ns ; 74273:18|18 ; DOUT3[0] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:16|16 ; DOUT3[1] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:18|18 ; DOUT3[2] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:18|18 ; DOUT3[3] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:16|16 ; DOUT3[4] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:16|16 ; DOUT3[5] ; CLK ;
; N/A ; None ; 28.700 ns ; 74273:16|16 ; DOUT3[6] ; CLK ;
; N/A ; None ; 28.600 ns ; xh:inst16|STATE[1] ; DOUT3[0] ; CLK ;
; N/A ; None ; 28.500 ns ; xh:inst16|STATE[1] ; DOUT3[2] ; CLK ;
; N/A ; None ; 28.500 ns ; xh:inst16|STATE[1] ; DOUT3[3] ; CLK ;
; N/A ; None ; 28.400 ns ; 74273:18|18 ; DOUT3[1] ; CLK ;
; N/A ; None ; 28.400 ns ; 74273:18|18 ; DOUT3[4] ; CLK ;
; N/A ; None ; 28.400 ns ; 74273:18|18 ; DOUT3[5] ; CLK ;
; N/A ; None ; 28.400 ns ; 74273:18|18 ; DOUT3[6] ; CLK ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+------------+--------------------+----------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri Jan 22 09:53:26 2010
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off examp1 -c examp1
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "CLK" is an undefined clock
Info: Assuming node "SIGNAL" is an undefined clock
Warning: Found 34 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "74160:inst14|49~22" as buffer
Info: Detected ripple clock "74160:inst14|9" as buffer
Info: Detected ripple clock "74160:inst14|6" as buffer
Info: Detected gated clock "74160:inst13|49~22" as buffer
Info: Detected ripple clock "74160:inst13|9" as buffer
Info: Detected ripple clock "74160:inst13|6" as buffer
Info: Detected gated clock "74160:inst12|49~22" as buffer
Info: Detected ripple clock "74160:inst12|9" as buffer
Info: Detected ripple clock "74160:inst12|6" as buffer
Info: Detected gated clock "74160:inst10|49~22" as buffer
Info: Detected ripple clock "74160:inst10|9" as buffer
Info: Detected ripple clock "74160:inst10|6" as buffer
Info: Detected gated clock "74160:inst9|49~22" as buffer
Info: Detected ripple clock "74160:inst9|9" as buffer
Info: Detected ripple clock "74160:inst9|6" as buffer
Info: Detected gated clock "74160:inst8|49~22" as buffer
Info: Detected ripple clock "74160:inst8|9" as buffer
Info: Detected ripple clock "74160:inst8|6" as buffer
Info: Detected gated clock "74160:inst7|49~22" as buffer
Info: Detected ripple clock "74160:inst7|9" as buffer
Info: Detected ripple clock "74160:inst7|6" as buffer
Info: Detected gated clock "74160:inst6|49~22" as buffer
Info: Detected ripple clock "74160:inst6|9" as buffer
Info: Detected ripple clock "74160:inst6|6" as buffer
Info: Detected gated clock "74160:inst3|49~22" as buffer
Info: Detected ripple clock "74160:inst3|9" as buffer
Info: Detected ripple clock "74160:inst3|6" as buffer
Info: Detected gated clock "74160:inst2|49~22" as buffer
Info: Detected ripple clock "74160:inst2|9" as buffer
Info: Detected ripple clock "74160:inst2|6" as buffer
Info: Detected gated clock "74160:inst|49~22" as buffer
Info: Detected ripple clock "74160:inst|9" as buffer
Info: Detected gated clock "inst4" as buffer
Info: Detected ripple clock "74160:inst|6" as buffer
Info: Clock "CLK" has Internal fmax of 11.35 MHz between source register "74160:inst15|9" and destination register "74273:19|16" (period= 88.1 ns)
Info: + Longest register to register delay is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C13; Fanout = 5; REG Node = '74160:inst15|9'
Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC8_C13; Fanout = 2; REG Node = '74273:19|16'
Info: Total cell delay = 1.200 ns ( 66.67 % )
Info: Total interconnect delay = 0.600 ns ( 33.33 % )
Info: - Smallest clock skew is -82.700 ns
Info: + Shortest clock path from clock "CLK" to destination register is 5.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 52; CLK Node = 'CLK'
Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC8_C13; Fanout = 2; REG Node = '74273:19|16'
Info: Total cell delay = 2.800 ns ( 52.83 % )
Info: Total interconnect delay = 2.500 ns ( 47.17 % )
Info: - Longest clock path from clock "CLK" to source register is 88.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 52; CLK Node = 'CLK'
Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 9.500 ns; Loc. = LC8_B7; Fanout = 5; REG Node = '74160:inst|9'
Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 16.600 ns; Loc. = LC5_A9; Fanout = 5; REG Node = '74160:inst2|9'
Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 19.500 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 23.800 ns; Loc. = LC6_C11; Fanout = 5; REG Node = '74160:inst3|9'
Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 26.700 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 30.000 ns; Loc. = LC1_C6; Fanout = 5; REG Node = '74160:inst6|9'
Info: 10: + IC(0.600 ns) + CELL(2.300 ns) = 32.900 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 37.700 ns; Loc. = LC5_B22; Fanout = 5; REG Node = '74160:inst7|9'
Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 40.600 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 44.500 ns; Loc. = LC2_B8; Fanout = 5; REG Node = '74160:inst8|9'
Info: 14: + IC(2.700 ns) + CELL(2.300 ns) = 49.500 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 53.200 ns; Loc. = LC6_B6; Fanout = 5; REG Node = '74160:inst9|9'
Info: 16: + IC(0.600 ns) + CELL(2.300 ns) = 56.100 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 59.900 ns; Loc. = LC2_B17; Fanout = 5; REG Node = '74160:inst10|9'
Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 62.800 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 67.000 ns; Loc. = LC4_A20; Fanout = 5; REG Node = '74160:inst12|9'
Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 69.900 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 73.600 ns; Loc. = LC8_A16; Fanout = 5; REG Node = '74160:inst13|9'
Info: 22: + IC(0.600 ns) + CELL(2.300 ns) = 76.500 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.300 ns) + CELL(1.100 ns) = 79.900 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: 24: + IC(2.400 ns) + CELL(2.300 ns) = 84.600 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 88.000 ns; Loc. = LC1_C13; Fanout = 5; REG Node = '74160:inst15|9'
Info: Total cell delay = 42.000 ns ( 47.73 % )
Info: Total interconnect delay = 46.000 ns ( 52.27 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Info: Clock "SIGNAL" has Internal fmax of 64.94 MHz between source register "74160:inst14|9" and destination register "74160:inst14|7" (period= 15.4 ns)
Info: + Longest register to register delay is 6.600 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: 2: + IC(2.500 ns) + CELL(2.300 ns) = 4.800 ns; Loc. = LC7_A22; Fanout = 1; COMB Node = '74160:inst14|49~23'
Info: 3: + IC(0.600 ns) + CELL(1.200 ns) = 6.600 ns; Loc. = LC1_A22; Fanout = 5; REG Node = '74160:inst14|7'
Info: Total cell delay = 3.500 ns ( 53.03 % )
Info: Total interconnect delay = 3.100 ns ( 46.97 % )
Info: - Smallest clock skew is -5.200 ns
Info: + Shortest clock path from clock "SIGNAL" to destination register is 74.100 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_78; Fanout = 2; CLK Node = 'SIGNAL'
Info: 2: + IC(1.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 10.000 ns; Loc. = LC2_B7; Fanout = 7; REG Node = '74160:inst|6'
Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 12.400 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 16.600 ns; Loc. = LC4_A9; Fanout = 7; REG Node = '74160:inst2|6'
Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 19.000 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 23.300 ns; Loc. = LC3_C11; Fanout = 7; REG Node = '74160:inst3|6'
Info: 8: + IC(0.600 ns) + CELL(1.800 ns) = 25.700 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 29.000 ns; Loc. = LC3_C6; Fanout = 7; REG Node = '74160:inst6|6'
Info: 10: + IC(0.600 ns) + CELL(1.800 ns) = 31.400 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 36.200 ns; Loc. = LC8_B22; Fanout = 7; REG Node = '74160:inst7|6'
Info: 12: + IC(0.600 ns) + CELL(1.800 ns) = 38.600 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 42.500 ns; Loc. = LC6_B8; Fanout = 7; REG Node = '74160:inst8|6'
Info: 14: + IC(2.400 ns) + CELL(1.800 ns) = 46.700 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 50.400 ns; Loc. = LC5_B6; Fanout = 7; REG Node = '74160:inst9|6'
Info: 16: + IC(0.600 ns) + CELL(1.800 ns) = 52.800 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 56.600 ns; Loc. = LC6_B17; Fanout = 7; REG Node = '74160:inst10|6'
Info: 18: + IC(0.600 ns) + CELL(1.800 ns) = 59.000 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 63.200 ns; Loc. = LC1_A20; Fanout = 7; REG Node = '74160:inst12|6'
Info: 20: + IC(0.600 ns) + CELL(1.800 ns) = 65.600 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 69.300 ns; Loc. = LC5_A16; Fanout = 7; REG Node = '74160:inst13|6'
Info: 22: + IC(0.600 ns) + CELL(1.800 ns) = 71.700 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.400 ns) + CELL(0.000 ns) = 74.100 ns; Loc. = LC1_A22; Fanout = 5; REG Node = '74160:inst14|7'
Info: Total cell delay = 34.100 ns ( 46.02 % )
Info: Total interconnect delay = 40.000 ns ( 53.98 % )
Info: - Longest clock path from clock "SIGNAL" to source register is 79.300 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_78; Fanout = 2; CLK Node = 'SIGNAL'
Info: 2: + IC(1.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 10.000 ns; Loc. = LC8_B7; Fanout = 5; REG Node = '74160:inst|9'
Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 12.900 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 17.100 ns; Loc. = LC5_A9; Fanout = 5; REG Node = '74160:inst2|9'
Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 20.000 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 24.300 ns; Loc. = LC6_C11; Fanout = 5; REG Node = '74160:inst3|9'
Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 27.200 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 30.500 ns; Loc. = LC1_C6; Fanout = 5; REG Node = '74160:inst6|9'
Info: 10: + IC(0.600 ns) + CELL(2.300 ns) = 33.400 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 38.200 ns; Loc. = LC5_B22; Fanout = 5; REG Node = '74160:inst7|9'
Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 41.100 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 45.000 ns; Loc. = LC2_B8; Fanout = 5; REG Node = '74160:inst8|9'
Info: 14: + IC(2.700 ns) + CELL(2.300 ns) = 50.000 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 53.700 ns; Loc. = LC6_B6; Fanout = 5; REG Node = '74160:inst9|9'
Info: 16: + IC(0.600 ns) + CELL(2.300 ns) = 56.600 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 60.400 ns; Loc. = LC2_B17; Fanout = 5; REG Node = '74160:inst10|9'
Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 63.300 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 67.500 ns; Loc. = LC4_A20; Fanout = 5; REG Node = '74160:inst12|9'
Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 70.400 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 74.100 ns; Loc. = LC8_A16; Fanout = 5; REG Node = '74160:inst13|9'
Info: 22: + IC(0.600 ns) + CELL(2.300 ns) = 77.000 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.300 ns) + CELL(0.000 ns) = 79.300 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: Total cell delay = 39.100 ns ( 49.31 % )
Info: Total interconnect delay = 40.200 ns ( 50.69 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Micro setup delay of destination is 2.500 ns
Warning: Circuit may not operate. Detected 77 non-operational path(s) clocked by clock "CLK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "74160:inst15|6" and destination pin or register "74160:inst15|6" for clock "CLK" (Hold time is 4.5 ns)
Info: + Largest clock skew is 5.800 ns
Info: + Longest clock path from clock "CLK" to destination register is 88.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 52; CLK Node = 'CLK'
Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 9.500 ns; Loc. = LC8_B7; Fanout = 5; REG Node = '74160:inst|9'
Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 12.400 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 16.600 ns; Loc. = LC5_A9; Fanout = 5; REG Node = '74160:inst2|9'
Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 19.500 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 23.800 ns; Loc. = LC6_C11; Fanout = 5; REG Node = '74160:inst3|9'
Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 26.700 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 30.000 ns; Loc. = LC1_C6; Fanout = 5; REG Node = '74160:inst6|9'
Info: 10: + IC(0.600 ns) + CELL(2.300 ns) = 32.900 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 37.700 ns; Loc. = LC5_B22; Fanout = 5; REG Node = '74160:inst7|9'
Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 40.600 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 44.500 ns; Loc. = LC2_B8; Fanout = 5; REG Node = '74160:inst8|9'
Info: 14: + IC(2.700 ns) + CELL(2.300 ns) = 49.500 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 53.200 ns; Loc. = LC6_B6; Fanout = 5; REG Node = '74160:inst9|9'
Info: 16: + IC(0.600 ns) + CELL(2.300 ns) = 56.100 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 59.900 ns; Loc. = LC2_B17; Fanout = 5; REG Node = '74160:inst10|9'
Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 62.800 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 67.000 ns; Loc. = LC4_A20; Fanout = 5; REG Node = '74160:inst12|9'
Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 69.900 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 73.600 ns; Loc. = LC8_A16; Fanout = 5; REG Node = '74160:inst13|9'
Info: 22: + IC(0.600 ns) + CELL(2.300 ns) = 76.500 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.300 ns) + CELL(1.100 ns) = 79.900 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: 24: + IC(2.400 ns) + CELL(2.300 ns) = 84.600 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 88.000 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 42.000 ns ( 47.73 % )
Info: Total interconnect delay = 46.000 ns ( 52.27 % )
Info: - Shortest clock path from clock "CLK" to source register is 82.200 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_79; Fanout = 52; CLK Node = 'CLK'
Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 9.500 ns; Loc. = LC2_B7; Fanout = 7; REG Node = '74160:inst|6'
Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 11.900 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 16.100 ns; Loc. = LC4_A9; Fanout = 7; REG Node = '74160:inst2|6'
Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 18.500 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 22.800 ns; Loc. = LC3_C11; Fanout = 7; REG Node = '74160:inst3|6'
Info: 8: + IC(0.600 ns) + CELL(1.800 ns) = 25.200 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 28.500 ns; Loc. = LC3_C6; Fanout = 7; REG Node = '74160:inst6|6'
Info: 10: + IC(0.600 ns) + CELL(1.800 ns) = 30.900 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 35.700 ns; Loc. = LC8_B22; Fanout = 7; REG Node = '74160:inst7|6'
Info: 12: + IC(0.600 ns) + CELL(1.800 ns) = 38.100 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 42.000 ns; Loc. = LC6_B8; Fanout = 7; REG Node = '74160:inst8|6'
Info: 14: + IC(2.400 ns) + CELL(1.800 ns) = 46.200 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 49.900 ns; Loc. = LC5_B6; Fanout = 7; REG Node = '74160:inst9|6'
Info: 16: + IC(0.600 ns) + CELL(1.800 ns) = 52.300 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 56.100 ns; Loc. = LC6_B17; Fanout = 7; REG Node = '74160:inst10|6'
Info: 18: + IC(0.600 ns) + CELL(1.800 ns) = 58.500 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 62.700 ns; Loc. = LC1_A20; Fanout = 7; REG Node = '74160:inst12|6'
Info: 20: + IC(0.600 ns) + CELL(1.800 ns) = 65.100 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 68.800 ns; Loc. = LC5_A16; Fanout = 7; REG Node = '74160:inst13|6'
Info: 22: + IC(0.600 ns) + CELL(1.800 ns) = 71.200 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.400 ns) + CELL(1.100 ns) = 74.700 ns; Loc. = LC6_A22; Fanout = 7; REG Node = '74160:inst14|6'
Info: 24: + IC(2.300 ns) + CELL(1.800 ns) = 78.800 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 82.200 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 36.500 ns ( 44.40 % )
Info: Total interconnect delay = 45.700 ns ( 55.60 % )
Info: - Micro clock to output delay of source is 1.100 ns
Info: - Shortest register to register delay is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 1.200 ns ( 66.67 % )
Info: Total interconnect delay = 0.600 ns ( 33.33 % )
Info: + Micro hold delay of destination is 1.600 ns
Warning: Circuit may not operate. Detected 77 non-operational path(s) clocked by clock "SIGNAL" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "74160:inst15|6" and destination pin or register "74160:inst15|6" for clock "SIGNAL" (Hold time is 4.5 ns)
Info: + Largest clock skew is 5.800 ns
Info: + Longest clock path from clock "SIGNAL" to destination register is 88.500 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_78; Fanout = 2; CLK Node = 'SIGNAL'
Info: 2: + IC(1.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 10.000 ns; Loc. = LC8_B7; Fanout = 5; REG Node = '74160:inst|9'
Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 12.900 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 17.100 ns; Loc. = LC5_A9; Fanout = 5; REG Node = '74160:inst2|9'
Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 20.000 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 24.300 ns; Loc. = LC6_C11; Fanout = 5; REG Node = '74160:inst3|9'
Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 27.200 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 30.500 ns; Loc. = LC1_C6; Fanout = 5; REG Node = '74160:inst6|9'
Info: 10: + IC(0.600 ns) + CELL(2.300 ns) = 33.400 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 38.200 ns; Loc. = LC5_B22; Fanout = 5; REG Node = '74160:inst7|9'
Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 41.100 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 45.000 ns; Loc. = LC2_B8; Fanout = 5; REG Node = '74160:inst8|9'
Info: 14: + IC(2.700 ns) + CELL(2.300 ns) = 50.000 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 53.700 ns; Loc. = LC6_B6; Fanout = 5; REG Node = '74160:inst9|9'
Info: 16: + IC(0.600 ns) + CELL(2.300 ns) = 56.600 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 60.400 ns; Loc. = LC2_B17; Fanout = 5; REG Node = '74160:inst10|9'
Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 63.300 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 67.500 ns; Loc. = LC4_A20; Fanout = 5; REG Node = '74160:inst12|9'
Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 70.400 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 74.100 ns; Loc. = LC8_A16; Fanout = 5; REG Node = '74160:inst13|9'
Info: 22: + IC(0.600 ns) + CELL(2.300 ns) = 77.000 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.300 ns) + CELL(1.100 ns) = 80.400 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: 24: + IC(2.400 ns) + CELL(2.300 ns) = 85.100 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 88.500 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 42.500 ns ( 48.02 % )
Info: Total interconnect delay = 46.000 ns ( 51.98 % )
Info: - Shortest clock path from clock "SIGNAL" to source register is 82.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_78; Fanout = 2; CLK Node = 'SIGNAL'
Info: 2: + IC(1.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 10.000 ns; Loc. = LC2_B7; Fanout = 7; REG Node = '74160:inst|6'
Info: 4: + IC(0.600 ns) + CELL(1.800 ns) = 12.400 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 16.600 ns; Loc. = LC4_A9; Fanout = 7; REG Node = '74160:inst2|6'
Info: 6: + IC(0.600 ns) + CELL(1.800 ns) = 19.000 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 23.300 ns; Loc. = LC3_C11; Fanout = 7; REG Node = '74160:inst3|6'
Info: 8: + IC(0.600 ns) + CELL(1.800 ns) = 25.700 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 29.000 ns; Loc. = LC3_C6; Fanout = 7; REG Node = '74160:inst6|6'
Info: 10: + IC(0.600 ns) + CELL(1.800 ns) = 31.400 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 36.200 ns; Loc. = LC8_B22; Fanout = 7; REG Node = '74160:inst7|6'
Info: 12: + IC(0.600 ns) + CELL(1.800 ns) = 38.600 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 42.500 ns; Loc. = LC6_B8; Fanout = 7; REG Node = '74160:inst8|6'
Info: 14: + IC(2.400 ns) + CELL(1.800 ns) = 46.700 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 50.400 ns; Loc. = LC5_B6; Fanout = 7; REG Node = '74160:inst9|6'
Info: 16: + IC(0.600 ns) + CELL(1.800 ns) = 52.800 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 56.600 ns; Loc. = LC6_B17; Fanout = 7; REG Node = '74160:inst10|6'
Info: 18: + IC(0.600 ns) + CELL(1.800 ns) = 59.000 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 63.200 ns; Loc. = LC1_A20; Fanout = 7; REG Node = '74160:inst12|6'
Info: 20: + IC(0.600 ns) + CELL(1.800 ns) = 65.600 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 69.300 ns; Loc. = LC5_A16; Fanout = 7; REG Node = '74160:inst13|6'
Info: 22: + IC(0.600 ns) + CELL(1.800 ns) = 71.700 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.400 ns) + CELL(1.100 ns) = 75.200 ns; Loc. = LC6_A22; Fanout = 7; REG Node = '74160:inst14|6'
Info: 24: + IC(2.300 ns) + CELL(1.800 ns) = 79.300 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 82.700 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 37.000 ns ( 44.74 % )
Info: Total interconnect delay = 45.700 ns ( 55.26 % )
Info: - Micro clock to output delay of source is 1.100 ns
Info: - Shortest register to register delay is 1.800 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: 2: + IC(0.600 ns) + CELL(1.200 ns) = 1.800 ns; Loc. = LC1_C15; Fanout = 7; REG Node = '74160:inst15|6'
Info: Total cell delay = 1.200 ns ( 66.67 % )
Info: Total interconnect delay = 0.600 ns ( 33.33 % )
Info: + Micro hold delay of destination is 1.600 ns
Info: tco from clock "SIGNAL" to destination pin "co12" through register "74160:inst15|9" is 100.800 ns
Info: + Longest clock path from clock "SIGNAL" to source register is 88.500 ns
Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_78; Fanout = 2; CLK Node = 'SIGNAL'
Info: 2: + IC(1.600 ns) + CELL(2.300 ns) = 6.700 ns; Loc. = LC2_B5; Fanout = 4; COMB Node = 'inst4'
Info: 3: + IC(2.200 ns) + CELL(1.100 ns) = 10.000 ns; Loc. = LC8_B7; Fanout = 5; REG Node = '74160:inst|9'
Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 12.900 ns; Loc. = LC1_B7; Fanout = 5; COMB Node = '74160:inst|49~22'
Info: 5: + IC(3.100 ns) + CELL(1.100 ns) = 17.100 ns; Loc. = LC5_A9; Fanout = 5; REG Node = '74160:inst2|9'
Info: 6: + IC(0.600 ns) + CELL(2.300 ns) = 20.000 ns; Loc. = LC7_A9; Fanout = 5; COMB Node = '74160:inst2|49~22'
Info: 7: + IC(3.200 ns) + CELL(1.100 ns) = 24.300 ns; Loc. = LC6_C11; Fanout = 5; REG Node = '74160:inst3|9'
Info: 8: + IC(0.600 ns) + CELL(2.300 ns) = 27.200 ns; Loc. = LC2_C11; Fanout = 5; COMB Node = '74160:inst3|49~22'
Info: 9: + IC(2.200 ns) + CELL(1.100 ns) = 30.500 ns; Loc. = LC1_C6; Fanout = 5; REG Node = '74160:inst6|9'
Info: 10: + IC(0.600 ns) + CELL(2.300 ns) = 33.400 ns; Loc. = LC5_C6; Fanout = 5; COMB Node = '74160:inst6|49~22'
Info: 11: + IC(3.700 ns) + CELL(1.100 ns) = 38.200 ns; Loc. = LC5_B22; Fanout = 5; REG Node = '74160:inst7|9'
Info: 12: + IC(0.600 ns) + CELL(2.300 ns) = 41.100 ns; Loc. = LC1_B22; Fanout = 5; COMB Node = '74160:inst7|49~22'
Info: 13: + IC(2.800 ns) + CELL(1.100 ns) = 45.000 ns; Loc. = LC2_B8; Fanout = 5; REG Node = '74160:inst8|9'
Info: 14: + IC(2.700 ns) + CELL(2.300 ns) = 50.000 ns; Loc. = LC2_B12; Fanout = 5; COMB Node = '74160:inst8|49~22'
Info: 15: + IC(2.600 ns) + CELL(1.100 ns) = 53.700 ns; Loc. = LC6_B6; Fanout = 5; REG Node = '74160:inst9|9'
Info: 16: + IC(0.600 ns) + CELL(2.300 ns) = 56.600 ns; Loc. = LC7_B6; Fanout = 5; COMB Node = '74160:inst9|49~22'
Info: 17: + IC(2.700 ns) + CELL(1.100 ns) = 60.400 ns; Loc. = LC2_B17; Fanout = 5; REG Node = '74160:inst10|9'
Info: 18: + IC(0.600 ns) + CELL(2.300 ns) = 63.300 ns; Loc. = LC8_B17; Fanout = 5; COMB Node = '74160:inst10|49~22'
Info: 19: + IC(3.100 ns) + CELL(1.100 ns) = 67.500 ns; Loc. = LC4_A20; Fanout = 5; REG Node = '74160:inst12|9'
Info: 20: + IC(0.600 ns) + CELL(2.300 ns) = 70.400 ns; Loc. = LC7_A20; Fanout = 5; COMB Node = '74160:inst12|49~22'
Info: 21: + IC(2.600 ns) + CELL(1.100 ns) = 74.100 ns; Loc. = LC8_A16; Fanout = 5; REG Node = '74160:inst13|9'
Info: 22: + IC(0.600 ns) + CELL(2.300 ns) = 77.000 ns; Loc. = LC3_A16; Fanout = 5; COMB Node = '74160:inst13|49~22'
Info: 23: + IC(2.300 ns) + CELL(1.100 ns) = 80.400 ns; Loc. = LC2_A13; Fanout = 5; REG Node = '74160:inst14|9'
Info: 24: + IC(2.400 ns) + CELL(2.300 ns) = 85.100 ns; Loc. = LC2_A18; Fanout = 5; COMB Node = '74160:inst14|49~22'
Info: 25: + IC(3.400 ns) + CELL(0.000 ns) = 88.500 ns; Loc. = LC1_C13; Fanout = 5; REG Node = '74160:inst15|9'
Info: Total cell delay = 42.500 ns ( 48.02 % )
Info: Total interconnect delay = 46.000 ns ( 51.98 % )
Info: + Micro clock to output delay of source is 1.100 ns
Info: + Longest register to pin delay is 11.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C13; Fanout = 5; REG Node = '74160:inst15|9'
Info: 2: + IC(2.200 ns) + CELL(2.300 ns) = 4.500 ns; Loc. = LC7_C15; Fanout = 1; COMB Node = '74160:inst15|49~22'
Info: 3: + IC(1.600 ns) + CELL(5.100 ns) = 11.200 ns; Loc. = PIN_46; Fanout = 0; PIN Node = 'co12'
Info: Total cell delay = 7.400 ns ( 66.07 % )
Info: Total interconnect delay = 3.800 ns ( 33.93 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
Info: Allocated 110 megabytes of memory during processing
Info: Processing ended: Fri Jan 22 09:53:28 2010
Info: Elapsed time: 00:00:02