-
-
-
-
-
aduc7000_pwm.zip
This project is created using the Keil ARM CA Compiler.
The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3 ...
-
dossier.zip
... possibilist in C++. We thus work on a logical program possibilist, it be-¨¤-statement a logical program resulting from non-classique logic. The goal first of this project is of d¨¦ terminer if a logical program is consisting or not of share the ...
-
fpga_timing.rar
...
UCF/NCF File Syntax
Attributes/Logical
Constraints
Placement Constraints
Relative Location (RLOC)
Constraints
Timing Constraints
Physical Constraints
Relationally Placed Macros
(RPM)
Carry Logic in XC4000
FPGAs
Carry Logic in XC5200
FPGAs
-
jxglTracker.zip
... called jxglTracker. The two main member functions in the class are DrawTrackRect() and Track(). In the DrawTrackRect() function, the logic op is enabled by calling glEnable(GL_COLOR_LOGIC_OP) and the XOR mode is set by calling glLogicOp(GL_XOR). The ...
-
-
-
-
Go To English Version 超过100万源码资源，1000万源码文件免费下载
