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advansys.c：源码内容

*/
if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
{
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
/*
* The first command completed by the RISC will be placed in
* the stopper.
*
* Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
* completed the RISC will set the ASC_RQ_STOPPER bit.
*/
asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Set RISC IRQ physical address start value.
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
asc_dvc->carr_pending_cnt = 0;
AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
(ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
AdvWriteWordRegister(iop_base, IOPW_PC, word);
/* finally, finally, gentlemen, start your engine */
AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
/*
* Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
* Resets should be performed. The RISC has to be running
* to issue a SCSI Bus Reset.
*/
if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
{
/*
* If the BIOS Signature is present in memory, restore the
* BIOS Handshake Configuration Table and do not perform
* a SCSI Bus Reset.
*/
if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
{
/*
* Restore per TID negotiated values.
*/
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
} else
{
if (AdvResetSB(asc_dvc) != ADV_TRUE)
{
warn_code = ASC_WARN_BUSRESET_ERROR;
}
}
}
return warn_code;
}
/*
* Initialize the ASC-38C0800.
*
* On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
*
* For a non-fatal error return a warning code. If there are no warnings
* then 0 is returned.
*
* Needed after initialization for error recovery.
*/
STATIC int
AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
{
AdvPortAddr iop_base;
ushort warn_code;
ADV_DCNT sum;
int begin_addr;
int end_addr;
ushort code_sum;
int word;
int j;
int adv_asc38C0800_expanded_size;
ADV_CARR_T *carrp;
ADV_DCNT contig_len;
ADV_SDCNT buf_size;
ADV_PADDR carr_paddr;
int i;
ushort scsi_cfg1;
uchar byte;
uchar tid;
ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
ushort wdtr_able, sdtr_able, tagqng_able;
uchar max_cmd[ADV_MAX_TID + 1];
/* If there is already an error, don't continue. */
if (asc_dvc->err_code != 0)
{
return ADV_ERROR;
}
/*
* The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
*/
if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
{
asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
return ADV_ERROR;
}
warn_code = 0;
iop_base = asc_dvc->iop_base;
/*
* Save the RISC memory BIOS region before writing the microcode.
* The BIOS may already be loaded and using its RISC LRAM region
* so its region must be saved and restored.
*
* Note: This code makes the assumption, which is currently true,
* that a chip reset does not clear RISC LRAM.
*/
for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
{
AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
}
/*
* Save current per TID negotiated values.
*/
AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
/*
* RAM BIST (RAM Built-In Self Test)
*
* Address : I/O base + offset 0x38h register (byte).
* Function: Bit 7-6(RW) : RAM mode
* Normal Mode : 0x00
* Pre-test Mode : 0x40
* RAM Test Mode : 0x80
* Bit 5 : unused
* Bit 4(RO) : Done bit
* Bit 3-0(RO) : Status
* Host Error : 0x08
* Int_RAM Error : 0x04
* RISC Error : 0x02
* SCSI Error : 0x01
* No Error : 0x00
*
* Note: RAM BIST code should be put right here, before loading the
* microcode and after saving the RISC memory BIOS region.
*/
/*
* LRAM Pre-test
*
* Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
* If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
* an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
* to NORMAL_MODE, return an error too.
*/
for (i = 0; i < 2; i++)
{
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
{
asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
return ADV_ERROR;
}
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
!= NORMAL_VALUE)
{
asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
return ADV_ERROR;
}
}
/*
* LRAM Test - It takes about 1.5 ms to run through the test.
*
* Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
* If Done bit not set or Status not 0, save register byte, set the
* err_code, and return an error.
*/
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
{
/* Get here if Done bit not set or Status not 0. */
asc_dvc->bist_err_code = byte; /* for BIOS display message */
asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
return ADV_ERROR;
}
/* We need to reset back to normal mode after LRAM test passes. */
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
/*
* Load the Microcode
*
* Write the microcode image to RISC memory starting at address 0.
*
*/
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
/* Assume the following compressed format of the microcode buffer:
*
* 254 word (508 byte) table indexed by byte code followed
* by the following byte codes:
*
* 1-Byte Code:
* 00: Emit word 0 in table.
* 01: Emit word 1 in table.
* .
* FD: Emit word 253 in table.
*
* Multi-Byte Code:
* FE WW WW: (3 byte code) Word to emit is the next word WW WW.
* FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
*/
word = 0;
for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
{
if (_adv_asc38C0800_buf[i] == 0xff)
{
for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C0800_buf[i + 3] << 8) |
_adv_asc38C0800_buf[i + 2]));
word++;
}
i += 3;
} else if (_adv_asc38C0800_buf[i] == 0xfe)
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C0800_buf[i + 2] << 8) |
_adv_asc38C0800_buf[i + 1]));
i += 2;
word++;
} else
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
_adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
word++;
}
}
/*
* Set 'word' for later use to clear the rest of memory and save
* the expanded mcode size.
*/
word *= 2;
adv_asc38C0800_expanded_size = word;
/*
* Clear the rest of ASC-38C0800 Internal RAM (16KB).
*/
for (; word < ADV_38C0800_MEMSIZE; word += 2)
{
AdvWriteWordAutoIncLram(iop_base, 0);
}
/*
* Verify the microcode checksum.
*/
sum = 0;
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
{
sum += AdvReadWordAutoIncLram(iop_base);
}
ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %dn", word, i);
ASC_DBG2(1,
"AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lxn",
(ulong) sum, (ulong) _adv_asc38C0800_chksum);
if (sum != _adv_asc38C0800_chksum)
{
asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
return ADV_ERROR;
}
/*
* Restore the RISC memory BIOS region.
*/
for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
{
AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
}
/*
* Calculate and write the microcode code checksum to the microcode
* code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
*/
AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
code_sum = 0;
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
for (word = begin_addr; word < end_addr; word += 2)
{
code_sum += AdvReadWordAutoIncLram(iop_base);
}
AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
/*
* Read microcode version and date.
*/
AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
/*
* Set the chip type to indicate the ASC38C0800.
*/
AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
/*
* Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
* When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
* cable detection and then we are able to read C_DET[3:0].
*
* Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
* Microcode Default Value' section below.
*/
scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
/*
* If the PCI Configuration Command Register "Parity Error Response
* Control" Bit was clear (0), then set the microcode variable
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
{
AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
word |= CONTROL_FLAG_IGNORE_PERR;
AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
}
/*
* For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
* bits for the default FIFO threshold.
*
* Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
*
* For DMA Errata #4 set the BC_THRESH_ENB bit.
*/
AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
/*
* Microcode operating variables for WDTR, SDTR, and command tag
* queuing will be set in AdvInquiryHandling() based on what a
* device reports it is capable of in Inquiry byte 7.
*
* If SCSI Bus Resets have been disabled, then directly set
* SDTR and WDTR from the EEPROM configuration. This will allow
* the BIOS and warm boot to work without a SCSI bus hang on
* the Inquiry caused by host and target mismatched DTR values.
* Without the SCSI Bus Reset, before an Inquiry a device can't
* be assumed to be in Asynchronous, Narrow mode.
*/
if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
{
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
}
/*
* Set microcode operating variables for DISC and SDTR_SPEED1,
* SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
* configuration values.
*
* The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
* SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
* without determining here whether the device supports SDTR.
*/
AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
/*
* Set SCSI_CFG0 Microcode Default Value.
*
* The microcode will set the SCSI_CFG0 register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
asc_dvc->chip_scsi_id);
/*
* Determine SCSI_CFG1 Microcode Default Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
/* Read current SCSI_CFG1 Register value. */
scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
/*
* If the internal narrow cable is reversed all of the SCSI_CTRL
* register signals will be set. Check for and return an error if
* this condition is found.
*/
if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
{
asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
return ADV_ERROR;
}
/*
* All kind of combinations of devices attached to one of four connectors
* are acceptable except HVD device attached. For example, LVD device can
* be attached to SE connector while SE device attached to LVD connector.
* If LVD device attached to SE connector, it only runs up to Ultra speed.
*
* If an HVD device is attached to one of LVD connectors, return an error.
* However, there is no way to detect HVD device attached to SE connectors.
*/
if (scsi_cfg1 & HVD)
{
asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
return ADV_ERROR;
}
/*
* If either SE or LVD automatic termination control is enabled, then
* set the termination value based on a table listed in a_condor.h.
*
* If manual termination was specified with an EEPROM setting then
* 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
* be 'ored' into SCSI_CFG1.
*/
if ((asc_dvc->cfg->termination & TERM_SE) == 0)
{
/* SE automatic termination control is enabled. */
switch(scsi_cfg1 & C_DET_SE)
{
/* TERM_SE_HI: on, TERM_SE_LO: on */
case 0x1: case 0x2: case 0x3:
asc_dvc->cfg->termination |= TERM_SE;
break;
/* TERM_SE_HI: on, TERM_SE_LO: off */
case 0x0:
asc_dvc->cfg->termination |= TERM_SE_HI;
break;
}
}
if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
{
/* LVD automatic termination control is enabled. */
switch(scsi_cfg1 & C_DET_LVD)
{
/* TERM_LVD_HI: on, TERM_LVD_LO: on */
case 0x4: case 0x8: case 0xC:
asc_dvc->cfg->termination |= TERM_LVD;
break;
/* TERM_LVD_HI: off, TERM_LVD_LO: off */
case 0x0:
break;
}
}
/*
* Clear any set TERM_SE and TERM_LVD bits.
*/
scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
/*
* Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
*/
scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
/*
* Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
* and set possibly modified termination control bits in the Microcode
* SCSI_CFG1 Register Value.
*/
scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
/*
* Set SCSI_CFG1 Microcode Default Value
*
* Set possibly modified termination control and reset DIS_TERM_DRV
* bits in the Microcode SCSI_CFG1 Register Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
/*
* Set MEM_CFG Microcode Default Value
*
* The microcode will set the MEM_CFG register using this value
* after it is started below.
*
* MEM_CFG may be accessed as a word or byte, but only bits 0-7
* are defined.
*
* ASC-38C0800 has 16KB internal memory.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
BIOS_EN | RAM_SZ_16KB);
/*
* Set SEL_MASK Microcode Default Value
*
* The microcode will set the SEL_MASK register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
/*
* Build the carrier freelist.
*
* Driver must have already allocated memory and set 'carrier_buf'.
*/
ASC_ASSERT(asc_dvc->carrier_buf != NULL);
carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
asc_dvc->carr_freelist = NULL;
if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
{
buf_size = ADV_CARRIER_BUFSIZE;
} else
{
buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
}
do {
/*
* Get physical address for the carrier 'carrp'.
*/
contig_len = sizeof(ADV_CARR_T);
carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
(ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
buf_size -= sizeof(ADV_CARR_T);
/*
* If the current carrier is not physically contiguous, then
* maybe there was a page crossing. Try the next carrier aligned
* start address.
*/
if (contig_len < sizeof(ADV_CARR_T))
{
carrp++;
continue;
}
carrp->carr_pa = carr_paddr;
carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
/*
* Insert the carrier at the beginning of the freelist.
*/
carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
asc_dvc->carr_freelist = carrp;
carrp++;
}
while (buf_size > 0);
/*
* Set-up the Host->RISC Initiator Command Queue (ICQ).
*/
if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
{
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
/*
* The first command issued will be placed in the stopper carrier.
*/
asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Set RISC ICQ physical address start value.
* carr_pa is LE, must be native before write
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
/*
* Set-up the RISC->Host Initiator Response Queue (IRQ).
*/
if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
{
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
/*
* The first command completed by the RISC will be placed in
* the stopper.
*
* Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
* completed the RISC will set the ASC_RQ_STOPPER bit.
*/
asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Set RISC IRQ physical address start value.
*
* carr_pa is LE, must be native before write *
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
asc_dvc->carr_pending_cnt = 0;
AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
(ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
AdvWriteWordRegister(iop_base, IOPW_PC, word);
/* finally, finally, gentlemen, start your engine */
AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
/*
* Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
* Resets should be performed. The RISC has to be running
* to issue a SCSI Bus Reset.
*/
if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
{
/*
* If the BIOS Signature is present in memory, restore the
* BIOS Handshake Configuration Table and do not perform
* a SCSI Bus Reset.
*/
if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
{
/*
* Restore per TID negotiated values.
*/
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
} else
{
if (AdvResetSB(asc_dvc) != ADV_TRUE)
{
warn_code = ASC_WARN_BUSRESET_ERROR;
}
}
}
return warn_code;
}
/*
* Initialize the ASC-38C1600.
*
* On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
*
* For a non-fatal error return a warning code. If there are no warnings
* then 0 is returned.
*
* Needed after initialization for error recovery.
*/
STATIC int
AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
{
AdvPortAddr iop_base;
ushort warn_code;
ADV_DCNT sum;
int begin_addr;
int end_addr;
ushort code_sum;
long word;
int j;
int adv_asc38C1600_expanded_size;
ADV_CARR_T *carrp;
ADV_DCNT contig_len;
ADV_SDCNT buf_size;
ADV_PADDR carr_paddr;
int i;
ushort scsi_cfg1;
uchar byte;
uchar tid;
ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
uchar max_cmd[ASC_MAX_TID + 1];
/* If there is already an error, don't continue. */
if (asc_dvc->err_code != 0)
{
return ADV_ERROR;
}
/*
* The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
*/
if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
{
asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
return ADV_ERROR;
}
warn_code = 0;
iop_base = asc_dvc->iop_base;
/*
* Save the RISC memory BIOS region before writing the microcode.
* The BIOS may already be loaded and using its RISC LRAM region
* so its region must be saved and restored.
*
* Note: This code makes the assumption, which is currently true,
* that a chip reset does not clear RISC LRAM.
*/
for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
{
AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
}
/*
* Save current per TID negotiated values.
*/
AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ASC_MAX_TID; tid++)
{
AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
/*
* RAM BIST (Built-In Self Test)
*
* Address : I/O base + offset 0x38h register (byte).
* Function: Bit 7-6(RW) : RAM mode
* Normal Mode : 0x00
* Pre-test Mode : 0x40
* RAM Test Mode : 0x80
* Bit 5 : unused
* Bit 4(RO) : Done bit
* Bit 3-0(RO) : Status
* Host Error : 0x08
* Int_RAM Error : 0x04
* RISC Error : 0x02
* SCSI Error : 0x01
* No Error : 0x00
*
* Note: RAM BIST code should be put right here, before loading the
* microcode and after saving the RISC memory BIOS region.
*/
/*
* LRAM Pre-test
*
* Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
* If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
* an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
* to NORMAL_MODE, return an error too.
*/
for (i = 0; i < 2; i++)
{
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
{
asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
return ADV_ERROR;
}
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
!= NORMAL_VALUE)
{
asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
return ADV_ERROR;
}
}
/*
* LRAM Test - It takes about 1.5 ms to run through the test.
*
* Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
* If Done bit not set or Status not 0, save register byte, set the
* err_code, and return an error.
*/
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
{
/* Get here if Done bit not set or Status not 0. */
asc_dvc->bist_err_code = byte; /* for BIOS display message */
asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
return ADV_ERROR;
}
/* We need to reset back to normal mode after LRAM test passes. */
AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
/*
* Load the Microcode
*
* Write the microcode image to RISC memory starting at address 0.
*
*/
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
/*
* Assume the following compressed format of the microcode buffer:
*
* 254 word (508 byte) table indexed by byte code followed
* by the following byte codes:
*
* 1-Byte Code:
* 00: Emit word 0 in table.
* 01: Emit word 1 in table.
* .
* FD: Emit word 253 in table.
*
* Multi-Byte Code:
* FE WW WW: (3 byte code) Word to emit is the next word WW WW.
* FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
*/
word = 0;
for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
{
if (_adv_asc38C1600_buf[i] == 0xff)
{
for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C1600_buf[i + 3] << 8) |
_adv_asc38C1600_buf[i + 2]));
word++;
}
i += 3;
} else if (_adv_asc38C1600_buf[i] == 0xfe)
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C1600_buf[i + 2] << 8) |
_adv_asc38C1600_buf[i + 1]));
i += 2;
word++;
} else
{
AdvWriteWordAutoIncLram(iop_base, (((ushort)
_adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
_adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
word++;
}
}
/*
* Set 'word' for later use to clear the rest of memory and save
* the expanded mcode size.
*/
word *= 2;
adv_asc38C1600_expanded_size = word;
/*
* Clear the rest of ASC-38C1600 Internal RAM (32KB).
*/
for (; word < ADV_38C1600_MEMSIZE; word += 2)
{
AdvWriteWordAutoIncLram(iop_base, 0);
}
/*
* Verify the microcode checksum.
*/
sum = 0;
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
{
sum += AdvReadWordAutoIncLram(iop_base);
}
if (sum != _adv_asc38C1600_chksum)
{
asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
return ADV_ERROR;
}
/*
* Restore the RISC memory BIOS region.
*/
for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
{
AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
}
/*
* Calculate and write the microcode code checksum to the microcode
* code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
*/
AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
code_sum = 0;
AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
for (word = begin_addr; word < end_addr; word += 2)
{
code_sum += AdvReadWordAutoIncLram(iop_base);
}
AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
/*
* Read microcode version and date.
*/
AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
/*
* Set the chip type to indicate the ASC38C1600.
*/
AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
/*
* Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
* When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
* cable detection and then we are able to read C_DET[3:0].
*
* Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
* Microcode Default Value' section below.
*/
scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
/*
* If the PCI Configuration Command Register "Parity Error Response
* Control" Bit was clear (0), then set the microcode variable
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
{
AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
word |= CONTROL_FLAG_IGNORE_PERR;
AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
}
/*
* If the BIOS control flag AIPP (Asynchronous Information
* Phase Protection) disable bit is not set, then set the firmware
* 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
* AIPP checking and encoding.
*/
if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
{
AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
word |= CONTROL_FLAG_ENABLE_AIPP;
AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
}
/*
* For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
* and START_CTL_TH [3:2].
*/
AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
/*
* Microcode operating variables for WDTR, SDTR, and command tag
* queuing will be set in AdvInquiryHandling() based on what a
* device reports it is capable of in Inquiry byte 7.
*
* If SCSI Bus Resets have been disabled, then directly set
* SDTR and WDTR from the EEPROM configuration. This will allow
* the BIOS and warm boot to work without a SCSI bus hang on
* the Inquiry caused by host and target mismatched DTR values.
* Without the SCSI Bus Reset, before an Inquiry a device can't
* be assumed to be in Asynchronous, Narrow mode.
*/
if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
{
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
}
/*
* Set microcode operating variables for DISC and SDTR_SPEED1,
* SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
* configuration values.
*
* The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
* SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
* without determining here whether the device supports SDTR.
*/
AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
/*
* Set SCSI_CFG0 Microcode Default Value.
*
* The microcode will set the SCSI_CFG0 register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
asc_dvc->chip_scsi_id);
/*
* Calculate SCSI_CFG1 Microcode Default Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*
* Each ASC-38C1600 function has only two cable detect bits.
* The bus mode override bits are in IOPB_SOFT_OVER_WR.
*/
scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
/*
* If the cable is reversed all of the SCSI_CTRL register signals
* will be set. Check for and return an error if this condition is
* found.
*/
if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
{
asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
return ADV_ERROR;
}
/*
* Each ASC-38C1600 function has two connectors. Only an HVD device
* can not be connected to either connector. An LVD device or SE device
* may be connected to either connecor. If an SE device is connected,
* then at most Ultra speed (20 Mhz) can be used on both connectors.
*
* If an HVD device is attached, return an error.
*/
if (scsi_cfg1 & HVD)
{
asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
return ADV_ERROR;
}
/*
* Each function in the ASC-38C1600 uses only the SE cable detect and
* termination because there are two connectors for each function. Each
* function may use either LVD or SE mode. Corresponding the SE automatic
* termination control EEPROM bits are used for each function. Each
* function has its own EEPROM. If SE automatic control is enabled for
* the function, then set the termination value based on a table listed
* in a_condor.h.
*
* If manual termination is specified in the EEPROM for the function,
* then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
* ready to be 'ored' into SCSI_CFG1.
*/
if ((asc_dvc->cfg->termination & TERM_SE) == 0)
{
/* SE automatic termination control is enabled. */
switch(scsi_cfg1 & C_DET_SE)
{
/* TERM_SE_HI: on, TERM_SE_LO: on */
case 0x1: case 0x2: case 0x3:
asc_dvc->cfg->termination |= TERM_SE;
break;
case 0x0:
if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
{
/* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
}
else
{
/* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
asc_dvc->cfg->termination |= TERM_SE_HI;
}
break;
}
}
/*
* Clear any set TERM_SE bits.
*/
scsi_cfg1 &= ~TERM_SE;
/*
* Invert the TERM_SE bits and then set 'scsi_cfg1'.
*/
scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
/*
* Clear Big Endian and Terminator Polarity bits and set possibly
* modified termination control bits in the Microcode SCSI_CFG1
* Register Value.
*
* Big Endian bit is not used even on big endian machines.
*/
scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
/*
* Set SCSI_CFG1 Microcode Default Value
*
* Set possibly modified termination control bits in the Microcode
* SCSI_CFG1 Register Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
/*
* Set MEM_CFG Microcode Default Value
*
* The microcode will set the MEM_CFG register using this value
* after it is started below.
*
* MEM_CFG may be accessed as a word or byte, but only bits 0-7
* are defined.
*
* ASC-38C1600 has 32KB internal memory.
*
* XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
* out a special 16K Adv Library and Microcode version. After the issue
* resolved, we should turn back to the 32K support. Both a_condor.h and
* mcode.sas files also need to be updated.
*
* AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
* BIOS_EN | RAM_SZ_32KB);
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
/*
* Set SEL_MASK Microcode Default Value
*
* The microcode will set the SEL_MASK register using this value
* after it is started below.
*/
AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
/*
* Build the carrier freelist.
*
* Driver must have already allocated memory and set 'carrier_buf'.
*/
ASC_ASSERT(asc_dvc->carrier_buf != NULL);
carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
asc_dvc->carr_freelist = NULL;
if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
{
buf_size = ADV_CARRIER_BUFSIZE;
} else
{
buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
}
do {
/*
* Get physical address for the carrier 'carrp'.
*/
contig_len = sizeof(ADV_CARR_T);
carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
(ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
buf_size -= sizeof(ADV_CARR_T);
/*
* If the current carrier is not physically contiguous, then
* maybe there was a page crossing. Try the next carrier aligned
* start address.
*/
if (contig_len < sizeof(ADV_CARR_T))
{
carrp++;
continue;
}
carrp->carr_pa = carr_paddr;
carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
/*
* Insert the carrier at the beginning of the freelist.
*/
carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
asc_dvc->carr_freelist = carrp;
carrp++;
}
while (buf_size > 0);
/*
* Set-up the Host->RISC Initiator Command Queue (ICQ).
*/
if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
{
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
/*
* The first command issued will be placed in the stopper carrier.
*/
asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Set RISC ICQ physical address start value. Initialize the
* COMMA register to the same value otherwise the RISC will
* prematurely detect a command is available.
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
le32_to_cpu(asc_dvc->icq_sp->carr_pa));
/*
* Set-up the RISC->Host Initiator Response Queue (IRQ).
*/
if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
{
asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
return ADV_ERROR;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
/*
* The first command completed by the RISC will be placed in
* the stopper.
*
* Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
* completed the RISC will set the ASC_RQ_STOPPER bit.
*/
asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Set RISC IRQ physical address start value.
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
asc_dvc->carr_pending_cnt = 0;
AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
(ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
AdvWriteWordRegister(iop_base, IOPW_PC, word);
/* finally, finally, gentlemen, start your engine */
AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
/*
* Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
* Resets should be performed. The RISC has to be running
* to issue a SCSI Bus Reset.
*/
if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
{
/*
* If the BIOS Signature is present in memory, restore the
* per TID microcode operating variables.
*/
if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
{
/*
* Restore per TID negotiated values.
*/
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ASC_MAX_TID; tid++)
{
AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
} else
{
if (AdvResetSB(asc_dvc) != ADV_TRUE)
{
warn_code = ASC_WARN_BUSRESET_ERROR;
}
}
}
return warn_code;
}
/*
* Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
* ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
* all of this is done.
*
* On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
*
* For a non-fatal error return a warning code. If there are no warnings
* then 0 is returned.
*
* Note: Chip is stopped on entry.
*/
ASC_INITFUNC(
STATIC int,
AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
)
{
AdvPortAddr iop_base;
ushort warn_code;
ADVEEP_3550_CONFIG eep_config;
int i;
iop_base = asc_dvc->iop_base;
warn_code = 0;
/*
* Read the board's EEPROM configuration.
*
* Set default values if a bad checksum is found.
*/
if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
{
warn_code |= ASC_WARN_EEPROM_CHKSUM;
/*
* Set EEPROM default values.
*/
for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
{
*((uchar *) &eep_config + i) =
*((uchar *) &Default_3550_EEPROM_Config + i);
}
/*
* Assume the 6 byte board serial number that was read
* from EEPROM is correct even if the EEPROM checksum
* failed.
*/
eep_config.serial_number_word3 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
eep_config.serial_number_word2 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
eep_config.serial_number_word1 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
AdvSet3550EEPConfig(iop_base, &eep_config);
}
/*
* Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
* EEPROM configuration that was read.
*
* This is the mapping of EEPROM fields to Adv Library fields.
*/
asc_dvc->wdtr_able = eep_config.wdtr_able;
asc_dvc->sdtr_able = eep_config.sdtr_able;
asc_dvc->ultra_able = eep_config.ultra_able;
asc_dvc->tagqng_able = eep_config.tagqng_able;
asc_dvc->cfg->disc_enable = eep_config.disc_enable;
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
asc_dvc->start_motor = eep_config.start_motor;
asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
asc_dvc->bios_ctrl = eep_config.bios_ctrl;
asc_dvc->no_scam = eep_config.scam_tolerant;
asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
/*
* Set the host maximum queuing (max. 253, min. 16) and the per device
* maximum queuing (max. 63, min. 4).
*/
if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_host_qng == 0)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else
{
eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
}
}
if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_dvc_qng == 0)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else
{
eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
}
}
/*
* If 'max_dvc_qng' is greater than 'max_host_qng', then
* set 'max_dvc_qng' to 'max_host_qng'.
*/
if (eep_config.max_dvc_qng > eep_config.max_host_qng)
{
eep_config.max_dvc_qng = eep_config.max_host_qng;
}
/*
* Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
* values based on possibly adjusted EEPROM values.
*/
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
/*
* If the EEPROM 'termination' field is set to automatic (0), then set
* the ADV_DVC_CFG 'termination' field to automatic also.
*
* If the termination is specified with a non-zero 'termination'
* value check that a legal value is set and set the ADV_DVC_CFG
* 'termination' field appropriately.
*/
if (eep_config.termination == 0)
{
asc_dvc->cfg->termination = 0; /* auto termination */
} else
{
/* Enable manual control with low off / high off. */
if (eep_config.termination == 1)
{
asc_dvc->cfg->termination = TERM_CTL_SEL;
/* Enable manual control with low off / high on. */
} else if (eep_config.termination == 2)
{
asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
/* Enable manual control with low on / high on. */
} else if (eep_config.termination == 3)
{
asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
} else
{
/*
* The EEPROM 'termination' field contains a bad value. Use
* automatic termination instead.
*/
asc_dvc->cfg->termination = 0;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
return warn_code;
}
/*
* Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
* ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
* all of this is done.
*
* On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
*
* For a non-fatal error return a warning code. If there are no warnings
* then 0 is returned.
*
* Note: Chip is stopped on entry.
*/
ASC_INITFUNC(
STATIC int,
AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
)
{
AdvPortAddr iop_base;
ushort warn_code;
ADVEEP_38C0800_CONFIG eep_config;
int i;
uchar tid, termination;
ushort sdtr_speed = 0;
iop_base = asc_dvc->iop_base;
warn_code = 0;
/*
* Read the board's EEPROM configuration.
*
* Set default values if a bad checksum is found.
*/
if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
{
warn_code |= ASC_WARN_EEPROM_CHKSUM;
/*
* Set EEPROM default values.
*/
for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
{
*((uchar *) &eep_config + i) =
*((uchar *) &Default_38C0800_EEPROM_Config + i);
}
/*
* Assume the 6 byte board serial number that was read
* from EEPROM is correct even if the EEPROM checksum
* failed.
*/
eep_config.serial_number_word3 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
eep_config.serial_number_word2 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
eep_config.serial_number_word1 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
AdvSet38C0800EEPConfig(iop_base, &eep_config);
}
/*
* Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
* EEPROM configuration that was read.
*
* This is the mapping of EEPROM fields to Adv Library fields.
*/
asc_dvc->wdtr_able = eep_config.wdtr_able;
asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
asc_dvc->tagqng_able = eep_config.tagqng_able;
asc_dvc->cfg->disc_enable = eep_config.disc_enable;
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
asc_dvc->start_motor = eep_config.start_motor;
asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
asc_dvc->bios_ctrl = eep_config.bios_ctrl;
asc_dvc->no_scam = eep_config.scam_tolerant;
asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
/*
* For every Target ID if any of its 'sdtr_speed[1234]' bits
* are set, then set an 'sdtr_able' bit for it.
*/
asc_dvc->sdtr_able = 0;
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
if (tid == 0)
{
sdtr_speed = asc_dvc->sdtr_speed1;
} else if (tid == 4)
{
sdtr_speed = asc_dvc->sdtr_speed2;
} else if (tid == 8)
{
sdtr_speed = asc_dvc->sdtr_speed3;
} else if (tid == 12)
{
sdtr_speed = asc_dvc->sdtr_speed4;
}
if (sdtr_speed & ADV_MAX_TID)
{
asc_dvc->sdtr_able |= (1 << tid);
}
sdtr_speed >>= 4;
}
/*
* Set the host maximum queuing (max. 253, min. 16) and the per device
* maximum queuing (max. 63, min. 4).
*/
if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_host_qng == 0)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else
{
eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
}
}
if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_dvc_qng == 0)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else
{
eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
}
}
/*
* If 'max_dvc_qng' is greater than 'max_host_qng', then
* set 'max_dvc_qng' to 'max_host_qng'.
*/
if (eep_config.max_dvc_qng > eep_config.max_host_qng)
{
eep_config.max_dvc_qng = eep_config.max_host_qng;
}
/*
* Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
* values based on possibly adjusted EEPROM values.
*/
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
/*
* If the EEPROM 'termination' field is set to automatic (0), then set
* the ADV_DVC_CFG 'termination' field to automatic also.
*
* If the termination is specified with a non-zero 'termination'
* value check that a legal value is set and set the ADV_DVC_CFG
* 'termination' field appropriately.
*/
if (eep_config.termination_se == 0)
{
termination = 0; /* auto termination for SE */
} else
{
/* Enable manual control with low off / high off. */
if (eep_config.termination_se == 1)
{
termination = 0;
/* Enable manual control with low off / high on. */
} else if (eep_config.termination_se == 2)
{
termination = TERM_SE_HI;
/* Enable manual control with low on / high on. */
} else if (eep_config.termination_se == 3)
{
termination = TERM_SE;
} else
{
/*
* The EEPROM 'termination_se' field contains a bad value.
* Use automatic termination instead.
*/
termination = 0;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
if (eep_config.termination_lvd == 0)
{
asc_dvc->cfg->termination = termination; /* auto termination for LVD */
} else
{
/* Enable manual control with low off / high off. */
if (eep_config.termination_lvd == 1)
{
asc_dvc->cfg->termination = termination;
/* Enable manual control with low off / high on. */
} else if (eep_config.termination_lvd == 2)
{
asc_dvc->cfg->termination = termination | TERM_LVD_HI;
/* Enable manual control with low on / high on. */
} else if (eep_config.termination_lvd == 3)
{
asc_dvc->cfg->termination =
termination | TERM_LVD;
} else
{
/*
* The EEPROM 'termination_lvd' field contains a bad value.
* Use automatic termination instead.
*/
asc_dvc->cfg->termination = termination;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
return warn_code;
}
/*
* Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
* ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
* all of this is done.
*
* On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
*
* For a non-fatal error return a warning code. If there are no warnings
* then 0 is returned.
*
* Note: Chip is stopped on entry.
*/
ASC_INITFUNC(
STATIC int,
AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
)
{
AdvPortAddr iop_base;
ushort warn_code;
ADVEEP_38C1600_CONFIG eep_config;
int i;
uchar tid, termination;
ushort sdtr_speed = 0;
iop_base = asc_dvc->iop_base;
warn_code = 0;
/*
* Read the board's EEPROM configuration.
*
* Set default values if a bad checksum is found.
*/
if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
{
warn_code |= ASC_WARN_EEPROM_CHKSUM;
/*
* Set EEPROM default values.
*/
for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
{
if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
{
/*
* Set Function 1 EEPROM Word 0 MSB
*
* Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
* EEPROM bits.
*
* Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
* old Mac system booting problem. The Expansion ROM must
* be disabled in Function 1 for these systems.
*
*/
*((uchar *) &eep_config + i) =
((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
(~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
0xFF)));
/*
* Set the INTAB (bit 11) if the GPIO 0 input indicates
* the Function 1 interrupt line is wired to INTA.
*
* Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
* 1 - Function 1 interrupt line wired to INT A.
* 0 - Function 1 interrupt line wired to INT B.
*
* Note: Adapter boards always have Function 0 wired to INTA.
* Put all 5 GPIO bits in input mode and then read
* their input values.
*/
AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
{
/* Function 1 interrupt wired to INTA; Set EEPROM bit. */
*((uchar *) &eep_config + i) |=
((ADV_EEPROM_INTAB >> 8) & 0xFF);
}
}
else
{
*((uchar *) &eep_config + i) =
*((uchar *) &Default_38C1600_EEPROM_Config + i);
}
}
/*
* Assume the 6 byte board serial number that was read
* from EEPROM is correct even if the EEPROM checksum
* failed.
*/
eep_config.serial_number_word3 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
eep_config.serial_number_word2 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
eep_config.serial_number_word1 =
AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
AdvSet38C1600EEPConfig(iop_base, &eep_config);
}
/*
* Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
* EEPROM configuration that was read.
*
* This is the mapping of EEPROM fields to Adv Library fields.
*/
asc_dvc->wdtr_able = eep_config.wdtr_able;
asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
asc_dvc->ppr_able = 0;
asc_dvc->tagqng_able = eep_config.tagqng_able;
asc_dvc->cfg->disc_enable = eep_config.disc_enable;
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
asc_dvc->start_motor = eep_config.start_motor;
asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
asc_dvc->bios_ctrl = eep_config.bios_ctrl;
asc_dvc->no_scam = eep_config.scam_tolerant;
/*
* For every Target ID if any of its 'sdtr_speed[1234]' bits
* are set, then set an 'sdtr_able' bit for it.
*/
asc_dvc->sdtr_able = 0;
for (tid = 0; tid <= ASC_MAX_TID; tid++)
{
if (tid == 0)
{
sdtr_speed = asc_dvc->sdtr_speed1;
} else if (tid == 4)
{
sdtr_speed = asc_dvc->sdtr_speed2;
} else if (tid == 8)
{
sdtr_speed = asc_dvc->sdtr_speed3;
} else if (tid == 12)
{
sdtr_speed = asc_dvc->sdtr_speed4;
}
if (sdtr_speed & ASC_MAX_TID)
{
asc_dvc->sdtr_able |= (1 << tid);
}
sdtr_speed >>= 4;
}
/*
* Set the host maximum queuing (max. 253, min. 16) and the per device
* maximum queuing (max. 63, min. 4).
*/
if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_host_qng == 0)
{
eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
} else
{
eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
}
}
if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
{
/* If the value is zero, assume it is uninitialized. */
if (eep_config.max_dvc_qng == 0)
{
eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
} else
{
eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
}
}
/*
* If 'max_dvc_qng' is greater than 'max_host_qng', then
* set 'max_dvc_qng' to 'max_host_qng'.
*/
if (eep_config.max_dvc_qng > eep_config.max_host_qng)
{
eep_config.max_dvc_qng = eep_config.max_host_qng;
}
/*
* Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
* values based on possibly adjusted EEPROM values.
*/
asc_dvc->max_host_qng = eep_config.max_host_qng;
asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
/*
* If the EEPROM 'termination' field is set to automatic (0), then set
* the ASC_DVC_CFG 'termination' field to automatic also.
*
* If the termination is specified with a non-zero 'termination'
* value check that a legal value is set and set the ASC_DVC_CFG
* 'termination' field appropriately.
*/
if (eep_config.termination_se == 0)
{
termination = 0; /* auto termination for SE */
} else
{
/* Enable manual control with low off / high off. */
if (eep_config.termination_se == 1)
{
termination = 0;
/* Enable manual control with low off / high on. */
} else if (eep_config.termination_se == 2)
{
termination = TERM_SE_HI;
/* Enable manual control with low on / high on. */
} else if (eep_config.termination_se == 3)
{
termination = TERM_SE;
} else
{
/*
* The EEPROM 'termination_se' field contains a bad value.
* Use automatic termination instead.
*/
termination = 0;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
if (eep_config.termination_lvd == 0)
{
asc_dvc->cfg->termination = termination; /* auto termination for LVD */
} else
{
/* Enable manual control with low off / high off. */
if (eep_config.termination_lvd == 1)
{
asc_dvc->cfg->termination = termination;
/* Enable manual control with low off / high on. */
} else if (eep_config.termination_lvd == 2)
{
asc_dvc->cfg->termination = termination | TERM_LVD_HI;
/* Enable manual control with low on / high on. */
} else if (eep_config.termination_lvd == 3)
{
asc_dvc->cfg->termination =
termination | TERM_LVD;
} else
{
/*
* The EEPROM 'termination_lvd' field contains a bad value.
* Use automatic termination instead.
*/
asc_dvc->cfg->termination = termination;
warn_code |= ASC_WARN_EEPROM_TERMINATION;
}
}
return warn_code;
}
/*
* Read EEPROM configuration into the specified buffer.
*
* Return a checksum based on the EEPROM configuration read.
*/
ASC_INITFUNC(
STATIC ushort,
AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
)
{
ushort wval, chksum;
ushort *wbuf;
int eep_addr;
ushort *charfields;
charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
wbuf = (ushort *) cfg_buf;
chksum = 0;
for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
eep_addr < ADV_EEP_DVC_CFG_END;
eep_addr++, wbuf++)
{
wval = AdvReadEEPWord(iop_base, eep_addr);
chksum += wval; /* Checksum is calculated from word values. */
if (*charfields++) {
*wbuf = le16_to_cpu(wval);
} else {
*wbuf = wval;
}
}
/* Read checksum word. */
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
wbuf++; charfields++;
/* Read rest of EEPROM not covered by the checksum. */
for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
eep_addr < ADV_EEP_MAX_WORD_ADDR;
eep_addr++, wbuf++)
{
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
if (*charfields++) {
*wbuf = le16_to_cpu(*wbuf);
}
}
return chksum;
}
/*
* Read EEPROM configuration into the specified buffer.
*
* Return a checksum based on the EEPROM configuration read.
*/
ASC_INITFUNC(
STATIC ushort,
AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
ADVEEP_38C0800_CONFIG *cfg_buf)
)
{
ushort wval, chksum;
ushort *wbuf;
int eep_addr;
ushort *charfields;
charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
wbuf = (ushort *) cfg_buf;
chksum = 0;
for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
eep_addr < ADV_EEP_DVC_CFG_END;
eep_addr++, wbuf++)
{
wval = AdvReadEEPWord(iop_base, eep_addr);
chksum += wval; /* Checksum is calculated from word values. */
if (*charfields++) {
*wbuf = le16_to_cpu(wval);
} else {
*wbuf = wval;
}
}
/* Read checksum word. */
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
wbuf++; charfields++;
/* Read rest of EEPROM not covered by the checksum. */
for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
eep_addr < ADV_EEP_MAX_WORD_ADDR;
eep_addr++, wbuf++)
{
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
if (*charfields++) {
*wbuf = le16_to_cpu(*wbuf);
}
}
return chksum;
}
/*
* Read EEPROM configuration into the specified buffer.
*
* Return a checksum based on the EEPROM configuration read.
*/
ASC_INITFUNC(
STATIC ushort,
AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
ADVEEP_38C1600_CONFIG *cfg_buf)
)
{
ushort wval, chksum;
ushort *wbuf;
int eep_addr;
ushort *charfields;
charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
wbuf = (ushort *) cfg_buf;
chksum = 0;
for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
eep_addr < ADV_EEP_DVC_CFG_END;
eep_addr++, wbuf++)
{
wval = AdvReadEEPWord(iop_base, eep_addr);
chksum += wval; /* Checksum is calculated from word values. */
if (*charfields++) {
*wbuf = le16_to_cpu(wval);
} else {
*wbuf = wval;
}
}
/* Read checksum word. */
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
wbuf++; charfields++;
/* Read rest of EEPROM not covered by the checksum. */
for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
eep_addr < ADV_EEP_MAX_WORD_ADDR;
eep_addr++, wbuf++)
{
*wbuf = AdvReadEEPWord(iop_base, eep_addr);
if (*charfields++) {
*wbuf = le16_to_cpu(*wbuf);
}
}
return chksum;
}
/*
* Read the EEPROM from specified location
*/
ASC_INITFUNC(
STATIC ushort,
AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
)
{
AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
ASC_EEP_CMD_READ | eep_word_addr);
AdvWaitEEPCmd(iop_base);
return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
}
/*
* Wait for EEPROM command to complete
*/
ASC_INITFUNC(
STATIC void,
AdvWaitEEPCmd(AdvPortAddr iop_base)
)
{
int eep_delay_ms;
for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
{
if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
{
break;
}
DvcSleepMilliSecond(1);
}
if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
{
ASC_ASSERT(0);
}
return;
}
/*
* Write the EEPROM from 'cfg_buf'.
*/
void
AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
{
ushort *wbuf;
ushort addr, chksum;
ushort *charfields;
wbuf = (ushort *) cfg_buf;
charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
chksum = 0;
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
AdvWaitEEPCmd(iop_base);
/*
* Write EEPROM from word 0 to word 20.
*/
for (addr = ADV_EEP_DVC_CFG_BEGIN;
addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
chksum += *wbuf; /* Checksum is calculated from word values. */
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
}
/*
* Write EEPROM checksum at word 21.
*/
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
wbuf++; charfields++;
/*
* Write EEPROM OEM name at words 22 to 29.
*/
for (addr = ADV_EEP_DVC_CTL_BEGIN;
addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
}
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
AdvWaitEEPCmd(iop_base);
return;
}
/*
* Write the EEPROM from 'cfg_buf'.
*/
void
AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
ADVEEP_38C0800_CONFIG *cfg_buf)
{
ushort *wbuf;
ushort *charfields;
ushort addr, chksum;
wbuf = (ushort *) cfg_buf;
charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
chksum = 0;
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
AdvWaitEEPCmd(iop_base);
/*
* Write EEPROM from word 0 to word 20.
*/
for (addr = ADV_EEP_DVC_CFG_BEGIN;
addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
chksum += *wbuf; /* Checksum is calculated from word values. */
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
}
/*
* Write EEPROM checksum at word 21.
*/
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
wbuf++; charfields++;
/*
* Write EEPROM OEM name at words 22 to 29.
*/
for (addr = ADV_EEP_DVC_CTL_BEGIN;
addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
}
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
AdvWaitEEPCmd(iop_base);
return;
}
/*
* Write the EEPROM from 'cfg_buf'.
*/
void
AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
ADVEEP_38C1600_CONFIG *cfg_buf)
{
ushort *wbuf;
ushort *charfields;
ushort addr, chksum;
wbuf = (ushort *) cfg_buf;
charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
chksum = 0;
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
AdvWaitEEPCmd(iop_base);
/*
* Write EEPROM from word 0 to word 20.
*/
for (addr = ADV_EEP_DVC_CFG_BEGIN;
addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
chksum += *wbuf; /* Checksum is calculated from word values. */
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
}
/*
* Write EEPROM checksum at word 21.
*/
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
wbuf++; charfields++;
/*
* Write EEPROM OEM name at words 22 to 29.
*/
for (addr = ADV_EEP_DVC_CTL_BEGIN;
addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
{
ushort word;
if (*charfields++) {
word = cpu_to_le16(*wbuf);
} else {
word = *wbuf;
}
AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
AdvWaitEEPCmd(iop_base);
}
AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
AdvWaitEEPCmd(iop_base);
return;
}
/* a_advlib.c */
/*
* AdvExeScsiQueue() - Send a request to the RISC microcode program.
*
* Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
* add the carrier to the ICQ (Initiator Command Queue), and tickle the
* RISC to notify it a new command is ready to be executed.
*
* If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
* set to SCSI_MAX_RETRY.
*
* Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
* for DMA addresses or math operations are byte swapped to little-endian
* order.
*
* Return:
* ADV_SUCCESS(1) - The request was successfully queued.
* ADV_BUSY(0) - Resource unavailable; Retry again after pending
* request completes.
* ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
* host IC error.
*/
STATIC int
AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
ADV_SCSI_REQ_Q *scsiq)
{
ulong last_int_level;
AdvPortAddr iop_base;
ADV_DCNT req_size;
ADV_PADDR req_paddr;
ADV_CARR_T *new_carrp;
ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
/*
* The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
*/
if (scsiq->target_id > ADV_MAX_TID)
{
scsiq->host_status = QHSTA_M_INVALID_DEVICE;
scsiq->done_status = QD_WITH_ERROR;
return ADV_ERROR;
}
iop_base = asc_dvc->iop_base;
last_int_level = DvcEnterCritical();
/*
* Allocate a carrier ensuring at least one carrier always
* remains on the freelist and initialize fields.
*/
if ((new_carrp = asc_dvc->carr_freelist) == NULL)
{
DvcLeaveCritical(last_int_level);
return ADV_BUSY;
}
asc_dvc->carr_freelist = (ADV_CARR_T *)
ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
asc_dvc->carr_pending_cnt++;
/*
* Set the carrier to be a stopper by setting 'next_vpa'
* to the stopper value. The current stopper will be changed
* below to point to the new stopper.
*/
new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
/*
* Clear the ADV_SCSI_REQ_Q done flag.
*/
scsiq->a_flag &= ~ADV_SCSIQ_DONE;
req_size = sizeof(ADV_SCSI_REQ_Q);
req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
(ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
/* Wait for assertion before making little-endian */
req_paddr = cpu_to_le32(req_paddr);
/* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
scsiq->scsiq_rptr = req_paddr;
scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
/*
* Every ADV_CARR_T.carr_pa is byte swapped to little-endian
* order during initialization.
*/
scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
/*
* Use the current stopper to send the ADV_SCSI_REQ_Q command to
* the microcode. The newly allocated stopper will become the new
* stopper.
*/
asc_dvc->icq_sp->areq_vpa = req_paddr;
/*
* Set the 'next_vpa' pointer for the old stopper to be the
* physical address of the new stopper. The RISC can only
* follow physical addresses.
*/
asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
/*
* Set the host adapter stopper pointer to point to the new carrier.
*/
asc_dvc->icq_sp = new_carrp;
if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
{
/*
* Tickle the RISC to tell it to read its Command Queue Head pointer.
*/
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
{
/*
* Clear the tickle value. In the ASC-3550 the RISC flag
* command 'clr_tickle_a' does not work unless the host
* value is cleared.
*/
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
}
} else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
{
/*
* Notify the RISC a carrier is ready by writing the physical
* address of the new carrier stopper to the COMMA register.
*/
AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
le32_to_cpu(new_carrp->carr_pa));
}
DvcLeaveCritical(last_int_level);
return ADV_SUCCESS;
}
/*
* Reset SCSI Bus and purge all outstanding requests.
*
* Return Value:
* ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
* ADV_FALSE(0) - Microcode command failed.
* ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
* may be hung which requires driver recovery.
*/
STATIC int
AdvResetSB(ADV_DVC_VAR *asc_dvc)
{
int status;
/*
* Send the SCSI Bus Reset idle start idle command which asserts
* the SCSI Bus Reset signal.
*/
status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
if (status != ADV_TRUE)
{
return status;
}
/*
* Delay for the specified SCSI Bus Reset hold time.
*
* The hold time delay is done on the host because the RISC has no
* microsecond accurate timer.
*/
DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
/*
* Send the SCSI Bus Reset end idle command which de-asserts
* the SCSI Bus Reset signal and purges any pending requests.
*/
status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
if (status != ADV_TRUE)
{
return status;
}
DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
return status;
}
/*
* Reset chip and SCSI Bus.
*
* Return Value:
* ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
* ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
*/
STATIC int
AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
{
int status;
ushort wdtr_able, sdtr_able, tagqng_able;
ushort ppr_able = 0;
uchar tid, max_cmd[ADV_MAX_TID + 1];
AdvPortAddr iop_base;
ushort bios_sig;
iop_base = asc_dvc->iop_base;
/*
* Save current per TID negotiated values.
*/
AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
{
AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
}
AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
/*
* Force the AdvInitAsc3550/38C0800Driver() function to
* perform a SCSI Bus Reset by clearing the BIOS signature word.
* The initialization functions assumes a SCSI Bus Reset is not
* needed if the BIOS signature word is present.
*/
AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
/*
* Stop chip and reset it.
*/
AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
DvcSleepMilliSecond(100);
AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
/*
* Reset Adv Library error code, if any, and try
* re-initializing the chip.
*/
asc_dvc->err_code = 0;
if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
{
status = AdvInitAsc38C1600Driver(asc_dvc);
}
else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
{
status = AdvInitAsc38C0800Driver(asc_dvc);
} else
{
status = AdvInitAsc3550Driver(asc_dvc);
}
/* Translate initialization return value to status value. */
if (status == 0)
{
status = ADV_TRUE;
} else
{
status = ADV_FALSE;
}
/*
* Restore the BIOS signature word.
*/
AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
/*
* Restore per TID negotiated values.
*/
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
{
AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
}
AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
for (tid = 0; tid <= ADV_MAX_TID; tid++)
{
AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
max_cmd[tid]);
}
return status;
}
/*
* Adv Library Interrupt Service Routine
*
* This function is called by a driver's interrupt service routine.
* The function disables and re-enables interrupts.
*
* When a microcode idle command is completed, the ADV_DVC_VAR
* 'idle_cmd_done' field is set to ADV_TRUE.
*
* Note: AdvISR() can be called when interrupts are disabled or even
* when there is no hardware interrupt condition present. It will
* always check for completed idle commands and microcode requests.
* This is an important feature that shouldn't be changed because it
* allows commands to be completed from polling mode loops.
*
* Return:
* ADV_TRUE(1) - interrupt was pending
* ADV_FALSE(0) - no interrupt was pending
*/
STATIC int
AdvISR(ADV_DVC_VAR *asc_dvc)
{
AdvPortAddr iop_base;
uchar int_stat;
ushort target_bit;
ADV_CARR_T *free_carrp;
ADV_VADDR irq_next_vpa;
int flags;
ADV_SCSI_REQ_Q *scsiq;
flags = DvcEnterCritical();
iop_base = asc_dvc->iop_base;
/* Reading the register clears the interrupt. */
int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
ADV_INTR_STATUS_INTRC)) == 0)
{
DvcLeaveCritical(flags);
return ADV_FALSE;
}
/*
* Notify the driver of an asynchronous microcode condition by
* calling the ADV_DVC_VAR.async_callback function. The function
* is passed the microcode ASC_MC_INTRB_CODE byte value.
*/
if (int_stat & ADV_INTR_STATUS_INTRB)
{
uchar intrb_code;
AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
{
if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
asc_dvc->carr_pending_cnt != 0)
{
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
{
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
}
}
}
if (asc_dvc->async_callback != 0)
{
(*asc_dvc->async_callback)(asc_dvc, intrb_code);
}
}
/*
* Check if the IRQ stopper carrier contains a completed request.
*/
while (((irq_next_vpa =
le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
{
/*
* Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
* The RISC will have set 'areq_vpa' to a virtual address.
*
* The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
* field to the carrier ADV_CARR_T.areq_vpa field. The conversion
* below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
* in AdvExeScsiQueue().
*/
scsiq = (ADV_SCSI_REQ_Q *)
ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
/*
* Request finished with good status and the queue was not
* DMAed to host memory by the firmware. Set all status fields
* to indicate good status.
*/
if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
{
scsiq->done_status = QD_NO_ERROR;
scsiq->host_status = scsiq->scsi_status = 0;
scsiq->data_cnt = 0L;
}
/*
* Advance the stopper pointer to the next carrier
* ignoring the lower four bits. Free the previous
* stopper carrier.
*/
free_carrp = asc_dvc->irq_sp;
asc_dvc->irq_sp = (ADV_CARR_T *)
ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
free_carrp->next_vpa =
cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
asc_dvc->carr_freelist = free_carrp;
asc_dvc->carr_pending_cnt--;
ASC_ASSERT(scsiq != NULL);
target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
/*
* Clear request microcode control flag.
*/
scsiq->cntl = 0;
/*
* If the command that completed was a SCSI INQUIRY and
* LUN 0 was sent the command, then process the INQUIRY
* command information for the device.
*
* Note: If data returned were either VPD or CmdDt data,
* don't process the INQUIRY command information for
* the device, otherwise may erroneously set *_able bits.
*/
if (scsiq->done_status == QD_NO_ERROR &&
scsiq->cdb[0] == SCSICMD_Inquiry &&
scsiq->target_lun == 0 &&
(scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
== ADV_INQ_RTN_STD_INQUIRY_DATA)
{
AdvInquiryHandling(asc_dvc, scsiq);
}
/*
* Notify the driver of the completed request by passing
* the ADV_SCSI_REQ_Q pointer to its callback function.
*/
scsiq->a_flag |= ADV_SCSIQ_DONE;
(*asc_dvc->isr_callback)(asc_dvc, scsiq);
/*
* Note: After the driver callback function is called, 'scsiq'
* can no longer be referenced.
*
* Fall through and continue processing other completed
* requests...
*/
/*
* Disable interrupts again in case the driver inadvertently
* enabled interrupts in its callback function.
*
* The DvcEnterCritical() return value is ignored, because
* the 'flags' saved when AdvISR() was first entered will be
* used to restore the interrupt flag on exit.
*/
(void) DvcEnterCritical();
}
DvcLeaveCritical(flags);
return ADV_TRUE;
}
/*
* Send an idle command to the chip and wait for completion.
*
* Command completion is polled for once per microsecond.
*
* The function can be called from anywhere including an interrupt handler.
* But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
* functions to prevent reentrancy.
*
* Return Values:
* ADV_TRUE - command completed successfully
* ADV_FALSE - command failed
* ADV_ERROR - command timed out
*/
STATIC int
AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
ushort idle_cmd,
ADV_DCNT idle_cmd_parameter)
{
ulong last_int_level;
int result;
ADV_DCNT i, j;
AdvPortAddr iop_base;
last_int_level = DvcEnterCritical();
iop_base = asc_dvc->iop_base;
/*
* Clear the idle command status which is set by the microcode
* to a non-zero value to indicate when the command is completed.
* The non-zero result is one of the IDLE_CMD_STATUS_* values
* defined in a_advlib.h.
*/
AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
/*
* Write the idle command value after the idle command parameter
* has been written to avoid a race condition. If the order is not
* followed, the microcode may process the idle command before the
* parameters have been written to LRAM.
*/
AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
cpu_to_le32(idle_cmd_parameter));
AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
/*
* Tickle the RISC to tell it to process the idle command.
*/
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
{
/*
* Clear the tickle value. In the ASC-3550 the RISC flag
* command 'clr_tickle_b' does not work unless the host
* value is cleared.
*/
AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
}
/* Wait for up to 100 millisecond for the idle command to timeout. */
for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
{
/* Poll once each microsecond for command completion. */
for (j = 0; j < SCSI_US_PER_MSEC; j++)
{
AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
if (result != 0)
{
DvcLeaveCritical(last_int_level);
return result;
}
DvcDelayMicroSecond(asc_dvc, (ushort) 1);
}
}
ASC_ASSERT(0); /* The idle command should never timeout. */
DvcLeaveCritical(last_int_level);
return ADV_ERROR;
}
/*
* Inquiry Information Byte 7 Handling
*
* Handle SCSI Inquiry Command information for a device by setting
* microcode operating variables that affect WDTR, SDTR, and Tag
* Queuing.
*/
STATIC void
AdvInquiryHandling(
ADV_DVC_VAR *asc_dvc,
ADV_SCSI_REQ_Q *scsiq)
{
AdvPortAddr iop_base;
uchar tid;
ADV_SCSI_INQUIRY *inq;
ushort tidmask;
ushort cfg_word;
/*
* AdvInquiryHandling() requires up to INQUIRY information Byte 7
* to be available.
*
* If less than 8 bytes of INQUIRY information were requested or less
* than 8 bytes were transferred, then return. cdb[4] is the request
* length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
* microcode to the transfer residual count.
*/
if (scsiq->cdb[4] < 8 ||
(scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
{
return;
}
iop_base = asc_dvc->iop_base;
tid = scsiq->target_id;
inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
/*
* WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
*/
if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
{
return;
} else
{
/*
* INQUIRY Byte 7 Handling
*
* Use a device's INQUIRY byte 7 to determine whether it
* supports WDTR, SDTR, and Tag Queuing. If the feature
* is enabled in the EEPROM and the device supports the
* feature, then enable it in the microcode.
*/
tidmask = ADV_TID_TO_TIDMASK(tid);
/*
* Wide Transfers
*
* If the EEPROM enabled WDTR for the device and the device
* supports wide bus (16 bit) transfers, then turn on the
* device's 'wdtr_able' bit and write the new value to the
* microcode.
*/
if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
{
AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
if ((cfg_word & tidmask) == 0)
{
cfg_word |= tidmask;
AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
/*
* Clear the microcode "SDTR negotiation" and "WDTR
* negotiation" done indicators for the target to cause
* it to negotiate with the new setting set above.
* WDTR when accepted causes the target to enter
* asynchronous mode, so SDTR must be negotiated.
*/
AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
cfg_word &= ~tidmask;
AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
cfg_word &= ~tidmask;
AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
}
}
/*
* Synchronous Transfers
*
* If the EEPROM enabled SDTR for the device and the device
* supports synchronous transfers, then turn on the device's
* 'sdtr_able' bit. Write the new value to the microcode.
*/
if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
{
AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
if ((cfg_word & tidmask) == 0)
{
cfg_word |= tidmask;
AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
/*
* Clear the microcode "SDTR negotiation" done indicator
* for the target to cause it to negotiate with the new
* setting set above.
*/
AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
cfg_word &= ~tidmask;
AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
}
}
/*
* If the Inquiry data included enough space for the SPI-3
* Clocking field, then check if DT mode is supported.
*/
if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
(scsiq->cdb[4] >= 57 ||
(scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
{
/*
* PPR (Parallel Protocol Request) Capable
*
* If the device supports DT mode, then it must be PPR capable.
* The PPR message will be used in place of the SDTR and WDTR
* messages to negotiate synchronous speed and offset, transfer
* width, and protocol options.
*/
if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
{
AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
asc_dvc->ppr_able |= tidmask;
AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
}
}
/*
* If the EEPROM enabled Tag Queuing for the device and the
* device supports Tag Queueing, then turn on the device's
* 'tagqng_enable' bit in the microcode and set the microcode
* maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
* value.
*
* Tag Queuing is disabled for the BIOS which runs in polled
* mode and would see no benefit from Tag Queuing. Also by
* disabling Tag Queuing in the BIOS devices with Tag Queuing
* bugs will at least work with the BIOS.
*/
if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
{
AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
cfg_word |= tidmask;
AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
asc_dvc->max_dvc_qng);
}
}
}
MODULE_LICENSE("Dual BSD/GPL");