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Test.sta.zip
Simple Logic test program for VHDL functionality
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parity_generator.zip
... to a data word to enable error checking. There are two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output if the data word contains an odd number of ones. If the data word contains an even number of ones then ...
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DiSyLab1.rar
A vhdl design of a simple arithmetic and logic unit (alu)
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Calculate-Time-Interval.zip
... to compute the time interval taking into account the leap days that are subsumed within the time interval.
Note:
The logic subsumes the time interval by
yearEnd, monthEnd, dayEnd - timeEarlier (within that year)
+ time interval ( ...
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waveformgenerator.zip
The following information has been generated by Exemplar Logic
-- and may be freely distributed and modified.
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-- Design name : smart_waveform
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-- Purpose : This design is a smart waveform generator.
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Univestem.rar
通用逻辑电路自动检测系统的设计Universal logic circuit design of automatic detection system
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