VHDL/FPGA/Verilog

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VHDL

I8253f.tan.rpt：源码内容

Warning: Node "dataout[2]$latch" is a latch
Warning: Node "dataout[3]$latch" is a latch
Warning: Node "dataout[4]$latch" is a latch
Warning: Node "dataout[5]$latch" is a latch
Warning: Node "dataout[6]$latch" is a latch
Warning: Node "dataout[7]$latch" is a latch
Warning: Node "clk_out[0]$latch" is a latch
Warning: Node "clk_out[1]$latch" is a latch
Warning: Node "clk_out[2]$latch" is a latch
Warning: Found combinational loop of 1 nodes
Warning: Node "start2~53"
Warning: Found combinational loop of 1 nodes
Warning: Node "reg0~30"
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "WR" is an undefined clock
Info: Assuming node "RD" is an undefined clock
Info: Assuming node "A1" is an undefined clock
Info: Assuming node "A0" is an undefined clock
Info: Assuming node "CS" is an undefined clock
Info: Assuming node "clk0" is an undefined clock
Info: Assuming node "gate0" is an undefined clock
Info: Assuming node "clk1" is an undefined clock
Info: Assuming node "gate1" is an undefined clock
Info: Assuming node "clk2" is an undefined clock
Info: Assuming node "gate2" is an undefined clock
Warning: Found 110 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "read0" as buffer
Info: Detected ripple clock "read2" as buffer
Info: Detected ripple clock "read1" as buffer
Info: Detected ripple clock "wover2" as buffer
Info: Detected ripple clock "cmd2[5]" as buffer
Info: Detected ripple clock "write2" as buffer
Info: Detected ripple clock "cmd2[4]" as buffer
Info: Detected ripple clock "cmd2[2]" as buffer
Info: Detected ripple clock "cmd2[3]" as buffer
Info: Detected ripple clock "wover1" as buffer
Info: Detected ripple clock "write1" as buffer
Info: Detected ripple clock "cmd1[5]" as buffer
Info: Detected ripple clock "cmd1[4]" as buffer
Info: Detected ripple clock "cmd1[3]" as buffer
Info: Detected ripple clock "cmd1[2]" as buffer
Info: Detected ripple clock "buffer[3]" as buffer
Info: Detected ripple clock "buffer[5]" as buffer
Info: Detected ripple clock "buffer[1]" as buffer
Info: Detected ripple clock "buffer[11]" as buffer
Info: Detected ripple clock "buffer[9]" as buffer
Info: Detected ripple clock "buffer[12]" as buffer
Info: Detected ripple clock "buffer[15]" as buffer
Info: Detected ripple clock "buffer[4]" as buffer
Info: Detected ripple clock "buffer[8]" as buffer
Info: Detected ripple clock "buffer[10]" as buffer
Info: Detected ripple clock "buffer[14]" as buffer
Info: Detected ripple clock "buffer[6]" as buffer
Info: Detected ripple clock "buffer[2]" as buffer
Info: Detected ripple clock "buffer[7]" as buffer
Info: Detected ripple clock "buffer[0]" as buffer
Info: Detected ripple clock "buffer[13]" as buffer
Info: Detected ripple clock "cmd0[3]" as buffer
Info: Detected ripple clock "cmd0[2]" as buffer
Info: Detected ripple clock "cmd[1]" as buffer
Info: Detected ripple clock "cmd[0]" as buffer
Info: Detected ripple clock "wover0" as buffer
Info: Detected ripple clock "cmd[3]" as buffer
Info: Detected ripple clock "cmd[2]" as buffer
Info: Detected ripple clock "cmd[6]" as buffer
Info: Detected ripple clock "cmd[7]" as buffer
Info: Detected ripple clock "cmd[5]" as buffer
Info: Detected ripple clock "cmd[4]" as buffer
Info: Detected ripple clock "cmd0[5]" as buffer
Info: Detected ripple clock "cmd0[4]" as buffer
Info: Detected gated clock "all_set2~424" as buffer
Info: Detected gated clock "all_set1~535" as buffer
Info: Detected gated clock "Mux90~18" as buffer
Info: Detected gated clock "Mux10~83" as buffer
Info: Detected gated clock "dataout[2]~1606" as buffer
Info: Detected gated clock "dataout[2]~1605" as buffer
Info: Detected gated clock "WideOr2" as buffer
Info: Detected gated clock "WideOr5" as buffer
Info: Detected gated clock "WideOr3" as buffer
Info: Detected gated clock "wover2~48" as buffer
Info: Detected gated clock "set2[8]~153" as buffer
Info: Detected gated clock "WideOr1" as buffer
Info: Detected ripple clock "wlh2[1]" as buffer
Info: Detected ripple clock "wlh2[0]" as buffer
Info: Detected gated clock "set2[5]~151" as buffer
Info: Detected gated clock "cmd2[1]~0" as buffer
Info: Detected gated clock "set2[5]~152" as buffer
Info: Detected gated clock "wover1~48" as buffer
Info: Detected gated clock "set1[8]~153" as buffer
Info: Detected gated clock "Decoder0~411" as buffer
Info: Detected gated clock "WideOr1~33" as buffer
Info: Detected gated clock "Decoder0~413" as buffer
Info: Detected gated clock "Decoder0~410" as buffer
Info: Detected gated clock "Decoder0~414" as buffer
Info: Detected gated clock "Decoder0~412" as buffer
Info: Detected ripple clock "wlh1[0]" as buffer
Info: Detected ripple clock "wlh1[1]" as buffer
Info: Detected gated clock "set1[0]~151" as buffer
Info: Detected gated clock "cmd1[1]~0" as buffer
Info: Detected gated clock "set1[0]~152" as buffer
Info: Detected gated clock "buffer~70" as buffer
Info: Detected gated clock "buffer~71" as buffer
Info: Detected gated clock "buffer~74" as buffer
Info: Detected gated clock "buffer~68" as buffer
Info: Detected gated clock "buffer~72" as buffer
Info: Detected gated clock "buffer~73" as buffer
Info: Detected gated clock "buffer~75" as buffer
Info: Detected gated clock "buffer~69" as buffer
Info: Detected gated clock "buffer~0" as buffer
Info: Detected ripple clock "cnt0[4]~reg0" as buffer
Info: Detected ripple clock "cnt0[1]~reg0" as buffer
Info: Detected ripple clock "cnt0[10]~reg0" as buffer
Info: Detected ripple clock "cnt0[2]~reg0" as buffer
Info: Detected ripple clock "cnt0[3]~reg0" as buffer
Info: Detected ripple clock "cnt0[9]~reg0" as buffer
Info: Detected ripple clock "cnt0[7]~reg0" as buffer
Info: Detected ripple clock "cnt0[8]~reg0" as buffer
Info: Detected ripple clock "cnt0[6]~reg0" as buffer
Info: Detected ripple clock "cnt0[15]~reg0" as buffer
Info: Detected ripple clock "cnt0[12]~reg0" as buffer
Info: Detected ripple clock "cnt0[14]~reg0" as buffer
Info: Detected ripple clock "cnt0[13]~reg0" as buffer
Info: Detected ripple clock "cnt0[11]~reg0" as buffer
Info: Detected ripple clock "cnt0[5]~reg0" as buffer
Info: Detected ripple clock "cnt0[0]~reg0" as buffer
Info: Detected gated clock "set0[8]~157" as buffer
Info: Detected gated clock "wover0~48" as buffer
Info: Detected gated clock "WideOr7~301" as buffer
Info: Detected gated clock "WideOr7~302" as buffer
Info: Detected gated clock "Decoder0~415" as buffer
Info: Detected gated clock "cmd0[1]~0" as buffer
Info: Detected ripple clock "wlh0[1]" as buffer
Info: Detected ripple clock "wlh0[0]" as buffer
Info: Detected gated clock "Decoder0" as buffer
Info: Detected gated clock "set0[0]~158" as buffer
Info: Detected gated clock "set0[0]~159" as buffer
Info: Clock "WR" has Internal fmax of 67.66 MHz between source register "wover2" and destination register "wreset2" (period= 14.78 ns)
Info: + Longest register to register delay is 0.646 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: 2: + IC(0.418 ns) + CELL(0.228 ns) = 0.646 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 0.228 ns ( 35.29 % )
Info: Total interconnect delay = 0.418 ns ( 64.71 % )
Info: - Smallest clock skew is -5.886 ns
Info: + Shortest clock path from clock "WR" to destination register is 3.075 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_B8; Fanout = 7; CLK Node = 'WR'
Info: 2: + IC(0.862 ns) + CELL(0.053 ns) = 1.772 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.053 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.507 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 5: + IC(0.343 ns) + CELL(0.225 ns) = 3.075 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 1.413 ns ( 45.95 % )
Info: Total interconnect delay = 1.662 ns ( 54.05 % )
Info: - Longest clock path from clock "WR" to source register is 8.961 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_B8; Fanout = 7; CLK Node = 'WR'
Info: 2: + IC(1.093 ns) + CELL(0.346 ns) = 2.296 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.771 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.711 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.315 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.776 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.551 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.468 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.732 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.961 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.251 ns ( 36.28 % )
Info: Total interconnect delay = 5.710 ns ( 63.72 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Micro setup delay of destination is 0.858 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "RD" has Internal fmax of 68.9 MHz between source register "wover2" and destination register "wreset2" (period= 14.514 ns)
Info: + Longest register to register delay is 0.646 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: 2: + IC(0.418 ns) + CELL(0.228 ns) = 0.646 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 0.228 ns ( 35.29 % )
Info: Total interconnect delay = 0.418 ns ( 64.71 % )
Info: - Smallest clock skew is -5.753 ns
Info: + Shortest clock path from clock "RD" to destination register is 3.236 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(0.899 ns) + CELL(0.225 ns) = 1.933 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.214 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.668 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 5: + IC(0.343 ns) + CELL(0.225 ns) = 3.236 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 1.537 ns ( 47.50 % )
Info: Total interconnect delay = 1.699 ns ( 52.50 % )
Info: - Longest clock path from clock "RD" to source register is 8.989 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(1.149 ns) + CELL(0.366 ns) = 2.324 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.799 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.739 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.343 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.804 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.579 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.496 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.760 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.989 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.223 ns ( 35.85 % )
Info: Total interconnect delay = 5.766 ns ( 64.15 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Micro setup delay of destination is 0.858 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "A1" has Internal fmax of 73.34 MHz between source register "wover2" and destination register "wreset2" (period= 13.636 ns)
Info: + Longest register to register delay is 0.646 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: 2: + IC(0.418 ns) + CELL(0.228 ns) = 0.646 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 0.228 ns ( 35.29 % )
Info: Total interconnect delay = 0.418 ns ( 64.71 % )
Info: - Smallest clock skew is -5.314 ns
Info: + Shortest clock path from clock "A1" to destination register is 3.247 ns
Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_B10; Fanout = 7; CLK Node = 'A1'
Info: 2: + IC(0.938 ns) + CELL(0.053 ns) = 1.763 ns; Loc. = LCCOMB_X26_Y23_N12; Fanout = 5; COMB Node = 'Decoder0~412'
Info: 3: + IC(0.237 ns) + CELL(0.225 ns) = 2.225 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.679 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 5: + IC(0.343 ns) + CELL(0.225 ns) = 3.247 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 1.500 ns ( 46.20 % )
Info: Total interconnect delay = 1.747 ns ( 53.80 % )
Info: - Longest clock path from clock "A1" to source register is 8.561 ns
Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_B10; Fanout = 7; CLK Node = 'A1'
Info: 2: + IC(1.071 ns) + CELL(0.053 ns) = 1.896 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.371 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.311 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 3.915 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.376 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.151 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.068 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.332 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.561 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 2.873 ns ( 33.56 % )
Info: Total interconnect delay = 5.688 ns ( 66.44 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Micro setup delay of destination is 0.858 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "A0" has Internal fmax of 71.92 MHz between source register "wover2" and destination register "wreset2" (period= 13.904 ns)
Info: + Longest register to register delay is 0.646 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: 2: + IC(0.418 ns) + CELL(0.228 ns) = 0.646 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 0.228 ns ( 35.29 % )
Info: Total interconnect delay = 0.418 ns ( 64.71 % )
Info: - Smallest clock skew is -5.448 ns
Info: + Shortest clock path from clock "A0" to destination register is 3.418 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_B9; Fanout = 7; CLK Node = 'A0'
Info: 2: + IC(0.960 ns) + CELL(0.346 ns) = 2.115 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.396 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.850 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 5: + IC(0.343 ns) + CELL(0.225 ns) = 3.418 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 1.658 ns ( 48.51 % )
Info: Total interconnect delay = 1.760 ns ( 51.49 % )
Info: - Longest clock path from clock "A0" to source register is 8.866 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_B9; Fanout = 7; CLK Node = 'A0'
Info: 2: + IC(1.167 ns) + CELL(0.225 ns) = 2.201 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.676 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.616 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.220 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.681 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.456 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.373 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.637 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.866 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.082 ns ( 34.76 % )
Info: Total interconnect delay = 5.784 ns ( 65.24 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Micro setup delay of destination is 0.858 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "CS" has Internal fmax of 69.75 MHz between source register "wover2" and destination register "wreset2" (period= 14.336 ns)
Info: + Longest register to register delay is 0.646 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: 2: + IC(0.418 ns) + CELL(0.228 ns) = 0.646 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 0.228 ns ( 35.29 % )
Info: Total interconnect delay = 0.418 ns ( 64.71 % )
Info: - Smallest clock skew is -5.664 ns
Info: + Shortest clock path from clock "CS" to destination register is 3.302 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A8; Fanout = 7; CLK Node = 'CS'
Info: 2: + IC(0.914 ns) + CELL(0.228 ns) = 1.999 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.280 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.734 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 5: + IC(0.343 ns) + CELL(0.225 ns) = 3.302 ns; Loc. = LCCOMB_X27_Y23_N30; Fanout = 2; REG Node = 'wreset2'
Info: Total cell delay = 1.588 ns ( 48.09 % )
Info: Total interconnect delay = 1.714 ns ( 51.91 % )
Info: - Longest clock path from clock "CS" to source register is 8.966 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A8; Fanout = 7; CLK Node = 'CS'
Info: 2: + IC(1.216 ns) + CELL(0.228 ns) = 2.301 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.776 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.716 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.320 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.781 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.556 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.473 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.737 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.966 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.133 ns ( 34.94 % )
Info: Total interconnect delay = 5.833 ns ( 65.06 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Micro setup delay of destination is 0.858 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Info: Clock "clk0" has Internal fmax of 343.88 MHz between source register "cnt0[13]~reg0" and destination register "cnt0[5]~reg0" (period= 2.908 ns)
Info: + Longest register to register delay is 2.724 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y18_N27; Fanout = 8; REG Node = 'cnt0[13]~reg0'
Info: 2: + IC(0.370 ns) + CELL(0.366 ns) = 0.736 ns; Loc. = LCCOMB_X29_Y18_N10; Fanout = 2; COMB Node = 'Mux89~83'
Info: 3: + IC(0.256 ns) + CELL(0.228 ns) = 1.220 ns; Loc. = LCCOMB_X29_Y18_N18; Fanout = 3; COMB Node = 'Equal36~68'
Info: 4: + IC(0.391 ns) + CELL(0.053 ns) = 1.664 ns; Loc. = LCCOMB_X29_Y18_N22; Fanout = 15; COMB Node = 'all_gate0~101DUPLICATE'
Info: 5: + IC(0.314 ns) + CELL(0.746 ns) = 2.724 ns; Loc. = LCFF_X30_Y18_N11; Fanout = 10; REG Node = 'cnt0[5]~reg0'
Info: Total cell delay = 1.393 ns ( 51.14 % )
Info: Total interconnect delay = 1.331 ns ( 48.86 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk0" to destination register is 2.594 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_C7; Fanout = 16; CLK Node = 'clk0'
Info: 2: + IC(1.119 ns) + CELL(0.618 ns) = 2.594 ns; Loc. = LCFF_X30_Y18_N11; Fanout = 10; REG Node = 'cnt0[5]~reg0'
Info: Total cell delay = 1.475 ns ( 56.86 % )
Info: Total interconnect delay = 1.119 ns ( 43.14 % )
Info: - Longest clock path from clock "clk0" to source register is 2.594 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_C7; Fanout = 16; CLK Node = 'clk0'
Info: 2: + IC(1.119 ns) + CELL(0.618 ns) = 2.594 ns; Loc. = LCFF_X30_Y18_N27; Fanout = 8; REG Node = 'cnt0[13]~reg0'
Info: Total cell delay = 1.475 ns ( 56.86 % )
Info: Total interconnect delay = 1.119 ns ( 43.14 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "gate0" Internal fmax is restricted to 500.0 MHz between source register "edge0" and destination register "edge0"
Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.488 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y18_N13; Fanout = 2; REG Node = 'edge0'
Info: 2: + IC(0.000 ns) + CELL(0.333 ns) = 0.333 ns; Loc. = LCCOMB_X29_Y18_N12; Fanout = 1; COMB Node = 'edge0~31'
Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.488 ns; Loc. = LCFF_X29_Y18_N13; Fanout = 2; REG Node = 'edge0'
Info: Total cell delay = 0.488 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "gate0" to destination register is 2.680 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A7; Fanout = 8; CLK Node = 'gate0'
Info: 2: + IC(1.205 ns) + CELL(0.618 ns) = 2.680 ns; Loc. = LCFF_X29_Y18_N13; Fanout = 2; REG Node = 'edge0'
Info: Total cell delay = 1.475 ns ( 55.04 % )
Info: Total interconnect delay = 1.205 ns ( 44.96 % )
Info: - Longest clock path from clock "gate0" to source register is 2.680 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A7; Fanout = 8; CLK Node = 'gate0'
Info: 2: + IC(1.205 ns) + CELL(0.618 ns) = 2.680 ns; Loc. = LCFF_X29_Y18_N13; Fanout = 2; REG Node = 'edge0'
Info: Total cell delay = 1.475 ns ( 55.04 % )
Info: Total interconnect delay = 1.205 ns ( 44.96 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk1" has Internal fmax of 368.19 MHz between source register "cnt1[10]" and destination register "cnt1[1]" (period= 2.716 ns)
Info: + Longest register to register delay is 2.532 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y14_N21; Fanout = 6; REG Node = 'cnt1[10]'
Info: 2: + IC(0.364 ns) + CELL(0.366 ns) = 0.730 ns; Loc. = LCCOMB_X33_Y14_N14; Fanout = 1; COMB Node = 'Equal31~97'
Info: 3: + IC(0.243 ns) + CELL(0.228 ns) = 1.201 ns; Loc. = LCCOMB_X33_Y14_N10; Fanout = 5; COMB Node = 'Equal31~98'
Info: 4: + IC(0.221 ns) + CELL(0.053 ns) = 1.475 ns; Loc. = LCCOMB_X33_Y14_N6; Fanout = 15; COMB Node = 'all_gate1~187DUPLICATE'
Info: 5: + IC(0.311 ns) + CELL(0.746 ns) = 2.532 ns; Loc. = LCFF_X34_Y14_N3; Fanout = 6; REG Node = 'cnt1[1]'
Info: Total cell delay = 1.393 ns ( 55.02 % )
Info: Total interconnect delay = 1.139 ns ( 44.98 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk1" to destination register is 2.491 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk1~clkctrl'
Info: 3: + IC(0.676 ns) + CELL(0.618 ns) = 2.491 ns; Loc. = LCFF_X34_Y14_N3; Fanout = 6; REG Node = 'cnt1[1]'
Info: Total cell delay = 1.472 ns ( 59.09 % )
Info: Total interconnect delay = 1.019 ns ( 40.91 % )
Info: - Longest clock path from clock "clk1" to source register is 2.491 ns
Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk1'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 16; COMB Node = 'clk1~clkctrl'
Info: 3: + IC(0.676 ns) + CELL(0.618 ns) = 2.491 ns; Loc. = LCFF_X34_Y14_N21; Fanout = 6; REG Node = 'cnt1[10]'
Info: Total cell delay = 1.472 ns ( 59.09 % )
Info: Total interconnect delay = 1.019 ns ( 40.91 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "gate1" Internal fmax is restricted to 500.0 MHz between source register "edge1" and destination register "edge1"
Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.488 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y14_N13; Fanout = 3; REG Node = 'edge1'
Info: 2: + IC(0.000 ns) + CELL(0.333 ns) = 0.333 ns; Loc. = LCCOMB_X33_Y14_N12; Fanout = 1; COMB Node = 'edge1~31'
Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.488 ns; Loc. = LCFF_X33_Y14_N13; Fanout = 3; REG Node = 'edge1'
Info: Total cell delay = 0.488 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "gate1" to destination register is 3.127 ns
Info: 1: + IC(0.000 ns) + CELL(0.762 ns) = 0.762 ns; Loc. = PIN_C10; Fanout = 5; CLK Node = 'gate1'
Info: 2: + IC(1.747 ns) + CELL(0.618 ns) = 3.127 ns; Loc. = LCFF_X33_Y14_N13; Fanout = 3; REG Node = 'edge1'
Info: Total cell delay = 1.380 ns ( 44.13 % )
Info: Total interconnect delay = 1.747 ns ( 55.87 % )
Info: - Longest clock path from clock "gate1" to source register is 3.127 ns
Info: 1: + IC(0.000 ns) + CELL(0.762 ns) = 0.762 ns; Loc. = PIN_C10; Fanout = 5; CLK Node = 'gate1'
Info: 2: + IC(1.747 ns) + CELL(0.618 ns) = 3.127 ns; Loc. = LCFF_X33_Y14_N13; Fanout = 3; REG Node = 'edge1'
Info: Total cell delay = 1.380 ns ( 44.13 % )
Info: Total interconnect delay = 1.747 ns ( 55.87 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk2" has Internal fmax of 318.67 MHz between source register "cnt2[13]" and destination register "cnt2[7]" (period= 3.138 ns)
Info: + Longest register to register delay is 2.954 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y26_N27; Fanout = 6; REG Node = 'cnt2[13]'
Info: 2: + IC(0.565 ns) + CELL(0.357 ns) = 0.922 ns; Loc. = LCCOMB_X33_Y26_N4; Fanout = 1; COMB Node = 'Equal41~97'
Info: 3: + IC(0.204 ns) + CELL(0.053 ns) = 1.179 ns; Loc. = LCCOMB_X33_Y26_N8; Fanout = 2; COMB Node = 'Equal41~98'
Info: 4: + IC(0.214 ns) + CELL(0.225 ns) = 1.618 ns; Loc. = LCCOMB_X33_Y26_N10; Fanout = 4; COMB Node = 'Equal41~99'
Info: 5: + IC(0.214 ns) + CELL(0.053 ns) = 1.885 ns; Loc. = LCCOMB_X33_Y26_N0; Fanout = 16; COMB Node = 'all_gate2~340'
Info: 6: + IC(0.323 ns) + CELL(0.746 ns) = 2.954 ns; Loc. = LCFF_X34_Y26_N15; Fanout = 6; REG Node = 'cnt2[7]'
Info: Total cell delay = 1.434 ns ( 48.54 % )
Info: Total interconnect delay = 1.520 ns ( 51.46 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk2" to destination register is 2.511 ns
Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'clk2~clkctrl'
Info: 3: + IC(0.686 ns) + CELL(0.618 ns) = 2.511 ns; Loc. = LCFF_X34_Y26_N15; Fanout = 6; REG Node = 'cnt2[7]'
Info: Total cell delay = 1.482 ns ( 59.02 % )
Info: Total interconnect delay = 1.029 ns ( 40.98 % )
Info: - Longest clock path from clock "clk2" to source register is 2.511 ns
Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'clk2~clkctrl'
Info: 3: + IC(0.686 ns) + CELL(0.618 ns) = 2.511 ns; Loc. = LCFF_X34_Y26_N27; Fanout = 6; REG Node = 'cnt2[13]'
Info: Total cell delay = 1.482 ns ( 59.02 % )
Info: Total interconnect delay = 1.029 ns ( 40.98 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "gate2" Internal fmax is restricted to 500.0 MHz between source register "edge2" and destination register "edge2"
Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.488 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y26_N21; Fanout = 2; REG Node = 'edge2'
Info: 2: + IC(0.000 ns) + CELL(0.333 ns) = 0.333 ns; Loc. = LCCOMB_X33_Y26_N20; Fanout = 1; COMB Node = 'edge2~31'
Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.488 ns; Loc. = LCFF_X33_Y26_N21; Fanout = 2; REG Node = 'edge2'
Info: Total cell delay = 0.488 ns ( 100.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "gate2" to destination register is 2.308 ns
Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_E9; Fanout = 6; CLK Node = 'gate2'
Info: 2: + IC(0.863 ns) + CELL(0.618 ns) = 2.308 ns; Loc. = LCFF_X33_Y26_N21; Fanout = 2; REG Node = 'edge2'
Info: Total cell delay = 1.445 ns ( 62.61 % )
Info: Total interconnect delay = 0.863 ns ( 37.39 % )
Info: - Longest clock path from clock "gate2" to source register is 2.308 ns
Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_E9; Fanout = 6; CLK Node = 'gate2'
Info: 2: + IC(0.863 ns) + CELL(0.618 ns) = 2.308 ns; Loc. = LCFF_X33_Y26_N21; Fanout = 2; REG Node = 'edge2'
Info: Total cell delay = 1.445 ns ( 62.61 % )
Info: Total interconnect delay = 0.863 ns ( 37.39 % )
Info: + Micro clock to output delay of source is 0.094 ns
Info: + Micro setup delay of destination is 0.090 ns
Warning: Circuit may not operate. Detected 189 non-operational path(s) clocked by clock "WR" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "write2" and destination pin or register "wover2" for clock "WR" (Hold time is 5.096 ns)
Info: + Largest clock skew is 6.454 ns
Info: + Longest clock path from clock "WR" to destination register is 8.961 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_B8; Fanout = 7; CLK Node = 'WR'
Info: 2: + IC(1.093 ns) + CELL(0.346 ns) = 2.296 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.771 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.711 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.315 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.776 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.551 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.468 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.732 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.961 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.251 ns ( 36.28 % )
Info: Total interconnect delay = 5.710 ns ( 63.72 % )
Info: - Shortest clock path from clock "WR" to source register is 2.507 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_B8; Fanout = 7; CLK Node = 'WR'
Info: 2: + IC(0.862 ns) + CELL(0.053 ns) = 1.772 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.053 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.507 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: Total cell delay = 1.188 ns ( 47.39 % )
Info: Total interconnect delay = 1.319 ns ( 52.61 % )
Info: - Micro clock to output delay of source is 0.000 ns
Info: - Shortest register to register delay is 1.358 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 2: + IC(0.397 ns) + CELL(0.366 ns) = 0.763 ns; Loc. = LCCOMB_X27_Y23_N10; Fanout = 1; COMB Node = 'wover2~47'
Info: 3: + IC(0.249 ns) + CELL(0.346 ns) = 1.358 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 0.712 ns ( 52.43 % )
Info: Total interconnect delay = 0.646 ns ( 47.57 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 188 non-operational path(s) clocked by clock "RD" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "write1" and destination pin or register "wover1" for clock "RD" (Hold time is 5.032 ns)
Info: + Largest clock skew is 6.452 ns
Info: + Longest clock path from clock "RD" to destination register is 9.149 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(1.149 ns) + CELL(0.366 ns) = 2.324 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.665 ns) + CELL(0.228 ns) = 3.217 ns; Loc. = LCCOMB_X26_Y23_N22; Fanout = 5; COMB Node = 'WideOr1~33'
Info: 4: + IC(0.242 ns) + CELL(0.225 ns) = 3.684 ns; Loc. = LCCOMB_X26_Y23_N24; Fanout = 1; COMB Node = 'WideOr0'
Info: 5: + IC(0.225 ns) + CELL(0.225 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y23_N16; Fanout = 10; REG Node = 'write1'
Info: 6: + IC(0.906 ns) + CELL(0.712 ns) = 5.752 ns; Loc. = LCFF_X27_Y16_N21; Fanout = 2; REG Node = 'wlh1[1]'
Info: 7: + IC(0.272 ns) + CELL(0.366 ns) = 6.390 ns; Loc. = LCCOMB_X27_Y16_N10; Fanout = 2; COMB Node = 'set1[8]~153'
Info: 8: + IC(1.082 ns) + CELL(0.366 ns) = 7.838 ns; Loc. = LCCOMB_X27_Y16_N18; Fanout = 1; COMB Node = 'wover1~48'
Info: 9: + IC(1.083 ns) + CELL(0.228 ns) = 9.149 ns; Loc. = LCCOMB_X27_Y16_N16; Fanout = 2; REG Node = 'wover1'
Info: Total cell delay = 3.525 ns ( 38.53 % )
Info: Total interconnect delay = 5.624 ns ( 61.47 % )
Info: - Shortest clock path from clock "RD" to source register is 2.697 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(0.909 ns) + CELL(0.225 ns) = 1.943 ns; Loc. = LCCOMB_X26_Y23_N0; Fanout = 5; COMB Node = 'Decoder0~411'
Info: 3: + IC(0.251 ns) + CELL(0.053 ns) = 2.247 ns; Loc. = LCCOMB_X26_Y23_N24; Fanout = 1; COMB Node = 'WideOr0'
Info: 4: + IC(0.225 ns) + CELL(0.225 ns) = 2.697 ns; Loc. = LCCOMB_X26_Y23_N16; Fanout = 10; REG Node = 'write1'
Info: Total cell delay = 1.312 ns ( 48.65 % )
Info: Total interconnect delay = 1.385 ns ( 51.35 % )
Info: - Micro clock to output delay of source is 0.000 ns
Info: - Shortest register to register delay is 1.420 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y23_N16; Fanout = 10; REG Node = 'write1'
Info: 2: + IC(0.926 ns) + CELL(0.053 ns) = 0.979 ns; Loc. = LCCOMB_X27_Y16_N8; Fanout = 1; COMB Node = 'wover1~47'
Info: 3: + IC(0.216 ns) + CELL(0.225 ns) = 1.420 ns; Loc. = LCCOMB_X27_Y16_N16; Fanout = 2; REG Node = 'wover1'
Info: Total cell delay = 0.278 ns ( 19.58 % )
Info: Total interconnect delay = 1.142 ns ( 80.42 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 185 non-operational path(s) clocked by clock "A1" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "cmd1[5]" and destination pin or register "set1[9]" for clock "A1" (Hold time is 4.817 ns)
Info: + Largest clock skew is 6.166 ns
Info: + Longest clock path from clock "A1" to destination register is 9.310 ns
Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_B10; Fanout = 7; CLK Node = 'A1'
Info: 2: + IC(1.071 ns) + CELL(0.053 ns) = 1.896 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.665 ns) + CELL(0.228 ns) = 2.789 ns; Loc. = LCCOMB_X26_Y23_N22; Fanout = 5; COMB Node = 'WideOr1~33'
Info: 4: + IC(0.242 ns) + CELL(0.225 ns) = 3.256 ns; Loc. = LCCOMB_X26_Y23_N24; Fanout = 1; COMB Node = 'WideOr0'
Info: 5: + IC(0.225 ns) + CELL(0.225 ns) = 3.706 ns; Loc. = LCCOMB_X26_Y23_N16; Fanout = 10; REG Node = 'write1'
Info: 6: + IC(0.906 ns) + CELL(0.712 ns) = 5.324 ns; Loc. = LCFF_X27_Y16_N21; Fanout = 2; REG Node = 'wlh1[1]'
Info: 7: + IC(0.272 ns) + CELL(0.366 ns) = 5.962 ns; Loc. = LCCOMB_X27_Y16_N10; Fanout = 2; COMB Node = 'set1[8]~153'
Info: 8: + IC(2.197 ns) + CELL(0.000 ns) = 8.159 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'set1[8]~153clkctrl'
Info: 9: + IC(0.923 ns) + CELL(0.228 ns) = 9.310 ns; Loc. = LCCOMB_X25_Y20_N16; Fanout = 3; REG Node = 'set1[9]'
Info: Total cell delay = 2.809 ns ( 30.17 % )
Info: Total interconnect delay = 6.501 ns ( 69.83 % )
Info: - Shortest clock path from clock "A1" to source register is 3.144 ns
Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_B10; Fanout = 7; CLK Node = 'A1'
Info: 2: + IC(1.071 ns) + CELL(0.053 ns) = 1.896 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.247 ns) + CELL(0.225 ns) = 2.368 ns; Loc. = LCCOMB_X26_Y20_N16; Fanout = 7; REG Node = 'cmd[5]'
Info: 4: + IC(0.231 ns) + CELL(0.053 ns) = 2.652 ns; Loc. = LCCOMB_X26_Y20_N28; Fanout = 5; COMB Node = 'cmd1[1]~0'
Info: 5: + IC(0.264 ns) + CELL(0.228 ns) = 3.144 ns; Loc. = LCCOMB_X26_Y20_N6; Fanout = 12; REG Node = 'cmd1[5]'
Info: Total cell delay = 1.331 ns ( 42.33 % )
Info: Total interconnect delay = 1.813 ns ( 57.67 % )
Info: - Micro clock to output delay of source is 0.000 ns
Info: - Shortest register to register delay is 1.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y20_N6; Fanout = 12; REG Node = 'cmd1[5]'
Info: 2: + IC(0.389 ns) + CELL(0.366 ns) = 0.755 ns; Loc. = LCCOMB_X25_Y20_N18; Fanout = 1; COMB Node = 'Mux63~14'
Info: 3: + IC(0.248 ns) + CELL(0.346 ns) = 1.349 ns; Loc. = LCCOMB_X25_Y20_N16; Fanout = 3; REG Node = 'set1[9]'
Info: Total cell delay = 0.712 ns ( 52.78 % )
Info: Total interconnect delay = 0.637 ns ( 47.22 % )
Info: + Micro hold delay of destination is 0.000 ns
Warning: Circuit may not operate. Detected 184 non-operational path(s) clocked by clock "A0" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "cmd1[5]" and destination pin or register "set1[9]" for clock "A0" (Hold time is 4.817 ns)
Info: + Largest clock skew is 6.166 ns
Info: + Longest clock path from clock "A0" to destination register is 9.615 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_B9; Fanout = 7; CLK Node = 'A0'
Info: 2: + IC(1.167 ns) + CELL(0.225 ns) = 2.201 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.665 ns) + CELL(0.228 ns) = 3.094 ns; Loc. = LCCOMB_X26_Y23_N22; Fanout = 5; COMB Node = 'WideOr1~33'
Info: 4: + IC(0.242 ns) + CELL(0.225 ns) = 3.561 ns; Loc. = LCCOMB_X26_Y23_N24; Fanout = 1; COMB Node = 'WideOr0'
Info: 5: + IC(0.225 ns) + CELL(0.225 ns) = 4.011 ns; Loc. = LCCOMB_X26_Y23_N16; Fanout = 10; REG Node = 'write1'
Info: 6: + IC(0.906 ns) + CELL(0.712 ns) = 5.629 ns; Loc. = LCFF_X27_Y16_N21; Fanout = 2; REG Node = 'wlh1[1]'
Info: 7: + IC(0.272 ns) + CELL(0.366 ns) = 6.267 ns; Loc. = LCCOMB_X27_Y16_N10; Fanout = 2; COMB Node = 'set1[8]~153'
Info: 8: + IC(2.197 ns) + CELL(0.000 ns) = 8.464 ns; Loc. = CLKCTRL_G6; Fanout = 8; COMB Node = 'set1[8]~153clkctrl'
Info: 9: + IC(0.923 ns) + CELL(0.228 ns) = 9.615 ns; Loc. = LCCOMB_X25_Y20_N16; Fanout = 3; REG Node = 'set1[9]'
Info: Total cell delay = 3.018 ns ( 31.39 % )
Info: Total interconnect delay = 6.597 ns ( 68.61 % )
Info: - Shortest clock path from clock "A0" to source register is 3.449 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_B9; Fanout = 7; CLK Node = 'A0'
Info: 2: + IC(1.167 ns) + CELL(0.225 ns) = 2.201 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.247 ns) + CELL(0.225 ns) = 2.673 ns; Loc. = LCCOMB_X26_Y20_N16; Fanout = 7; REG Node = 'cmd[5]'
Info: 4: + IC(0.231 ns) + CELL(0.053 ns) = 2.957 ns; Loc. = LCCOMB_X26_Y20_N28; Fanout = 5; COMB Node = 'cmd1[1]~0'
Info: 5: + IC(0.264 ns) + CELL(0.228 ns) = 3.449 ns; Loc. = LCCOMB_X26_Y20_N6; Fanout = 12; REG Node = 'cmd1[5]'
Info: Total cell delay = 1.540 ns ( 44.65 % )
Info: Total interconnect delay = 1.909 ns ( 55.35 % )
Info: - Micro clock to output delay of source is 0.000 ns
Info: - Shortest register to register delay is 1.349 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y20_N6; Fanout = 12; REG Node = 'cmd1[5]'
Info: 2: + IC(0.389 ns) + CELL(0.366 ns) = 0.755 ns; Loc. = LCCOMB_X25_Y20_N18; Fanout = 1; COMB Node = 'Mux63~14'
Info: 3: + IC(0.248 ns) + CELL(0.346 ns) = 1.349 ns; Loc. = LCCOMB_X25_Y20_N16; Fanout = 3; REG Node = 'set1[9]'
Info: Total cell delay = 0.712 ns ( 52.78 % )
Info: Total interconnect delay = 0.637 ns ( 47.22 % )
Info: + Micro hold delay of destination is 0.000 ns
Warning: Circuit may not operate. Detected 185 non-operational path(s) clocked by clock "CS" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "write2" and destination pin or register "wover2" for clock "CS" (Hold time is 4.874 ns)
Info: + Largest clock skew is 6.232 ns
Info: + Longest clock path from clock "CS" to destination register is 8.966 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A8; Fanout = 7; CLK Node = 'CS'
Info: 2: + IC(1.216 ns) + CELL(0.228 ns) = 2.301 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.776 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.716 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.320 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.781 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.550 ns) + CELL(0.225 ns) = 5.556 ns; Loc. = LCCOMB_X27_Y19_N28; Fanout = 5; REG Node = 'cmd2[4]'
Info: 8: + IC(0.689 ns) + CELL(0.228 ns) = 6.473 ns; Loc. = LCCOMB_X27_Y23_N8; Fanout = 2; COMB Node = 'set2[8]~153'
Info: 9: + IC(1.039 ns) + CELL(0.225 ns) = 7.737 ns; Loc. = LCCOMB_X27_Y23_N14; Fanout = 1; COMB Node = 'wover2~48'
Info: 10: + IC(1.001 ns) + CELL(0.228 ns) = 8.966 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 3.133 ns ( 34.94 % )
Info: Total interconnect delay = 5.833 ns ( 65.06 % )
Info: - Shortest clock path from clock "CS" to source register is 2.734 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A8; Fanout = 7; CLK Node = 'CS'
Info: 2: + IC(0.914 ns) + CELL(0.228 ns) = 1.999 ns; Loc. = LCCOMB_X26_Y23_N20; Fanout = 5; COMB Node = 'Decoder0~414'
Info: 3: + IC(0.228 ns) + CELL(0.053 ns) = 2.280 ns; Loc. = LCCOMB_X26_Y23_N18; Fanout = 1; COMB Node = 'WideOr1'
Info: 4: + IC(0.229 ns) + CELL(0.225 ns) = 2.734 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: Total cell delay = 1.363 ns ( 49.85 % )
Info: Total interconnect delay = 1.371 ns ( 50.15 % )
Info: - Micro clock to output delay of source is 0.000 ns
Info: - Shortest register to register delay is 1.358 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y23_N8; Fanout = 10; REG Node = 'write2'
Info: 2: + IC(0.397 ns) + CELL(0.366 ns) = 0.763 ns; Loc. = LCCOMB_X27_Y23_N10; Fanout = 1; COMB Node = 'wover2~47'
Info: 3: + IC(0.249 ns) + CELL(0.346 ns) = 1.358 ns; Loc. = LCCOMB_X27_Y23_N12; Fanout = 2; REG Node = 'wover2'
Info: Total cell delay = 0.712 ns ( 52.43 % )
Info: Total interconnect delay = 0.646 ns ( 47.57 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock "clk0" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source pin or register "cnt0[13]~reg0" and destination pin or register "buffer[13]" for clock "clk0" (Hold time is 4.586 ns)
Info: + Largest clock skew is 5.273 ns
Info: + Longest clock path from clock "clk0" to destination register is 7.867 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_C7; Fanout = 16; CLK Node = 'clk0'
Info: 2: + IC(1.119 ns) + CELL(0.712 ns) = 2.688 ns; Loc. = LCFF_X30_Y18_N11; Fanout = 10; REG Node = 'cnt0[5]~reg0'
Info: 3: + IC(0.326 ns) + CELL(0.225 ns) = 3.239 ns; Loc. = LCCOMB_X31_Y18_N24; Fanout = 1; COMB Node = 'buffer~68'
Info: 4: + IC(0.215 ns) + CELL(0.225 ns) = 3.679 ns; Loc. = LCCOMB_X31_Y18_N8; Fanout = 1; COMB Node = 'buffer~69'
Info: 5: + IC(0.585 ns) + CELL(0.366 ns) = 4.630 ns; Loc. = LCCOMB_X27_Y18_N2; Fanout = 1; COMB Node = 'buffer~0'
Info: 6: + IC(2.085 ns) + CELL(0.000 ns) = 6.715 ns; Loc. = CLKCTRL_G7; Fanout = 16; COMB Node = 'buffer~0clkctrl'
Info: 7: + IC(0.927 ns) + CELL(0.225 ns) = 7.867 ns; Loc. = LCCOMB_X31_Y18_N2; Fanout = 2; REG Node = 'buffer[13]'
Info: Total cell delay = 2.610 ns ( 33.18 % )
Info: Total interconnect delay = 5.257 ns ( 66.82 % )
Info: - Shortest clock path from clock "clk0" to source register is 2.594 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_C7; Fanout = 16; CLK Node = 'clk0'
Info: 2: + IC(1.119 ns) + CELL(0.618 ns) = 2.594 ns; Loc. = LCFF_X30_Y18_N27; Fanout = 8; REG Node = 'cnt0[13]~reg0'
Info: Total cell delay = 1.475 ns ( 56.86 % )
Info: Total interconnect delay = 1.119 ns ( 43.14 % )
Info: - Micro clock to output delay of source is 0.094 ns
Info: - Shortest register to register delay is 0.593 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y18_N27; Fanout = 8; REG Node = 'cnt0[13]~reg0'
Info: 2: + IC(0.365 ns) + CELL(0.228 ns) = 0.593 ns; Loc. = LCCOMB_X31_Y18_N2; Fanout = 2; REG Node = 'buffer[13]'
Info: Total cell delay = 0.228 ns ( 38.45 % )
Info: Total interconnect delay = 0.365 ns ( 61.55 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: tsu for register "cmd[2]" (data pin = "datain[2]", clock pin = "A1") is 4.878 ns
Info: + Longest pin to register delay is 6.652 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_A6; Fanout = 7; PIN Node = 'datain[2]'
Info: 2: + IC(5.567 ns) + CELL(0.228 ns) = 6.652 ns; Loc. = LCCOMB_X25_Y20_N12; Fanout = 4; REG Node = 'cmd[2]'
Info: Total cell delay = 1.085 ns ( 16.31 % )
Info: Total interconnect delay = 5.567 ns ( 83.69 % )
Info: + Micro setup delay of destination is 0.505 ns
Info: - Shortest clock path from clock "A1" to destination register is 2.279 ns
Info: 1: + IC(0.000 ns) + CELL(0.772 ns) = 0.772 ns; Loc. = PIN_B10; Fanout = 7; CLK Node = 'A1'
Info: 2: + IC(1.071 ns) + CELL(0.053 ns) = 1.896 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.330 ns) + CELL(0.053 ns) = 2.279 ns; Loc. = LCCOMB_X25_Y20_N12; Fanout = 4; REG Node = 'cmd[2]'
Info: Total cell delay = 0.878 ns ( 38.53 % )
Info: Total interconnect delay = 1.401 ns ( 61.47 % )
Info: tco from clock "RD" to destination pin "dataout[1]" through register "dataout[1]$latch" is 14.082 ns
Info: + Longest clock path from clock "RD" to source register is 10.104 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(1.149 ns) + CELL(0.366 ns) = 2.324 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.799 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.739 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.343 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.236 ns) + CELL(0.225 ns) = 4.804 ns; Loc. = LCCOMB_X27_Y20_N20; Fanout = 5; COMB Node = 'cmd2[1]~0'
Info: 7: + IC(0.628 ns) + CELL(0.225 ns) = 5.657 ns; Loc. = LCCOMB_X27_Y23_N22; Fanout = 12; REG Node = 'cmd2[5]'
Info: 8: + IC(0.648 ns) + CELL(0.225 ns) = 6.530 ns; Loc. = LCCOMB_X27_Y19_N8; Fanout = 2; COMB Node = 'dataout[2]~1605'
Info: 9: + IC(0.249 ns) + CELL(0.228 ns) = 7.007 ns; Loc. = LCCOMB_X27_Y19_N24; Fanout = 1; COMB Node = 'Mux10~83'
Info: 10: + IC(2.036 ns) + CELL(0.000 ns) = 9.043 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'Mux10~83clkctrl'
Info: 11: + IC(0.907 ns) + CELL(0.154 ns) = 10.104 ns; Loc. = LCCOMB_X29_Y20_N0; Fanout = 1; REG Node = 'dataout[1]$latch'
Info: Total cell delay = 3.149 ns ( 31.17 % )
Info: Total interconnect delay = 6.955 ns ( 68.83 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Longest register to pin delay is 3.978 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X29_Y20_N0; Fanout = 1; REG Node = 'dataout[1]$latch'
Info: 2: + IC(1.834 ns) + CELL(2.144 ns) = 3.978 ns; Loc. = PIN_P2; Fanout = 0; PIN Node = 'dataout[1]'
Info: Total cell delay = 2.144 ns ( 53.90 % )
Info: Total interconnect delay = 1.834 ns ( 46.10 % )
Info: th for register "wover0" (data pin = "WR", clock pin = "RD") is 4.912 ns
Info: + Longest clock path from clock "RD" to destination register is 8.329 ns
Info: 1: + IC(0.000 ns) + CELL(0.809 ns) = 0.809 ns; Loc. = PIN_C9; Fanout = 7; CLK Node = 'RD'
Info: 2: + IC(1.149 ns) + CELL(0.366 ns) = 2.324 ns; Loc. = LCCOMB_X26_Y20_N18; Fanout = 9; COMB Node = 'Decoder0~415'
Info: 3: + IC(0.250 ns) + CELL(0.225 ns) = 2.799 ns; Loc. = LCCOMB_X26_Y20_N22; Fanout = 20; REG Node = 'cmd[6]'
Info: 4: + IC(0.594 ns) + CELL(0.346 ns) = 3.739 ns; Loc. = LCCOMB_X27_Y20_N22; Fanout = 1; COMB Node = 'WideOr7~301'
Info: 5: + IC(0.258 ns) + CELL(0.346 ns) = 4.343 ns; Loc. = LCCOMB_X27_Y20_N2; Fanout = 4; COMB Node = 'WideOr7~302'
Info: 6: + IC(0.238 ns) + CELL(0.225 ns) = 4.806 ns; Loc. = LCCOMB_X27_Y20_N18; Fanout = 5; COMB Node = 'cmd0[1]~0'
Info: 7: + IC(0.605 ns) + CELL(0.053 ns) = 5.464 ns; Loc. = LCCOMB_X27_Y19_N4; Fanout = 13; REG Node = 'cmd0[5]'
Info: 8: + IC(0.264 ns) + CELL(0.228 ns) = 5.956 ns; Loc. = LCCOMB_X27_Y19_N2; Fanout = 2; COMB Node = 'set0[8]~157'
Info: 9: + IC(1.093 ns) + CELL(0.225 ns) = 7.274 ns; Loc. = LCCOMB_X27_Y19_N22; Fanout = 1; COMB Node = 'wover0~48'
Info: 10: + IC(1.002 ns) + CELL(0.053 ns) = 8.329 ns; Loc. = LCCOMB_X27_Y19_N20; Fanout = 2; REG Node = 'wover0'
Info: Total cell delay = 2.876 ns ( 34.53 % )
Info: Total interconnect delay = 5.453 ns ( 65.47 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: - Shortest pin to register delay is 3.417 ns
Info: 1: + IC(0.000 ns) + CELL(0.857 ns) = 0.857 ns; Loc. = PIN_B8; Fanout = 7; CLK Node = 'WR'
Info: 2: + IC(0.900 ns) + CELL(0.053 ns) = 1.810 ns; Loc. = LCCOMB_X26_Y23_N2; Fanout = 12; COMB Node = 'Decoder0'
Info: 3: + IC(0.694 ns) + CELL(0.228 ns) = 2.732 ns; Loc. = LCCOMB_X27_Y19_N12; Fanout = 1; COMB Node = 'wover0~47'
Info: 4: + IC(0.460 ns) + CELL(0.225 ns) = 3.417 ns; Loc. = LCCOMB_X27_Y19_N20; Fanout = 2; REG Node = 'wover0'
Info: Total cell delay = 1.363 ns ( 39.89 % )
Info: Total interconnect delay = 2.054 ns ( 60.11 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 138 warnings
Info: Allocated 143 megabytes of memory during processing
Info: Processing ended: Mon Apr 19 14:44:03 2010
Info: Elapsed time: 00:00:02